Low Leakage and High Density 4T CMOS SRAM in 45nm Technology

HCTL Open International Journal of Technology Innovations and Research (IJTIR)
http://ijtir.hctl.org
Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
Low Leakage and High

Density 4T CMOS SRAM in
45nm Technology
Puna Kumar Rajak1, Dr. S. N. Singh2, Amit Kumar Rajak3,
Sravan Kumar Kankanala4
puna.itgpa@gmail.com
Abstract
This paper presents a novel CMOS based 4T SRAM, it is highly dense and capable
for low power application. The Novel 4T SRAM consumes less power and has less
leakage current as well as less read and write time. It is capable of storing the bits
efficiently. The novel cell size is 26.46% smaller than the conventional sixtransistor SRAM cell using same design rules without any performance
degradation. The simulation result of 4T SRAM show that there is extensive
enhancement in performance of the proposed circuit parameters like delay, power
consumption and leakage current. The Novel 4T SRAM has been analysed on
Cadence Virtuoso v6.1.5 in 45 nm Technology.
Keywords
CMOS 4T SRAM, cell delay, Low leakage, low power consumption, 45nm technology.
Introduction
Static RAM is widely used in battery operated Embedded System. Where, we need to
operate device at low power consumption and its required less area as well as power
efficient. Static RAM used in processors is very fast as compared to other memory
storage medium as it needs less read and write timing [1]. Low power SRAMs have turn
into a significant part of many VLSI circuits because of its storage application. Rising size
of on-chip memories particularly on components like microprocessors, makes SRAMs a
significant circuit, since its power consumption is high as compared to other circuit due to
large number of cells used. Its high usage in processors makes it crucial circuit that
decides the speed of processor. Also in different VLSI chips, the power dissipation has
turn into a significant consideration due to the improved integration, operational speeds
and the volatile enlargement of portable appliances. With enhance in number of memory
cells, additional power will be consumed still in the standby mode. The memory cells are
frequently implemented by arrays of compactly packed SRAM cells for high performance,
a lesser amount of leakage and power consumption optimizing the cell ratio of the cell
and getting better the peripheral circuitry like precharge circuitry, write circuitry, sense
amplifier etc. Cell ratio plays an significant role in stabilizing the output of the cell [2]. The
proposed cell is using a lesser amount of power supply, since the technology is scaled
one. There are numerous configurations of memory cell that has been proposed.
Puna Kumar Rajak, Dr. S. N. Singh, Amit Kumar Rajak, Sravan Kumar Kankanala,
Low Leakage and High Density 4T CMOS SRAM in 45nm Technology.
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Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
Conventional CMOS 6T SRAM cell is power competent in standby mode and has
improved protection to transient noise and voltage variation than four transistor resistive
load cell. That's why it is ideal over resistive load cell for high speed and low power
applications [5]. Stable Data withholding remains, the main purpose when scheming any
configuration of memory cell. Generally majority of the bits stored are '0'. To read a bit in
the conventional 6T SRAM cell one of two bit-lines must be discharged to low apart from
of written value. Due to balance in configuration the power consumption in both writing '0'
and ' l' are the usually same. This is also true in case of read operation. Since in cell, an
irresistible majority of the write and read bits are 0, transitions always take place on bit
lines in both writing '0' and reading '0'. Hence this causes high dynamic power
consumption during read/write operation in conventional 6T SRAM cell [2]. Our intention
is to develop a SRAM cell with four transistors to decrease the cell area size with better
performance and power consumption enhancement. In section II the 6T SRAM cell is
presented. Section III represents the novel 4T configuration of the cell. This segment also
discusses the working of the cell. Segment IV discuss about the read and write operation
of the proposed cell. Segment V discusses the leakage current of the cell and its
calculation. Segment VI discusses about the delay at different nodes of the cell. Segment
VII discusses about the circuitry of the cell including precharge, write and sense amplifier
circuitry. Segment VIII throws light on the power consumption of the cell and its
calculation at different nodes. Segment IX shows the layout of proposed cell. Conclusions
are drawn in the last segment.
Conventional 6T SRAM Configuration

Static read/write (or random access) memory (SRAM) is able to read and write data into its
memory cells and retain the memory contents as long as the power supply voltage is
provided. Currently SRAM are manufactured in the CMOS technology which offers very
low static power dissipation, superior noise margin and switching speed. The cells of the
CMOS SRAM are based on a simple latch circuit. The conventional six-transistor (6T)
SRAM is developed of two cross-coupled inverters and two access transistors, linking the
cell to the bit lines. The inverters constitute the storage element and the access transistors
are used to approach the outside. The cell is symmetrical and has a comparatively large
area. No special process steps are needed and it is fully compatible with standard CMOS
processes.
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Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
Figure 1: Conventional 6T SRAM Cell [3]
Proposed 4T SRAM Cell
Figure 2: A proposed 4T SRAM cell in 45 nm Technology

A proposed circuit configuration of 4T SRAM is shown in fig. 2. In this circuit instead of
NMOS, PMOS is used as a pass transistor. Stored bit are available at nodes ST and STB.
PM2 (pass transistor) is key factor through which we invoked data read and write
operation at BL (bit line) whose controlling signal is WL (word line). In inactive mode of
cell (when read or write operation not perform) PM2 is OFF. When 0 stored at ST node
PM0 is ON and STB node pulled up to VDD. When 1 stored at ST node NM0 is ON and
STB node pulled down to GND. As STB node goes low then PM1 will be ON and ST
node pulled up to GND (where transistor PM1 is used as refresh circuit). Signal high
stored at ST node uses leakage current at input-output point BL (BL is precharge with
VDD) through pass transistor PM2.
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Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
Figure 3 and figure 4 shows the transient analysis of the cell when bit 0 and bit 1is
written to the cell respectively. Pass transistor PM2 (via WL signals) is kept in ON
condition. And the required signal (1 in case of writing 1 and 0 in case of writing 0) to
be written is connected to Bit Line through write circuitry, where Bit Line is floated earlier
than this step. It has been found that the bits are efficiently stored and are stable.
Figure 3: Waveform of new cell with write 0.
Figure 4: Waveform of new cell with write 1.
Read and Write Operation

Waveforms of Write 0 and write 1 are shown in Fig. 3 and Fig. 4. During write operation
Pass transistor PM2 is ON and subsequent operations are performed on different
transistors and nodes in the proposed SRAM cell:
1) Bit-line driving: For the write operation, information (data) is set on bit-line (BL), and
then word-line (WL) asserted to GND.
2) Cell flipping: This step includes two states as follows:
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Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
a) Data is zero: In this state, ST node pulled up to GND by pass transistor PM2, and
therefore the Load transistor PM0 will be ON, and STB node will be pulled up to VDD.
b) Data is one: In this state, ST node pulled up to VDD by pass transistor PM2, and
therefore the drive transistor NM0 will be ON, and STB node will be pulled down to GND
and positive feedback created by PM1 and NM0.
3) Bit-line driving: At the end of write operation, cell will go to idle mode and WL and bitline asserted to VDD and VDD, respectively.
During read operation we look following steps:
1) Bit-line charging: For a read, bit-line is charged to VDD, and then floated.
2) Word-line activation: In this step WL is asserted to GND and two states can be
considered:
a) Voltage of ST node is high: When voltage of ST node is high, the voltage of bit-line is
pulled down to high and this voltage is sensed by sense amplifier.
b) Voltage of ST node is low: When voltage of ST node is low, the voltage of bit-line
pulled up to low voltage by the pass transistor which is sensed by the sense amplifier.
3) Sensing: Figure 6 shows possible circuit schematic of sense amplifier in 45nm
technology node that may be used for reading data from new cell [2]. Sense amplifier
sense signal from bit line and gives the output at bit (DO) and bit complement (DOC).
4) Idle mode: At the end of read operation, cell will go to idle mode and bit-line asserted to
VDD.
Figure 5: Sense amplifier schematic of proposed cell [3]

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Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
Figure 6 shows the simulation result of reading signals from the proposed 4T SRAM cell.
Where, ST and STB nodes hold information during read operation. WL (word Line) is
describing controlling signal of pass transistor PM2.
Figure 6: Reading data from the proposed SRAM cell
Leakage Current
In one state, novel 4T SRAM cell must retains its data using the leakage current
of the pass or access transistor (when zero stored) and in the other state the ST
SRAM cell must retains its data using positive feedback (when one stored). Table I
shows the comparison of leakage current of the previous 5T cells and conventional 6T
cells with the proposed 4T SRAM cell. An additional benefit of using this cell is that we
can use conventional pre-charge circuitry for this SRAM cell. The simulated results shows
that this cell is having very less leakage current that is a advantage to battery operated
devices. The simulated leakage current is shown in Fig. 7 and Fig. 8.
Table I. Leakage comparison of the proposed cell with the previous results
Sr.
No.
Parameters
For write 1
in st node
For write 0
in st node
For write 1
in stb node
For write 0
in stb node
2
3
4
Leakage
in
previous
5T cell[3]
6.61 pA
Leakage
in 6T
cell. [3]
Leakage in
proposed
4T cell
-32.10 nA
-7.58 nA
5.14 pA
9.20 nA
0.987 nA
-475.88 fA
-0.229 nA
-4.419 nA
-5.415 pA
94.11 nA
0.62 nA
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Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
Figure 7: Leakages at various nodes during write 0
Figure 8: Leakages at various nodes during write 1.
Delay
Delay of the cell depends on the consumption of time between the cells from
input (BL) to output [6]. Assessment of the cell delay between 5T , 6T & 4T shows in
the table below.
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Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
Table I. Delay comparison of the proposed cell with the previous cells.
Sl. No.
Parameters
Delay of
previous
5T cell
[2]
Delay of
conventional
6T cell [2]
Delay at
ST
Delay at
STB
2.453 ns
14.24 ps
0.839 ns
Delay of
new 5T
SRAM
cell
(180nm)[3]
23 ps
Delay of
new 5T
SRAM
cell
(45nm)[3]
5.13 ps
Delay of
new 4T
SRAM
cell
(45nm)
2.853ps
47.72 ps
46 ps
17.66 ps
16.62ps
This table shows that 4T cell delay in ST and STB node is less than 6T cell delay
in ST and STB node. It means 4T is superior to 6T.
SRAM Schematic
The possible schematic of sense amplifier for the proposed SRAM is shown in Fig. 6 [2].
The DC and transient response of the sense amplifier schematic is shown in Fig. 9. From
Fig. 9, we can say that this amplifier is close to idle switch characteristics.
Figure 10 shows the circuitry of memory cell as well as proposed SRAM cell, precharge,
write and sense amplifier circuitry.
Figure 9: DC and transient analysis of sense amplifiers
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Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
Figure 10: Circuitry of memory cell including 4T SRAM cell, pre-charge, write and sense
amplifier circuitry.
Power Consumption
Power consumption of the SRAM memory cell depends on the consumption of the power
of the active transistor (under operation) [4]. Power consumption of the 4T SRAM cell is
shows in the table below.
Sr.
No.
Parameters Power
Power
Consumption Consumption
in
in 6T cell [3]
previous 5T
cell [3]
For write 1
6.62 pW
0.011 pW
in st node
Power
Consumption
in proposed
4T cell
2.66 fW
For write 0
in st node
0.465 pW
0.003 pW
4.52 fW
For write 1
in stb node
5.14 pW
30 pW
0.014 fW
For write 0
in stb node
5.422 pW
28 pW
0.005 fW
Layout
Figure 11 shows the layout of the proposed 4T SRAM cell in 45nm technology node.
Length where fixed and widths as in schematic have been used in making this layout.
Pass transistor uses large widths as compared to other cells. The proposed 4T cell
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Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
requires 2.53 m 2 areas. 6T cell requires 3.438 m2 areas [2]. Hence the proposed cell is
26.46 % less than the conventional 6T SRAM cell and it is 2.69% smaller than the
previous 5T configuration [3].
Figure 11: Layout of proposed 4T SRAM cell in 45nm technology node.
Conclusion
With the goal of achieving a low leakage and high density
memory cell, we
developed a 4T CMOS SRAM cell. Leakage current found during write 0 or 1 at node
in which the transistor is OFF. Hence the proposed cell is 26.46 % less than the
conventional 6T SRAM cell and it is 2.69% smaller than the previous 5T configuration.
Proposed 4T SRAM is faster than the conventional 6T SRAM cell. Power consumption is
decreases in huge amount as compared to 6T and 5T.
Acknowledgements
This work has done in the VLSI Lab at NIT Jamshedpur. Professor and Head of the
Department provided us cadence environment to complete this work.
References
[1] K. Khare, N. Khare, V.K. Kulhade and P. Deshpande, VLSI Design And Analysis of
Low Power 6T SRAM Cell Using Cadence Tool, IEEE International Conference
on
Semiconductor Electronics, Nov. 2008, pp. 117121.
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Volume 15, May 2015
e-ISSN: 2321-1814, ISBN (Print): 978-1-62951-974-6
[2] S. Akashe, S. Bhushan and S. Sharma, High Density and Low Leakage Current
Based 5T SRAM Cell Using 45 nm Technology, International Conference on
Nanoscience, Engineering and Technology (ICONSET), Nov. 2011. pp. 346-350.
[3] Rohin Gupta, Sandeep Singh Gill, Navneet Kaur, A Novel Low Leakage and High
Density 5T CMOS SRAM Cell in 45nm Technology, IEEE Conference
Publication,
2014, Page(s): 1-6.
[4] J. M. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits, 2nd ed.,
Prentice-Hall of India Private limited, 2005, pp. 272-282.
[5] V.S. Babu, Solid State Device and Technology, 3rd ed., Pearson Publication, 2008.
[6] K. Martin, Digital Integrated Circuit Design, Oxford University Press, New York, 2000.
This article is an open access article distributed under the terms and conditions of the
Creative Commons Attribution 4.0 International License
(https://creativecommons.org/licenses/by/4.0/).
2015 by the Authors. Licensed by HCTL Open, India.
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