1.

Entity pgblock is
Port ( a: in std_logic;
b: in std_logic;
g0 : out std_logic;
p0: out std_logic);
end pgblock;
architecture Behavioral of pgcell is
g0 <=( a and b);
p0 <= (a xor b);
end behavioral;

2. entity blackcell is
port (g0 : in std_logic;
p0 : in std_logic;
g1 : in std_logic;
p1 : in std_logic;
G : out STD_LOGIC;
P : out STD_LOGIC);
end blackcell ;
architecture Behavioral of blackcell is
G <=( g1 or(g0 and p1));
P <= (p0 and p1);
End behavioral;

3. Entity SUMBLOCK is

port ( P: in std_logic;
c: in std_logic
sum : out std_logic);
end sumblock;
architecture Behavioral of sumblock is
sum <= (P xor c);
end behavioral;

4. Entity buffer is
Port ( G : in std_logic;
c : out std_logic);
end buffer;
architecture Behavioral of buffer is
c := G;
end behavioral;

entity Brent_kung is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);

b : in STD_LOGIC_VECTOR (15 downto 0);

cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR (15 downto 0);
cout : out STD_LOGIC);
end Brent_kung;

architecture Behavioral of Brent_kung is

component buffer is
Port (G : in std_logic;
c : out std_logic);
end component;

Component blackcell is
Port ( g0 : in std_logic;
p0 : in std_logic;
g1 : in std_logic;
p1 : in std_logic;
G : out STD_LOGIC;
P : out STD_LOGIC);
end Component;

Component pgblock is
Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
b : in STD_LOGIC_VECTOR (15downto 0);
g0 : out STD_LOGIC_VECTOR (15 downto 0);
p0 : out STD_LOGIC_VECTOR (15 downto 0));

end Component;
component SUMBLOCK is
port ( P: in std_logic;
c: in std_logic
sum : out std_logic);
end component;

signal G1,P1: std_logic_vector(7 downto 0);

signal G2, P2: std_logic(3 downto 0);
signal G3,P3 : std_logic_vector(1 downto 0);
signal G4,P4 : std_logic;
signal G5,P5 : std_logic_vector(2 downto 0);
signal G6,P6: std_logic_vector (6 downto 0);
signal g0,p0: std_logic_vector(15 downto 0);
signal c : std_logic_vector(14 downto 0);

begin

k0: pgblock port map (a(0),b(0),g0(0),p0(0));

k1 : pgblock port map (a(1),b(1),g0(1),p0(1));
k2: pgblock port map (a(2),b(2),g0(2),p0(2));
k3 : pgblock port map (a(3),b(3),g0(3),p0(3));
k4: pgblock port map (a(4),b(4),g0(4),p0(4));
k5 : pgblock port map (a(5),b(5),g0(5),p0(5));
k6 : pgblock port map (a(6),b(6),g0(6),p0(6));
k7 : pgblock port map (a(8),b(8),g0(8),p0(8));

k8 : pgblock port map (a(8),b(8),g0(8),p0(8));

k9 : pgblock port map (a(9),b(9),g0(9),p0(9));
k10: pgblock port map (a(10),b(10),g0(10),p0(10));
k11: pgblock port map (a(11),b(11),g0(11),p0(11));
k12 : pgblock port map (a(12),b(12),g0(12),p0(12));
k13 : pgblock port map (a(13),b(13),g0(13),p0(13));
k14: pgblock port map (a(14),b(14),g0(14),p0(14));
k15: pgblock port map (a(15),b(15),g0(15),p0(15));
s1: graycell port map (g0(0),p0(0),cin,GC(0));
s1: blackcell port map (g0(0), p0(0), g1(1), p1(1), G1(0),P1(0));
s2: blackcell port map (g0(2), p0(2), g1(3), p1(3), G1(1),P1(1));
s3: blackcell port map (g0(4), p0(4), g1(5), p1(5), G1(2),P1(2));
s4: blackcell port map (g0(6), p0(6), g1(7), p1(7), G1(3),P1(3));
s5: blackcell port map (g0(8), p0(8), g1(9), p1(9), G1(4),P1(4));
s6: blackcell port map (g0(10), p0(10), g1(11), p1(11), G1(5),P1(5));
s7: blackcell port map (g0(12), p0(12), g1(13), p1(13), G1(6),P1(6));
s8: blackcell port map (g0(14), p0(4), g1(15), p1(15), G1(7),P1(7));
s9: blackcell port map ( G1(0),P1(0), G1(1),P1(1,) G2(0),P2(0));
s10: blackcell port map ( G1(2),P1(2), G1(3),P1(3) ,G2(1),P2(1));
s11: blackcell port map ( G1(4),P1(4), G1(5),P1(5) ,G2(2),P2(2));
s12: blackcell port map ( G1(6),P1(6), G1(7),P171), G2(3),P2(3));
s13: blackcell port map (G2(0),P2(0) ,G2(1),P2(1), G3(0),P3(0));
s14: blackcell port map (G2(2),P2(2) ,G2(3),P2(3), G3(1),P3(1));
s15: blackcell port map (G2(2),P2(2), G3(0),P3(0),G4(0),P4(0));
s16: blackcell port map (G3(0),P3(0), G3(1),P3(1),G4(1),P4(1));
s17: blackcell port map (G2(0),P2(0), G1(2),P1(2),G5(0),P5(0));

s18: blackcell port map (G3(0),P3(0), G1(5),P1(5),G5(1),P5(1));

s19: blackcell port map (G4(0),P4(0), G1(6),P1(6),G5(2),P5(2));
s20: blackcell port map (G1(0),P1(0),g0(2),p0(2),G6(0),P6(0));
s21: blackcell port map (G2(0),P2(0),g0(4),p0(4),G6(1),P6(1));
s22: blackcell port map (G5(0),P5(0),g0(6),p0(6),G6(2),P6(2));
s23: blackcell port map (G3(0),P1(0),g0(8),p0(8),G6(3),P6(3));
s24: blackcell port map(G5(1),P5(1),g0(10),p0(10),G6(4),P6(4));
s25: blackcell port map (G4(0),P1(0),g0(12),p0(12),G6(5),P6(5));
s26: blackcell port map (G5(2),P5(2),g0(14),p0(14),G6(6),P6(6));

t1 : buffer portmap (g0(0),c(0));

t2 : buffer port map (G1(0),c(1));
t3 : buffer port map (G6(0),c(2));
t4 : buffer port map (G2(0),c(3));
t5 : buffer port map (G6(1),c(4));
t6 : buffer port map (G5(0),c(5));
t7 : buffer port map (G6(2),c(6));
t8 : buffer port map (G3(0),c(7));
t9 : buffer port map (G6(3),c(8));
t10 : buffer port map (G5(1),c(9));
t11 : buffer port map (G6(4),c(10));
t12 : buffer port map (G4(0),c(11));
t13 : buffer port map (G6(5), c(12));
t14 : buffer port map (G5(2),c(13));
t15 : buffer port map (G6(6),c(14));

t16 : buffer port map (G4(1),cout);

m1 : sumblock port map (P(0),c(0),sum(0));

m2: sumblock port map (P(1),c(1),sum(1));
m3: sumblock port map (P(2),c(2),sum(2));
m4: sumblock port map (P(3),c(3),sum(3));
m5: sumblock port map (P(4),c(4),sum(4));
m6: sumblock port map (P(5),c(5),sum(5));
m7: sumblock port map (P(6),c(6),sum(6));
m8: sumblock port map (P(7),c(7),sum(7));
m9: sumblock port map (P8),c(8),sum(8));
m10: sumblock port map (P(9),c(9),sum(9));
m11: sumblock port map (P(10),c(10),sum(10));
m12: sumblock port map (P(11),c(11),sum(11));
m13: sumblock port map (P(12),c(12),sum(12));
m14: sumblock port map (P(13),c(13),sum(13));
m15: sumblock port map (P(14),c(14),sum(14));
m16: sumblock port map (P(15),cout,sum(15));
end behavioral;