INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Int. J. Circ. Theor. Appl. (2009)

Published online in Wiley InterScience (www.interscience.wiley.com). DOI: 10.1002/cta.617

LETTER TO THE EDITOR

CMOS current mirror with enhanced input dynamic range

Hung-Yu Wang1, ∗, † , Yuan-Long Jeang2 , Ying-Chuan Liu1 and Yu-Wei Huang1

1 Department of Electronic Engineering, National Kaohsiung University of Applied Sciences, 415 Chien Kung
Road, Kaohsiung 807, Taiwan
2 Department of Information Engineering, Kun Shan University, Tainan, Taiwan

SUMMARY
A novel CMOS cascode current mirror configuration with enhanced input dynamic range is presented.
The proposed mirror circuit combines the advantages of wide input swing, wide output swing and large
output resistance capability, which make it attractive for practical application. Based on 0.18 m MOS
model parameters, HSPICE simulation results show that the input current ranges from 1 A to 1 mA
with large bandwidth for the proposed circuit. The simulation results confirm the theoretical prediction.
Copyright q 2009 John Wiley & Sons, Ltd.

Received 22 April 2008; Revised 19 May 2009; Accepted 7 June 2009

KEY WORDS: current mirror; low-voltage cascode current mirror; input dynamic range; signal swing

1. INTRODUCTION

Nowadays, the demand for portable electronics has made low-power circuit design extremely
desirable. Reducing power supply voltage is a straightforward method to achieve low-power
consumption. The low-power and low-voltage CMOS techniques are applied extensively in analog
and mixed-mode circuits for the compatibility with the present IC technologies.
The current mirror (CM) is one of the most common building blocks both in analog and mixed-
mode VLSI circuits. Especially, for active elements such as op-amps, current conveyors, current
feedback amplifiers, etc., CMs are often used to produce multiple outputs as well as operate as
active loads. They are the integral parts of such components [1]. Although most CM topologies
are desired to have high output impedance and large output voltage/current signal swings [2–13],
there are certain applications, where designers are also interested in having large input swings. For
example, the X -terminal of the current conveyors, controlled current conveyors and four-terminal
floating nullors with linear current following properties requires the larger input current swing

∗ Correspondence to: Hung-Yu Wang, Department of Electronic Engineering, National Kaohsiung University of
Applied Sciences, 415 Chien Kung Road, Kaohsiung 807, Taiwan.
†
E-mail: hywang@cc.kuas.edu.tw

Copyright q 2009 John Wiley & Sons, Ltd.

 H.-Y. WANG ET AL.

thereby voltage swing for their practical application [14]. In this article, a low-power CMOS
cascode CM featuring high output impedance and large input and output signal swings is presented.
To verify its feasibility, HSPICE simulations for the proposed circuit and the popular low-voltage
cascode CM [2, 15] are carried out. The simulation results confirm our theoretical prediction.

2. PROPOSED CIRCUIT STRUCTURE

Owing to the property of large output voltage swing and small input voltage compared with a
conventional cascode CM, the low-voltage cascode CM [2, 15], as shown in Figure 1, has received
considerable attention in low-voltage/low-power circuit design. It is assumed that the mirror
transistors M1 and M2 have identical aspect ratio, i.e. AM = W1 /L 1 = W2 /L 2 , where W1 , W2 , L 1 ,
and L 2 are the transistor channel widths and lengths for the transistors M1 and M2 , respectively.
Similarly, the cascode transistors M3 and M4 are assumed to have the same aspect ratio, AC =
W3 /L 3 = W4 /L 4 . The body effect is ignored and it is assumed that all NMOS transistors have the
identical threshold voltage Vtn and transconductance parameter k. To ensure saturation of M1 and
M3 , the biasing voltage VB in Figure 1 should be
VGS3 +(VGS1 − Vtn )VB VGS1 + Vtn (1)
Equation (1) can be used to determine the input current range [15]. It can be expressed by
 √ 2
k k AC /A M
A M (VB −2Vtn ) Iin  A M (VB − Vtn )
2 2
√ (2)
2 2 1+ AC /A M
In Figure 1, as Iin increases, VGS3 and Vin will increase. Because the biasing voltage VB is fixed,
the voltage level at the drain terminal of M1 decreases. Thereby, M1 may enter into the triode
region, which determines the upper limit of Iin .
The level-shifted CM with the advantage of low input and output voltage requirements [7, 16]
is redrawn in Figure 2. Transistor M5 shifts the voltage level at the drain terminal of M1 . The
input compliance voltage (Vin1 ) is a characteristic parameter that decides the range of input voltage
swing in such circuits. The magnitude of bias current (Ibias1 ) decides the operational region of

VDD

Vo
Iin
Iout
Vin M3
VB M4
V1 V2
M1 M2

VSS

Figure 1. Low-voltage cascode current mirror.

Copyright q 2009 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2009)
DOI: 10.1002/cta
 CMOS CURRENT MIRROR

Figure 2. Level-shifted current mirror.

Figure 3. Level-shifted low-voltage cascode current mirror.

M5 . The input current (Iin1 ) and the externally applied voltage (Vo1 ) decide the operational region
for M2 . The Ibias1 and Iin1 decide the operating region of M1 . In Figure 2, as Iin1 increases, VGS1
will increase. Owing to the level-shifted function of M5 , Vin1 will increase and it is helpful for the
saturation operation of M1 .
The proposed CM is shown in Figure 3. It combines the techniques of low-voltage cascode CM
with level-shifted CM to achieve high output impedance, large input and output signal swings.
Thus, we name it as level-shifted low-voltage cascode CM. In Figure 3, we assume that the
mirror transistors M1 and M2 , and the cascode transistors M3 and M4 have identical aspect ratios,
respectively. Namely, they are W1 /L 1 = W2 /L 2 = A M and W3 /L 3 = W4 /L 4 = AC as the expression
in Figure 1. The body effect is ignored and it is assumed that all NMOS transistors have the identical
threshold voltage Vtn , and Vtp is the threshold voltage of M5 (with aspect ratio of W5 /L 5 = AB ).
To turn on the transistors M5 and M3 , the conditions VSG5 >|Vtp | and VGS3 >Vtn must be satisfied.
Since |Vtp |>Vtn , there is a difficulty to keep the condition VDS3 >0 valid in the circuit over a wide
range of Iin2 [16]. Therefore, there may be many possible combinations in which the transistors
M5 , M3 and M1 can operate. After the investigation of various cases, it can be found that the

Copyright q 2009 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2009)
DOI: 10.1002/cta
 H.-Y. WANG ET AL.

most suitable operational mode is the operation of M5 in sub-threshold region, while M3 and
M1 operate in sub-threshold region for low input currents and in saturation region for high input
currents.
Considering the sub-threshold operation of M5 , for VSD5 >3VT , the sub-threshold drain current
of M5 can be expressed by [16–18]
 
W5 VSG5 −|Vtp |
Ibias2 ≈ IDO5 exp (3)
L5 nVT
where VT (≈ 26 mV for room temperature) is the thermal voltage. The constants n and IDO5 are
process parameters. Typical value of IDO5 ≈ 20 nA and n lies between 1.2 and 2.0. We discuss the
most suitable two operational modes as below.
Case 1: When input current is low, M3 and M1 will operate in sub-threshold region. The gate
to source voltages of M5 , M1 and M3 is almost near to their threshold voltages [16]. We can find
 
Iin2 IDO5 AB
Vin2 = nVT ln + VSG5 + Vtn −|Vtp | (4)
Ibias2 IDO1 A M
0  Vin2 Vtn (5)
0  Iin2  min(IDO1 A M , IDO3 AC ) (6)

In this condition, the CM has poor frequency response due to the sub-threshold operations of M1
and M3 [17].
Case 2: When input current is high, M3 and M1 will operate in saturation operation. We can
find

2Iin2
Vin2 = + Vtn (7)
k AM
  
AC
Vtn < Vin2 Vtn 1+ (8)
AM

In Figure 3, when Iin2 increases thereby Vin2 increases, transistor M5 will shift the voltage level
at the gate terminal of M3 , Therefore, this CM has improved upper limit of the input current as it
is compared with the low-voltage cascode CM in Figure 1. The upper limit of the input current
can be expressed by

k AC Vtn2
Iin2  (9)
2
The operational mode of Case 2 is the most desirable mode of the proposed level-shifted low-
voltage cascode CM. Because only M5 operates in sub-threshold region and M1 –M4 are restricted
to operate in the saturation region, this CM possesses better frequency response and the lower
limit of the input current is slightly higher than the input current in Case 1. The sub-threshold
operation of M5 does not degrade the frequency response because M5 is just used for setting the
dc operating point. Besides, in this operational mode, the minimum necessary output voltage for

Copyright q 2009 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2009)
DOI: 10.1002/cta
 CMOS CURRENT MIRROR

the proposed CM is given as:

Vo2,min = VDS2(sat) + VDS4(sat) (10)
In addition, the input resistance (Rin ) and output resistance (Rout ) can be expressed by
1
Rin ≈ (11)
gm1
Rout ≈ gm4ro2ro4 (12)
where gm1 , gm4 , ro2 and ro4 have usual meanings.
Owing to the property of |Vtp |>Vtn for many processes, the Ibias2 in Figure 3 needs to be small
enough to satisfy the sub-threshold operation of M5 and saturation operation of M3 for Case 2
operation. If the Ibias2 in Figure 3 is not small enough, the M3 may operate in triode region and
M1 , M2 and M4 operate in saturation region. The VGS3 must be larger than VGS4 to carry the
mirror currents of M1 and M2 . Thus, VDS1 is smaller than VDS2 . Thus, the accuracy of the current
transfer ratio of the mirror is reduced. However, if multi-threshold-voltage technology is available,
the saturation operation of M1 –M4 can be achieved easily. Besides, by observing the circuit in
Figure 3, we can derive its complementary version. This complementary CM possesses similar
characteristics as discussed earlier. However, the above-mentioned operational mode of Case 2 can
be easily achieved if |Vtp |>Vtn .
In Figure 2(b) of [7], a similar scheme using level-shifted technique has been proposed before.
Comparing the above proposed CM in Figure 3 with the circuits in Figure 2(b) of [7], some

Figure 4. The realization of bias circuit in Figure 3.

Table I. W/L for various transistors of circuits.

MOSFETs Type Circuit shown in figures W/L (m/m)
M1 , M2 , M3 , M4 NMOS 1, 3 20/0.5
M5 PMOS 3 10/0.3
M B1 , M B4 PMOS 5 3/2.4
M B2 , M B3 NMOS 5 2/3

Copyright q 2009 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2009)
DOI: 10.1002/cta
 H.-Y. WANG ET AL.

differences could be pointed out here. The circuit in Figure 3 uses less bias current sources so that
it has easier configuration. The M5 in Figure 3 works in sub-threshold mode instead of saturation
operation. The PNP is necessary for the circuit in Figure 2(b) of [7] and NPN is necessary for
its complementary version. Nevertheless, the realization of NPN is not convenient in CMOS
technology.

3. SIMULATION RESULTS

To verify the potentialities of the proposed configuration, circuit simulations of the proposed level-
shifted low-voltage cascode CM (Figure 3) and low-voltage cascode CM (Figure 1) have been
carried out based on the level 49 MOS model parameters provided by the TSMC 0.18 m CMOS

Figure 5. Input characteristics of both CMs.

Figure 6. Current transfer characteristics of both CMs.

Copyright q 2009 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2009)
DOI: 10.1002/cta
 CMOS CURRENT MIRROR

technology with a DC supply voltage of ±1 V. To achieve higher input current ranges, the VB = 0 V
is chosen and Ibias2 is set to 2.6 A to ensure sub-threshold operation of M5 . The bias circuit in
Figure 4 is used to provide the bias current. Table I shows the aspect ratios of different transistors
of the CMs and bias circuit. The input characteristics of both CMs are shown in Figure 5. Figure 6
shows the current transfer characteristics of both CMs. It can be observed that the proposed CM
has improved input dynamic range, and Iout2 to Iin2 ratio is almost equal to unity. The output
characteristics of proposed CM at high and low input currents are given in Figures 7 and 8,
respectively. For grounded output, Figure 9 shows the magnitude frequency response for Iin2 with
1 mA DC component. The bandwidth is a function of DC component of Iin2 and its values are
given in Table II. In practical application, output load will decrease the bandwidth of the CM due
to its RC effects.

Figure 7. Output characteristics of the proposed CM at high input currents.

Figure 8. Output characteristics of the proposed CM at low input currents.

Copyright q 2009 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2009)
DOI: 10.1002/cta
 H.-Y. WANG ET AL.

Table II. The bandwidth of proposed CM in Figure 3 for Iin2 with different DC components.
DC component of Iin2 30 A 50 A 100 A 500 A 1 mA
Bandwidth 723 MHz 794 MHz 1.7 GHz 2.16 GHz 2.6 GHz

Figure 9. Frequency response of the proposed CM for Iin2 with 1 mA DC component.

4. CONCLUSIONS

A level-shifted low-voltage cascode current mirror (CM) with large output resistance, large output
swing and enhanced input dynamic range was presented. An MOS transistor operated in sub-
threshold region is used as a level shifter, which improves the input swing of the popular low-voltage
cascode CM. Its feasibility is discussed and verified by HSPICE simulation. The proposed circuit
is attractive for low-power and low-voltage applications.

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Copyright q 2009 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2009)
DOI: 10.1002/cta