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Boolean and Gate
Boolean and Gate
1. Introduction:
A logic gate is an idealized or physical device implementing a Boolean function,
that is, it performs a logical operation on one or more logic inputs and produces a
single logic output. Depending on the context, the term may refer to an ideal logic
gate, one that has for instance zero rise time and unlimited fan-out, or it may refer
to a non-ideal physical device. (see Ideal and real op-amps for comparison)
Logic gates are primarily implemented using diodes or transistors acting
as electronic
switches,
but
can
also
be
constructed
using
electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics,
molecules or even mechanical elements. With amplification, logic gates can be
cascaded in the same way that Boolean functions can be composed, allowing the
construction of a physical model of all of Boolean logic, and therefore, all of the
algorithms and mathematics that can be described with Boolean logic.
In 1854 a British mathematician, George Boole, developed Boolean algebra.
Instead of an algebra that uses numbers, Boolean algebra uses truth values,
true (1) and false (0). By defining sentences using truth values and performing
operations on truth tables. Boolean algebra has had a massive impact on Computer
Science and the language that computers understand is a language of 1s and 0s,
Boolean.
Logic gates are pieces of hardware that perform operations on Boolean inputs,
allowing us to create complex devices out of abstract Boolean algebra. Logic
gates are the fundamental building blocks of hardware and processors will be
made out of billions of them. A logic gate will typically have one or more inputs,
and single output. There are six types of gate that you need to know, they are
AND, OR, NOT, NAND, NOR and XOR.
First, we need a mathematical framework for describing the relationship between
logic gates and binary numbers. That framework is Boolean algebra. This
document of course provides only an introduction to Boolean algebra; refer to
dedicated texts for a detailed discussion of the subject. The English mathematician
George Boole (1815-1864) sought to give symbolic form to Aristotle's system of
logic. Boole wrote a treatise on the subject in 1854, titled An Investigation of the
Laws of Thought, on Which Are Founded the Mathematical Theories of Logic
and Probabilities, which codified several rules of relationship between
mathematical quantities limited to one of two possible values: true or false, 1 or 0.
His mathematical system became known as Boolean algebra.
All arithmetic operations performed with Boolean quantities have but one of two
possible outcomes: either 1 or 0. There is no such thing as "2" or "-1" or "1/2" in
the Boolean world. It is a world in which all other possibilities are invalid by fiat.
As one might guess, this is not the kind of math you want to use when balancing a
checkbook or calculating current through a resistor. However, Claude Shannon of
MIT fame recognized how Boolean algebra could be applied to on-and-off
circuits, where all signals are characterized as either "high" (1) or "low" (0).
Theoretical work to use in a way Boole never could have imagined, giving us a
powerful mathematical tool for designing and analyzing digital circuits.
1
a.
In this section, you will find a lot of similarities between Boolean algebra and
"normal" algebra, the kind of algebra involving so-called real numbers. Just bear
in mind that the system of numbers defining Boolean algebra is severely limited in
terms of scope, and that there can only be one of two possible values for any
Boolean variable: 1 or 0. Consequently, the "Laws" of Boolean algebra often
differ from the "Laws" of real-number algebra, making possible such statements
as 1 + 1 = 1, which would normally be considered absurd. Once you comprehend
the premise of all quantities in Boolean algebra being limited to the two
possibilities of 1 and 0, and the general philosophical principle of Laws depending
on quantitative definitions, the "nonsense" of Boolean algebra disappears.
2. Digital Logic Gates:
A logic gate is a general purpose electronic device used to construct logic circuits.
All logic gates have inputs and outputs. The state of the output is set by the input
states using different rules depending on the type of gate. The different types of
gates have different shaped circuit symbols.
Logic gates the basic components in digital electronics. They are used to create
digital circuits and even complex integrated circuits. For examples, complex
integrated circuits may bring already a complete circuit ready to be used microprocessors and microcontrollers are the best examples-but inside them they
were projected using several logic gates.
A gate is a special type of amplifier circuit designed to accept and generate
voltage signals corresponding to binary 1's and 0's. As such, gates are not
intended to be used for amplifying analog signals (voltage signals between 0 and
full voltage). Used together, multiple gates may be applied to the task of binary
number storage (memory circuits) or manipulation (computing circuits), each
gate's output representing one bit of a multi-bit binary number.
Positive and Negative logic:
We know that, in binary logic, two voltage levels represent the two binary digits,
1 or 0. If the higher of the two voltages represents a 1 and lower voltage represent
a 0, the system is called a positive logic system. On the other hand, if the lower
voltage represents a 1 and the higher voltage represents a 0, we have a negative
logic system.
On a circuit diagram it must be accompanied by a statement asserting that
the positive logic convention or negative logic convention is being used (high
voltage level = 1 or high voltage level = 0, respectively). The wedge is used in
circuit diagrams to directly indicate an active-low (high voltage level = 0) input or
output without requiring a uniform convention throughout the circuit diagram.
This is called Direct Polarity Indication. Both the bubble and the wedge can be
used on distinctive-shape and rectangular-shape symbols on circuit diagrams,
depending on the logic convention used. On pure logic diagrams, only the
bubble is meaningful.
As an example, assume that we have positive 5V and 0V as logic-level voltages.
Let us designate +5V as high level and 0 as low level; then positive and negative
logic can be defined as:
Positive logic:
high = 1
Low = 0
Negative logic:
High = 0
Low = 1
Both positive and negative logic are used in digital systems, but positive logic is
more common.
2
b.
Distinctive
shape
Rectangular
shape
Boolean
algebra
Logic Statement
AND
Y=A.B
High output
when both inputs
are high.
OR
Y=A+B
Low output
when both inputs
are low.
NOT
Output is the
complement of
input.
Fig. 1 Basic Logic gates
2.1
AND gate:
Definition:
The AND gate is a logic device that has two or more inputs but one output.
Symbols:
There are three symbols for AND gates: the American (ANSI or 'military') symbol and
the IEC ('European' or 'rectangular') symbol, as well as the deprecated DIN symbol.
MIL/ANSI Symbol
IEC Symbol
DIN Symbol
Logic families:
(a)
(b)
Fig. 3 (a) Resistor Transistor Logic (RTL) circuit and (b) Diode Logic of
input AND gate
2-
(a)
(b)
Fig. 4 (a) Electrical analogy (b) easy way drawing of AND gate
The simplified AND gate shown above has two inputs, switch A and switch B.
The bulb Q will only light if both switches are closed. This will allow current to
flow through the bulb, illuminating the filament.
An easy way to remember how an AND gate works is thinking about a circuit to
turn a light bulb on. If both switches are on then the bulb will light up, if any
switch is off then the bulb won't light.
This is an AND gate circuit and it can be made quite easily. The example shown
is built from a modular electronics kit. Both switches A and B must be pressed
together for the bulb to light. If you construct this circuit, you may need to alter
the value of the resistors. This will depend on the type of transistors used and
whether to bulb or an LED is used.
Relay Equivalent:
(a)
(b)
Fig. 6 (a) Relay Equivalence of AND (b) AND and NAND gates.
5
In the AND gate circuit, both relays, in series with their own switch buttons are
placed (in parallel) independently from each other, yet connected to the same
source. The lamp (output) circuit is also connected to the same source.
However, the lamp is connected in series with NORMALY OPEN contact of
relay A, then in series with NORMALY open contacts of relay B. So the lamp
will light up only if both contacts will be closed. And it will happen only if
both relays be activated.
Domestic gate concept:
Parallel connected gates in your home. You can enter the home when all gates are
open.
Boolean Equation: Y= A.B
Timing Diagram: Timing diagrams are yet another method of showing the function of
a gate or circuit. If the function of the gate is known, you should be able to draw the
output waveform for a gate given the input waveforms.
(a)
(b)
The OR gate is a circuits that produces high output when any of its inputs are
high.
Symbols:
Fig. 9 shows conventional, IEC and the IEEE symbols for the two-input OR gate
with inputs A and B and output Y and table 3 summarized the operation of the OR
gate using truth table. All possible input combinations are listed by counting in
binary from 00 to 11.
(a)
(b)
Output
B
A
Y= A+B
0
0
0
0
1
1
1
0
1
1
1
1
Table 3. two- input OR gate truth table
Logic families:
(a)
(b)
Fig. 10. (a) Resistor Transistor Logic (RTL) circuit and (b) Diode Logic of two input
OR gate
7
10
(a)
(b)
Fig. 11. (a) Electrical analogy (b) easy drawing of (a) OR gate
The simplified OR gate shown above has two inputs, switch A and switch B. The
bulb Q will light if either switch A or B are closed. This will allow current to flow
through the bulb, illuminating the filament.
An easy way to remember how an OR gate works is thinking about a circuit to
turn a light bulb on. If one or more switches are on then the bulb will light up, if
both switch are off then the bulb won't light.
(a)
(b)
Fig. 14. (a) pin out diagram (b) front inner view of IC 7432
A variety of forms of OR gates are available in TTL and CMOS. In the TTL
family, the 7432 is a quad (meaning four gates) two-input TTL OR gate IC. The
four are independent. Each can be in a different part of the circuit without
feedback. Power is supplied to the IC through a VCC (+5V) and ground
connection. The 4072 is a dual (meaning two gates) four input CMOS OR gate
IC. The pin out for 7432 and 4072 is shown in Fig. 14.
Some of the available OR gate ICs are listed in following Table
Number
Family
Subfamily
Description
7432
TTL
Standard
Quad 2-input OR
74LS32
TTL
Low-Power
Quad 2-input OR
Schottky
74HC32
CMOS
High-Speed CMOS Quad 2-input OR
4071
CMOS
Standard
Quad 2-input OR
4072
CMOS
Standard
Dual 4-input OR
Table 4. some of the available OR gate ICs
9
2.4.3 Inverter:
Definition: The inverter is a singleinput and single output gate whose output is
the complement of the input. It inverts the signal on the input. Fig.15 (a) shows
conventional and IEC (International Electrochemical Commission) and the IEEE
(Institute of Electrical and Electronics Engineers) symbols for the inverter and
Table 5, summarized the operation in a truth table by listing all possible input and
the corresponding output. In electronics a NOT gate is more commonly called an
inverter. The circle on the symbol is called a bubble, and is used in logic diagrams
to indicate a logic negation between the external logic state and the internal logic
state (1 to 0 or vice versa).
Symbols: There are two symbols for NOT gates: the American (ANSI or 'military')
symbol and the IEC ('European'
deprecated DIN symbol.
MIL/ANSI Symbol
or
'rectangular')
symbol,
as
well
as
the
IEC Symbol
10
11
(a)
(b)
Fig. 19. (a) pin out diagram (b) front inner view of 7404/05/14
The original CMOS family was numbered 4xxx. For example, the 4069 is a hex
inverter. Most 4xxx ICs have a different pinout from their 74xxx counterparts.
The pinout of the 4069 happens to be same as the 7404. The power pin on the
4xxx series is labeled VDD instead of VCC; and the ground pin is labeled VSS.
VDD can range from +3 volt to +15 volt. Some of the available inverter ICs is
listed in following Table.
Number
7404
74LS04
74ALS04
Family
TTL
TTL
TTL
Subfamily
Standard
Low-Power Schottky
Advanced Low-Power
Schottky
74AC04
CMOS
Advanced CMOS
74HC04
CMOS
High-Speed CMOS
74HCT04
CMOS
High- Speed CMOS,
TTL Compatible
4069
CMOS
Standard
Table 6. Some of the available NOT gate ICs
Description
Hex Inverter
Hex Inverter
Hex Inverter
Hex Inverter
Hex Inverter
Hex Inverter
Hex Inverter
Distinctive
shape
Rectangular
shape
Boolean algebra
between A & B
XOR
XNOR
Logic
Low output
when both
inputs are
same
High output
when both
inputs are
same
12
An exclusive-OR (Ex-OR) gate is not one of the basic gates, but is constructed
from a combination of the basic gates. The Ex-OR is a two input gate that
produces a 1 on its output when its inputs are different and a 0 if they are the
same.
Symbol: The symbol for an exclusive-OR is shown in Fig. 20. The three previous
gates are fairly direct variations on basic functions: NOT, AND and OR. The
Exclusive-OR (XOR) gate is something quite different. Exclusive-OR gates
output a "high" (1) logic level if the inputs are at different logic levels, either 0
and 1 or 1 and 0. Conversely, they output a "low" (0) logic level if the inputs are
at the same logic levels. The Exclusive-OR (sometimes called XOR) gate has
both a symbol and a truth table pattern that is unique, refer to figure 8.
(a)
(b)
(c)
This symbol is seldom used in Boolean expressions because the identities, laws,
and rules of simplification involving addition, multiplication, and
complementation do not apply to it. However, there is a way to represent the
Exclusive-OR function in terms of OR and AND, as has been shown as: AB' +
A'B
Truth table:
The truth table for an exclusive-OR is shown in table
Input
XOR
gate
Logic families:
B
0
0
1
1
A
0
1
0
1
Output
Y A B
0
1
1
0
Table 7. 2 input
truth table
(a)
(b)
Fig. 23. (a) pin out diagram (b) front inner view of 7486
14
Following Table Shows the some Ex-OR gate are available in many forms in
TTL and CMOS.
Number
Family
Subfamily
Description
7486
TTL
Standard
Quad 2-input Ex-OR
74ACT86
CMOS
Advanced CMOS, TTL Quad 2-input Ex-OR
compatible
74ALST86 TTL
Advanced
Low-Power Quad 2-input Ex-OR
Schottky
4030
CMOS
Standard
Quad 2-input NAND
4070
CMOS
Standard
Dual 4-input NAND
Table 8. some of the available XOR gate ICs
2.5.2 Exclusive-NOR gates:
Definition:
The Exclusive-NOR Gate function or Ex-NOR for short, is a digital logic gate
that is the reverse or complementary form of the Exclusive-OR function we look
at in the previous section. It is a combination of the Exclusive-OR gate and
the NOT gate but has a truth table similar to the standard NOR gate in that it has
an output that is normally at logic level "1" and goes "LOW" to logic level "0"
when ANY of its inputs are at logic level "1". However, an output "1" is also
obtained if BOTH of its inputs are at logic level "1". For example, A = "1" and B
= "1" at the same time giving us the Boolean expression
of: Q = (A B) = A.B + A.B
An exclusive-NOR (Ex-NOR), sometimes called non exclusive-OR. Ex-NOR
gate is not one of the basic gates, but is constructed from a combination of the
basic gates. The Ex-NOR is a two input gate that produces a 1 on its output when
its inputs are same and a 0 if they are the different.
Symbol:
The symbol for an exclusive-NOR gate is shown in Fig, 24.
15
Output
Y A B
0
0
1
1
0
1
0
1
0
1
1
0
Y A B =
Timing Diagram
16
(a)
(b)
Fig. 26. (a) pin out diagram (b) front view of 74266 (quad 2-input Ex-NOR
Gate)
Number
Family
Subfamily
Description
74HCT266
CMOS
Hi Speed CMOS
17
Application of XOR
1. Uses in addition
The XOR logic gate can be used as a one-bit adder that adds any two bits together
to output one bit. For example, if we add 1 plus 1 inbinary, we expect a two-bit
answer, 10 (i.e. 2 in decimal). Since the trailing sum bit in this output is achieved
with XOR, the precedingcarry bit is calculated with an AND gate. This is the
main principle in Half Adders and the combined AND-XOR circuit may be
chained together in order to add ever longer binary numbers.
Distinctive
shape
Rectangular
shape
Boolean algebra
between A & B
NAND
Logic
Low output
when both
inputs are
high
high output
when both
inputs are
low
NOR
A variation on the idea of the AND gate is called the NAND gate. The word
"NAND" is a verbal contraction of the words NOT and AND. Essentially, a
18
NAND gate behaves the same as an AND gate with a NOT (inverter) gate
connected to the output terminal. The NAND gate is a circuit that produces a 0
on its output when all of its inputs are 1. NAND is the contraction of the words
NOT and AND.
Symbols:
To symbolize this output signal inversion, the NAND gate symbol has a bubble
on the output line. The truth table for a NAND gate is as one might expect,
exactly opposite as that of an AND gate.
A
0
1
0
1
Output
Y AB
0
0
0
1
Logic families:
(a)
(b)
Fig. 31. (a) Resistor Transistor Logic (RTL) circuit and (b) Schematic of
basic two-input DTL NAND gate Diode Transistor Logic of NAND gate
19
Subfamily
Description
Standard
Quad 2-input NAND
Standard
8-input NAND
Low-Power Schottky
Dual 4-input NAND
Advanced Low-Power Triple 3-input NAND
Schottky
74ALST133
TTL
Advanced Low-Power 13-input NAND
Schottky
74HTC11
CMOS
High-Speed CMOS
Quad 2-input NAND
4011
CMOS
Standard
Quad 2-input NAND
4012
CMOS
Standard
Dual 4-input NAND
4023
CMOS
Standard
Triple 3-input NAND
Table 12. some of the available NAND gate ICs
2.6.2 NOR gates:
Definition:
The NOR gate is a circuit that produces a 0 on its output when one or more of its
inputs are 1. NOR is the contraction of the words NOT and OR. Its symbol is
the OR symbol with an inverted (conventional, and IEC/IEEE), with two inputs A
and B and output Y, is shown in Fig.35.
Symbols:
Truth table:
Input
B
0
0
1
1
A
0
1
0
1
Output
Y A B
1
0
0
0
(a)
(b)
Fig. 37. (a) pin out diagram (b) front inner view of 7402
22
The NOR gate is available in many forms in TTL and CMOS, as shown in
following Table.
Number
7402
7425
74LVQ02
74ALS27
4001
4002
4025
2.7
Family
TTL
TTL
TTL
TTL
Subfamily
Description
Standard
Quad 2-input NOR
Standard
Dual 4-input NOR
Low-Voltage Quiet
Quad 2-input NOR
Advanced
Low-Power Triple 3-input NAND
Schottky
CMOS
Standard
Quad 2-input NOR
CMOS
Standard
Dual 4-input NOR
CMOS
Standard
Triple 3-input NOR
Table 14. some of the available NOR gate ICs
OR gate
inputs
output
output
A
B
Y
A
B
Y
1
1
1
0
0
0
1
0
0
0
1
1
0
1
0
1
0
1
0
0
0
1
1
1
Table 16. representation in positive logic
Table 17. representation in negative logic
Inputs
AND gate
Similarly table 18 and table 19 represents the positive and negative logic AND
gate respectively.
23
And gate
inputs
output
output
A
B
Y
A
B
Y
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
1
0
0
0
0
0
1
1
1
Table18. representation in positive logic
Table 19. representation in negative logic
Above tables show that positive logic OR gate system becomes an negative logic
AND gate systems and vice versa.
Inputs
Positive OR
Positive AND
Negative AND
Negative OR
In a similar ways, we can compare the equivalences between positive and negative
logic NOR and NAND gates:
Positive NOR
Positive NAND
2.8
Negative NAND
Negative NOR
Gate Universality:
2.8.1 NAND/NOR gate as a Universal gate:
A NAND gate is a combination of NOT and AND gate (i.e., AND gate followed
by inverter). Therefore, the output is NOT the AND of the inputs. Thus it has two
or more input signals but only one output signal. All input signals must be high to
get a low output.
The NAND gate is said to be a universal gate because any digital system can be
implement with it. The logic operation of NOT (inverter/complement), AND, OR,
Ex-OR, and Ex-NOR gates can be obtained with NAND gates only. NAND gate
is easier to realize and consume less power than the other gates.
The NOR operation is the dual of the NAND operation. Therefore, all procedures
and rules for NOR logic are the duals of the corresponding procedures and rules
developed for NAND logic. A NOR gate is a combination of NOT and OR gate
(i.e., OR gate followed by inverter). Therefore, the output is NOT the OR of the
inputs. Thus it has two or more input signals but only one output signal. All input
signals must be low to get a high output. The NOR gate is another universal gate
that can be used to implement any Boolean function. The implement of the NOT
(complement), AND, OR, NAND, Ex-OR, and Ex-NOR gates with NOR gate
only. NOR gate is easier to realize and consume less power than the other gates.
2.8.2 NAND/NOR as NOT (Inverter /Complement) operation:
The complement operation is obtained from a one input NAND gate that behaves
exactly like an inverterFig.2.1.1 shows a two-input NAND gate as an Inverter.
Suppose we apply the same signal to both inputs of a two-input NAND. The twoinputs to NAND gate are tied together, so that the gate works as inverter (NOT)
gate. Then either both inputs are 0 or both inputs are 1. If input is 0 the output
will be 1. If input is 1 the output will be 0. The output is always the
complement of the input.
24
The complement operation is obtained from a one input NOR gate that behaves
exactly like an inverter. If we apply the same signals of a two-input NOR gate,
then either both inputs are0 or both inputs are 1. In either case the output is
always the complement of the input. Fig.2.2.1 shows a two-input NOR gate as an
Inverter. An Inverter or logic NOT gate can also be made using
standard NAND and NOR gates by connecting together ALL their inputs to a
common input signal for example.
25
26
27
Fig. shows a two-input NAND gates as a two-input NOR gate The output of twoinput NOR gate is ( Y A B A . B ). It indicates, the combination of four two-input
NAND gates gives two-input NOR gate operation. In Fig.2.1.4, the two inputs of each of
the first two NAND gates are tied together and fed by A and B. The outputs are Aand B .
They are fed to as inputs to third NAND gate. The output is A+B, fed to as input to fourth
NAND gate. The final output is A B thus giving NOR operation.
It would be pointless to show you how to "construct" the NAND function using a NAND
gate, since there is nothing to do. To make a NOR gate perform the NAND function, we
must invert all inputs to the NOR gate as well as the NOR gate's output. For a two-input
gate, this requires three more NOR gates connected as inverters.
=
. .
.
Second way: = . + . + +
= ( + ) + ( + )
= (.
) + (.
)
= (.
).
(.
)
Second way:Y AB A B A A B B
Y AB AB
A( A B ) B (( A B )
( A B) ( A B)
( A B ).( A B )
( A B) ( A B)
2.
The output of Ex-NOR gate is ( Y AB AB AB AB ). It is the invert of ExOR gate. We can implement the Ex-NOR gate using minimum number of
NAND gates as shown in the following logic diagram.
. + . + + )
=
. + . = (
) + ()
=
( + ) + ( + ) = (
) . (
)
= (
One easier way of producing the Ex-NOR function from a single gate type is to
use NAND gates as shown below.
Inhibit
Enable
Input
Control
0
0
1
1
Data
0
1
0
1
Y
0
0
0
1
Output
Comments
Output locked at 0
Data passes through unaltered
Inhibit
Enable
Input
Control
0
0
1
1
Data
0
1
0
1
Y
1
1
1
0
Output
Comments
Output locked at 1
Data passes through inverted
Input
Output
Control
Data
Y
Comments
Enable
0
0
0
Data passes through
0
1
1
Inhibit
1
0
1
Output
locked at 1
1
1
1
Table 22. truth table for OR gate as an Enable/Inhibit.
If the signal on the control input of an OR gate is 0 (top two lines of the truth
table in Table 22), the signal on the data input passes through to the output
and the gate is enabled.
If the signal on the control input is 1 (bottom top two lines of the truth table in
Table 22), the signal on the data input is ignored and the output is locked up
in the 1 state. The gate is said to be inhibited.
NOR gate as Enable/Inhibit:
Following table shows the truth table for NOR gate as an Enable/Inhibit.
Input
Output
Control
Data
Y
Comments
Enable
0
0
1
Data passes through inverted
0
1
0
Inhibit
1
0
0
Output
locked at 0
1
1
0
Table23. truth table for NOR gate as an Enable/Inhibit.
If the signal on the control input of a NOR gate is 0 (top two lines of the truth
table in Table 23), whatever is present on the data input appears at the output
inverted. The gate is enabled.
If the signal on the control input is 1 (bottom top two lines of the truth table in
Table 23), the output of the gate is 0 regardless of the data present at the data
input. The gate is said to be inhibited.
4. Ex-OR gate as Enable/Inhibit:
Following table shows the truth table for Ex-OR gate as an Enable/Inhibit.
Input
Output
Control
Data
Y
Comments
Data passes
Data passes
0
0
0
(buffer)
0
1
1
Data passes
Inverted
1
1
0
1
1
0
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
35
+5V
(a)
(b)
(c)
(d)
(f)
(g)
(h)
+5V
(e)
b. A four-input NAND gate can be created from two two-input NAND gates as
shown in Fig.52. The output is the same as if we had fed A, B, C, and D into a
four-input NAND as:
3. Expanding an OR gate:
a. A three-input OR gate can be created from two two-input OR gates as shown
in Fig.53. The output is the same as if we had fed A, B, and C into a threeinput AND, Y= (A+B) +C =A+ (B+C).
b. A four-input OR gate can be created from two two-input OR gates. The output
is the same as if we had fed A, B, C, and D into a four-input OR, Y= (A.B).
(C.D), similarly we can expand an OR with another OR.
The OR function can have any number of individual inputs. However,
commercial available OR gates are available in 2, 3, or 4 inputs types.
Additional inputs will require gates to be cascaded together for example.
Fig. 55. four input NOR using two input NOR gates
The Boolean Expression for this 4-input NOR gate will therefore
be: Q = A+B+C+D
If the number of inputs required is an odd number of inputs any "unused" inputs
can be held LOW by connecting them directly to ground using suitable "Pulldown" resistors.
The Logic NOR Gate function is sometimes known as the Pierce Function and
is denoted by a downwards arrow operator as shown, AB.
2.9
Boolean Postulates
2.2.1 Boolean Arithmetic
Let us begin our exploration of Boolean algebra by adding numbers together: The
first three sums make perfect sense to anyone familiar with elementary addition.
The last sum, though, is quite possibly responsible for more confusion than any
other single statement in digital electronics, because it seems to run contrary to
the basic principles of mathematics. Well, it does contradict principles of addition
for real numbers, but not for Boolean numbers. Remember that in the world of
Boolean algebra, there are only two possible values for any quantity and for any
arithmetic operation: 1 or 0. There is no such thing as "2" within the scope of
38
Boolean values. Since the sum "1 + 1" certainly isn't 0, it must be 1 by process of
elimination. It does not matter how many or few terms we add together, either.
Consider the following sums: Take a close look at the two-term sums in the first
set of equations. Does that pattern look familiar to you? It should! It is the same
pattern of 1's and 0's as seen in the truth table for an OR gate. In other words,
Boolean addition corresponds to the logical function of an "OR" gate, as shown in
figure 1 below.
0=
1=
0=
1=
0
1
1
1
39
0=
1=
0=
1=
0
0
0
1
This set of equations should also look familiar to you: it is the same pattern
found in the truth table for an AND gate. In other words, Boolean multiplication
corresponds to the logical function of an "AND" gate, as well as to series switch
contacts:
40
If : A 1 ; Then A 0
In written form, the complement of "A" denoted as "A-not" or "A-bar".
Sometimes a "prime" symbol is used to represent complementation. For
example, A' would be the complement of A, much the same as using a prime
symbol to denote differentiation in calculus rather than the fractional notation
d/dt. Usually, though, the "bar" symbol finds more widespread use than the
"prime" symbol, for reasons that will become more apparent later in this
chapter.
Boolean complementation finds equivalency in the form of the NOT gate, or a
normally-closed switch or relay contact:
41
Fig.59. OR operation
No matter what the value of A, the output will always be the same: when A=1,
the output will also be 1; when A=0, the output will also be 0.The next identity
is most definitely different from any seen in normal algebra. Here we discover
that the sum of anything and one is one:
43
44
45
0
1
2
3
Inputs
A
0
0
1
1
B
0
1
0
1
Commutative (ORing)
Commutative (ANDing)
A+B
B+A
A.B
B.A
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
Table 25. truth table for commutative laws
b. Distributive law:
The distributive laws allow the factoring or multiplying of expressions. Two
distributive laws will be considered.
A + (B. C) = (A + B). ( A + C )
46
Figure 2.72 illustrates the distributive law, the AND gate gives an output B.C.
This signal when fed to OR gate along with input A gives the output A + (B. C).In
the circuit on right hand side the two OR gates give the output (A + B) and ( A +
C ) respectively. The AND gate gives the output (A + B). (A + C).
Boolean Algebraic Properties
Another type of mathematical identity, called a "property" or a "law," describes
how differing variables relate to each other in a system of numbers. Assuming A
and B are Boolean numbers; figure 2 lists the Boolean algebraic properties.
S.No.
0
1
2
3
4
5
6
7
(A+B).(A+C)
0
0
0
1
1
1
1
1
A. (B + C) = A .B + A. C
Figure 69 illustrates the distributive law, the OR gate gives an output B + C.
This is fed as input to AND gate along with input A. On the right hand side the
47
two AND gates give the output (A. B) and (A. C) respectively. The OR gate gives
the output (A. B) + (A. C).
S.No.
0
1
2
3
4
Inputs
A
0
0
0
0
1
B
0
0
1
1
0
(A+B)+C
0
1
1
1
1
48
5
6
7
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 27. truth table for associative law using OR.
1
1
1
(b) . . = . (. ) = (. ).
Fig 71 shows the associative law for ANDing. The inputs to AND gates have
been grouped in two different ways without affecting the output. In each case
the output is y = A.B.C.
S.No.
Inputs
0
1
2
3
4
5
6
7
A
0
0
0
0
1
1
1
1
To summarize, here are the three basic properties: commutative, associative, and
distributive.
d. Absorption law:
This law is extremely important for the elimination of redundant function in a
system.
(a) ( + ) =
Fig.2.78 shows the law of absorption. The output is logic 0 when A is 0 and logic
1 when A is 1, irrespective of the state of B.
49
0
1
2
3
4
5
6
7
Inputs
Output
B
C
A+B
A
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
Table 29. truth table for absorption law
A(A+B)
0
0
0
0
1
1
1
1
(b) + =
Fig.2.79 shows another law of absorption. The output is logic 0 when A is 0
and logic 1 when A is 1, irrespective of the state of B.
Boolean rules for simplification
Boolean algebra finds its most practical use in the simplification of logic
circuits. If we translate a logic circuit's function into symbolic (Boolean)
form, and apply certain algebraic rules to the resulting equation to reduce the
number of terms and/or arithmetic operations, the simplified equation may be
translated back into circuit form for a logic circuit performing the same
function with fewer components. If equivalent function may be achieved
with fewer components, the result will be increased reliability and decreased
cost of manufacture.
To this end, there are several rules of Boolean algebra presented in this
section for use in reducing expressions to their simplest forms. The identities
and properties already reviewed in this chapter are very useful in Boolean
simplification, and for the most part bear similarity to many identities and
properties of "normal" algebra. However, the rules shown in this section are
all unique to Boolean mathematics.
This rule may be proven symbolically by factoring an "A" out of the two
terms, then applying the rules of A + 1 = 1 and 1A = A to achieve the final
result:
50
0
1
2
3
4
5
6
7
Inputs
A
0
0
0
0
1
1
1
1
Output
B
C
AB
A+(AB)
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
Table 30. truth table for absorption law
Please note how the rule A + 1 = 1 was used to reduce the (B + 1) term to 1.
When a rule like "A + 1 = 1" is expressed using the letter "A", it doesn't
mean it only applies to expressions containing "A". What the "A" stands for
in a rule like A + 1 = 1 is any Boolean variable or collection of variables.
This is perhaps the most difficult concept for new students to master in
Boolean simplification: applying standardized identities, properties, and rules
to expressions not in standard form.
For instance, the Boolean expression ABC + 1 also reduces to 1 by means of
the "A + 1 = 1" identity. In this case, we recognize that the "A" term in the
identity's standard form can represent the entire "ABC" term in the original
expression.
The next rule looks similar to the first one shown in this section, but is
actually quite different and requires a more clever proof:
Note how the last rule (A + AB = A) is used to "un-simplify" the first "A"
term in the expression, changing the "A" into an "A + AB". While this may
seem like a backward step, it certainly helped to reduce the expression to
something simpler! Sometimes in mathematics we must take "backward"
steps to achieve the most elegant solution. Knowing when to take such a step
and when not to is part of the art-form of algebra, just as a victory in a game
of chess almost always requires calculated sacrifices.
Another rule involves the simplification of a product-of-sums expression:
52
Following table summarizes the operation of AND, NAND, OR, NOR, XOR, and
XNOR.
Gates
AND
Commutative
Yes A.B B.A
NAND
Yes
Associative
Yes
( AB) ( BA)
( A.B)C A( BC )
Distributive
Yes
Yes
Not
( A.B).C )
Yes
Yes
OR
Yes
A B B A
Yes
( A.( B.C )
( A. B ) C
A (B C)
NOR
Yes
( A B) ( B A)
Not
( A B) C )
XOR
Yes
A B B A
Yes
( A .( B C )
A (B C)
( A B) C
XNOR
Yes
A B B A
Yes
A (B C)
( A B) C
A( B C )
AB AC
A( B C )
AB AC
A. ( BC )
( A B ).( A C )
A. ( BC )
( A B).( A C )
Not
Not
A (B C)
( A B) ( A C )
A (B C)
( A B) ( A C )
Output
A
A
A
A.A.A
0
0
0
0
1
1
1
1
Table 32. truth table for idempotent law using AND
(b) = + + + .
Fig 2.84 shows another law of idempotent for ORing. The output is
variable itself A whatsoever, the value of A.
53
A
0
1
Output
A
A
A+A+A
0
0
0
1
1
1
Table 33. truth table for idempotent law using OR
f. Complementation law:
This law states that if a function consists of a variable and its inverse, then the
function is a constant.
(a) . = 0
Since an AND gate requires both inputs to be logic 1 for a logic 1 output, .
is always logic 0, since A and can never be logic 1 simultaneously. This is
shown in Fig.3.2.11
Output
.
0
1
0
1
0
0
Table 34. truth table for complementation using AND
(b) + = 1
..(3.2.5)
Since an OR gate requires only one input to be logic 1 for logic 1 output,
either must be 1 at any time, so the result of A+A is always logic 1.
This is shown in Fig.3.2.12.
54
Output
+
0
1
1
1
0
1
Table 35. truth table for idempotent law using OR
2.10 Basic Theorems and Proof
De Morgan equivalent symbolsBy use of De Morgan's theorem,
an AND function is identical to an OR function with negated inputs and outputs.
Likewise, an OR function is identical to an AND function with negated inputs
and outputs. Similarly, a NAND gate is equivalent to an OR gate with negated
inputs, and a NOR gate is equivalent to an AND gate with negated inputs.
The leads to an alternative set of symbols for basic gates that use the opposite
core symbol (AND or OR) but with the inputs and outputs negated . Use of these
alternative symbols can make logic circuit diagrams much clearer and help to
show accidental connection of an active high output to an active low input or
vice-versa. Any connection that has logic negations at both ends can be replaced
by a negationless connection and a suitable change of gate or vice-versa. Any
connection that has a negation at one end and no negation at the other can be
made easier to interpret by instead using the De Morgan equivalent symbol at
either of the two ends. When negation or polarity indicators on both ends of a
connection match, there is no logic negation in that path (effectively, bubbles
"cancel"), making it easier to follow logic states from one symbol to the next.
This is commonly seen in real logic diagrams - thus the reader must not get into
the habit of associating the shapes exclusively as OR or AND shapes, but also
take into account the bubbles at both inputs and outputs in order to determine
the "true" logic function indicated.
All logic relations can be realized by using NAND gates (this can also be done
using NOR gates). De Morgan's theorem is most commonly used to transform
all logic gates to NAND gates or NOR gates. This is done mainly since it is easy
55
to buy logic gates in bulk and because many electronics labs stock only NAND
and NOR gates.
2.11
De Morgans Theorems
De-Morgans theorems is one of the most important theorems of Boolean
algebra, since it formulates the relationship between N (AND) and N (OR)
functions that allows one type of function to be implemented using a different
type of gate. This is also known as Law of dualisation.
1. De-Morgans first theorem:
In words, it says the complement of a sum equals the product of the
complements. Boolean expression for the above is B A B. A . This equation
means that a NOR function can be implemented by inverting the two inputs to
an AND function. Fig. 3.1.1 shows the logic diagram and truth table for twoinput De-Morgans first theorem. This theorem supports the fact that a NOR
gate is the same as inverting the inputs into an AND gate (bubbled AND).
B
0
0
1
1
A
0
1
0
1
B.A
0
0
0
1
+
1
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
B
0
0
1
1
A
0
1
0
1
B.A
0
0
0
1
BA
B A
.
1
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
B. A
B. A
57
When multiple "layers" of bars exist in an expression, you may only break one
bar at a time, and it is generally easier to begin simplification by breaking the
longest (uppermost) bar first. To illustrate, let's take the expression (A + (BC)')'
and reduce it using De-Morgan's Theorems:
As a result, the original circuit is reduced to a three-input AND gate with the A
input inverted:
As tempting as it may be to conserve steps and break more than one bar at a time,
it often leads to an incorrect result, so don't do it!
58
It is possible to properly reduce this expression by breaking the short bar first,
rather than the long bar first:
The end result is the same, but more steps are required compared to using the first
method, where the longest bar was broken first. Note how in the third step we
broke the long bar in two places. This is a legitimate mathematical operation, and
not the same as breaking two bars in one step! The prohibition against breaking
more than one bar in one step is not a prohibition against breaking a bar in more
than one place. Breaking in more than one place in a single step is okay; breaking
more than one bar in a single step is not.
You might be wondering why parentheses were placed around the sub-expression
B' + C', considering the fact that I just removed them in the next step. I did this to
emphasize an important but easily neglected aspect of DeMorgan's theorem. Since
a long bar functions as a grouping symbol, the variables formerly grouped by a
broken bar must remain grouped lest proper precedence (order of operation) be
lost. In this example, it really wouldn't matter if I forgot to put parentheses in after
breaking the short bar, but in other cases it might. Consider this example, starting
with a different expression:
59
As you can see, maintaining the grouping implied by the complementation bars
for this expression is crucial to obtaining the correct answer.
Let's apply the principles of De-Morgan's theorems to the simplification of a gate
circuit:
Next, we can label the outputs of the first NOR gate and the NAND gate. When
dealing with inverted-output gates, I find it easier to write an expression for the
gate's output without the final inversion, with an arrow pointing to just before the
inversion bubble. Then, at the wire leading out of the gate (after the bubble), I
write the full, complemented expression. This helps ensure I don't forget a
complementing bar in the sub-expression, by forcing myself to split the
expression-writing task into two steps:
60
61
Duality Theorem
It states that every algebraic expression deducible from the postulate of Boolean
algebra remains valid if the operators and identity elements are interchanged.
When applying duality theorem, we simply interchange OR and AND operators
and replaced 1s by 0s and 0s by 1s. For example A+1 =1, by duality A.1 =
0.The variables are not complemented in this process
2.13
2. Look for identical terms. Only one of those terms be retained and all others
dropped.
AB+AB+AB++AB+AB = AB
3. Look for variable and its negation in the same term. This term can be
dropped.
AB A ABB C ABCC 0
4. Look gor the pairs of terms that are identical except for one variable which
may be missing in of the terms. The larger term cam be dropped.
AB C D AB C ABC
5. Look for the pairs of terms, which have the same variables, with one or
more variables complemented. If a variable in term of such a pair is
complemented while in the second term it is not, then such term can be
combined into a single term with that variable dropped.
= AB C D AB C D ABC
Boolean expressions and logic diagrams:
Can be realized as hardware using logic gates. Conversely, hardware can be
translated into Boolean expression for analysis of circuits.
1. Converting Boolean expressions to logic:
To start with the output and work towards the input.
2. Converting logic to Boolean expressions:
To start with the input and work towards the output.
2.14
(1) Each maxterm is obtained from an OR term of the n variables, with each
variable being unprimed if the corresponding bit is a 0 and primed if a 1,
and
(2) Each maxterms is the complement of its corresponding minterms and vice
versa.
(i)
SOP (sum of the Product terms ) sum of Minterms:
It is sometimes convenient to express a Boolean function in its sum-of-minterms
form. If the function is not in this form, it can be made so by first expanding the
expression in to a sum of AND terms. Each term is then inspected to see if it
contains all the variables. If it misses one or more variables, it is ANDed with an
expression such as A A , where A is one of the missing variables.
Steps for the expansion of a Boolean expression in SOP form to the standard SOP
form:
1. Write down all the terms.
2. If one or more variable are missing in any term, expand that term by
multiplying it with the sum of each of the missing variables and its
compliments.
3. Drop out redundant terms.
4. Direct method:
a. Write down all the terms.
b. Put Xs in terms where variable must be inserted to form a minterm.
c. Replace the non-complimented variable by 1 and the complemented
variables by 0, and use all combinations of Xs in terms of 0 and 1 to
generate minterms.
d. Droup out all the redundant terms.
If the Boolean function in sum of products (SOP) form. Consider the given logic
function in SOP form; y1 AB CD .This function can be implemented with (a)
AND and OR gates, (b) NAND-NAND, and (c) NOR-NOR as shown in Fig.3.3.1.
In (b) the AND gates are replaced by NAND gates and the OR gates by NAND
gates with an OR-invert graphic symbol (bubbled OR), similarly in (c) the AND
gates are replaced by NOR gates and the OR gates by NOR gates. Remember that
a bubble denotes complementation and two bubbles along the same line represent
double complementation, so both can be removed. Therefore, the given SOP
equation is implemented by universal gates only, but minimum number of
gates/IC is required in NAND-NAND implementation.
Following tables summarizes the converting non standard SOP to standard form
and vice versa.
SOP
Standard
SOP
y AB A
y BA A B
y B A
In second term B is In first term A and in No missing terms
missing
second term B is
missing
y AB A ( B B )
y ( A A ) B A ( B B ) y BA A B
AB A B A B
AB A B A B A B
64
y AB A X
y XB A X
y AB A B
11 00 01
01 10 10 11
11 00
m (0,2,3)
m ( m 0 m 2 m3 )
m ( m 0 m3 )
m 0 m 2 m3
y AB A ( BB )
y ( A A)B A(B B )
y BA A B
AB A B A B
Missing minterms
AB A B A B A B
Missing minterms
Missing minterms
y M (M 1 )
y M (M 1 )
y M (M 1 .M 2 )
POS
yB
yA
y B A
Standard
POS
y AA B
y A BB
( A B ).( A B )
y ( A B ).( A B )
y B A
M ( M 0 )
M ( M 0 .M 2 )
M ( M 2 .M 3 )
Missing Maxterm
Missing Maxterm
Standard
SOP
Standard
POS
Standard
POS
Standard
SOP
y m(1.3)
Table 37.
y m(0,1)
Missing Maxterm
y m(1,2,3)
POS function:
Steps for the expansion of a Boolean expression in POS form to the standard POS
form:
1. Write down all the terms.
2. If one or more variable are missing in any term, expand that term by
adding it with the product of each of the missing variables and its
compliments.
3. Drop out redundant terms.
4. Direct method:
a. Write down all the terms.
b. Put Xs in terms where variable must be inserted to form a maxterms.
c. Replace the non-complimented variable by 0 and the complemented
variables by 1, and use all combinations of Xs in terms of 1 and 0
to generate maxterms.
d. Drop out all the redundant terms.
If the Boolean function in sum of products (POS) form. Consider the given logic
function in POS form; y2 ( A B).(C D) .This function can be implemented
with (a) OR and AND gates, (b) NOR- NOR, and (c) NAND-NAND, as shown in
Fig.3.3.2. In (b) the OR gates are replaced by NOR gates and the AND gates by
NOR gates with an AND-invert graphic symbol (bubbled AND), similarly in (c)
the AND gates are replaced by NAND gates and the OR gates by NAND gates.
Remember that a bubble denotes complementation and two bubbles along the
same line represent double complementation, so both can be removed. Therefore,
the given POS equation is implemented by universal gates only, but minimum
number of gates/IC is required in NOR-NOR implementation.
65
Boolean addition is equivalent to the OR logic function, as well as parallel switch contacts.
Boolean multiplication is equivalent to the AND logic function, as well as series switch contacts.
Boolean complementation is equivalent to the NOT logic function, as well as normally-closed relay
contacts.
DeMorgan's Theorems describe the equivalence between gates with inverted inputs and gates with
inverted outputs. Simply put, a NAND gate is equivalent to a Negative-OR gate, and a NOR gate is
equivalent to a Negative-AND gate.
When "breaking" a complementation bar in a Boolean expression, the operation directly underneath
the break (addition or multiplication) reverses, and the broken bar pieces remain over the respective
terms.
It is often easier to approach a problem by breaking the longest (uppermost) bar before breaking any
bars under it. You must never attempt to break two bars in one step!
Complementation bars function as grouping symbols. Therefore, when a bar is broken, the terms
underneath it must remain grouped. Parentheses may be placed around these grouped terms as a help
to avoid changing precedence.
Sum-Of-Products, or SOP, Boolean expressions may be generated from truth tables quite easily, by
determining which rows of the table have an output of 1, writing one product term for each row, and
finally summing all the product terms. This creates a Boolean expression representing the truth table
as a whole.
Sum-Of-Products expressions lend themselves well to implementation as a set of AND gates
(products) feeding into a single OR gate (sum).
Product-Of-Sums, or POS, Boolean expressions may also be generated from truth tables quite easily,
by determining which rows of the table have an output of 0, writing one sum term for each row, and
finally multiplying all the sum terms. This creates a Boolean expression representing the truth table
as a whole.
Product-Of-Sums expressions lend themselves well to implementation as a set of OR gates (sums)
feeding into a single AND gate (product).
NAND and NOR gates are universal: that is, they have the ability to mimic any type of gate, if
interconnected in sufficient numbers.
To convert a gate circuit to a Boolean expression, label each gate output with a Boolean subexpression corresponding to the gates' input signals, until a final expression is reached at the last
gate.
To convert a Boolean expression to a gate circuit, evaluate the expression using standard order of
operations: multiplication before addition, and operations within parentheses before anything else.
To convert a ladder logic circuit to a Boolean expression, label each rung with a Boolean subexpression corresponding to the contacts' input signals, until a final expression is reached at the last
coil or light. To determine proper order of evaluation, treat the contacts as though they were resistors,
and as if you were determining total resistance of the series-parallel network formed by them. In
other words, look for contacts that are either directly in series or directly in parallel with each other
first, then "collapse" them into equivalent Boolean sub-expressions before proceeding to other
contacts.
To convert a Boolean expression to a ladder logic circuit, evaluate the expression using standard
order of operations: multiplication before addition, and operations within parentheses before
anything else.
Logic gates most commonly used are AND, OR. NOT. NAND, NOR, XOR. XNOR
NAND and NOR are universal gates.
Output of AND gate is low even if one input is low (Y = A.B) where A and B are inputs and Y is the
output.
Output of OR gate is high if any one input is high (Y = A + B)
In NOT gate, when a high is applied as input, a low appears at output and vice versa.
66
NAND gate has output high when any one of its input is low.
The output of NOR gate is high when any input is low.
Output of XOR gate is high if one an only one input is high.
The output of XNOR gate is high when all inputs are high.
NAND and NOR can be used to realize any gate.
SOP involves sum of given product terms and these terms are known as minterms (m).
POS involves product of given sum terms of these are known as maxterms (M).
67
Problems:
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
2.27
2.28
2.29
2.30
2.31
2.32
2.33
2.34
2.35
2.36
2.37
69