Ejemplos VHDL

Divisin de frecuencia
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity div_clk IS
port ( reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
clk_out : OUT STD_LOGIC);
end div_clk;
architecture arch of div_clk is
signal clk_cnt : unsigned(25 downto 0);
signal clk_bit : std_logic;
begin
gen_clock: process (clk, reset) is
begin
if (reset = '0') then
clk_cnt <= "00000000000000000000000000"; -- <= (others =>
'0')
clk_bit <= '0';
elsif (clk'event and clk='1') then
if (clk_cnt = 49999999) then
ck_cnt <= "00000000000000000000000000"; -- <= (others
=> '0')
clk_bit <= not clk_bit;
else
clk_cnt <= clk_cnt + 1;
end if;
end if;
end process;
clk_out <= clk_bit;
end arch;

Otro divisor de frecuencia

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity delay_clock is
port (
Clk50Mhz: in STD_LOGIC;
Clk: out STD_LOGIC
);
end delay_clock;
architecture arch of delay_clock is
constant max: INTEGER := 50000000;
constant half: INTEGER := max/2;
signal count: INTEGER range 0 to max;
begin
process
begin
wait until Clk50Mhz'event and Clk50Mhz = '1';
if count < max then

count <= count + 1;

else
count <= 0;
end if;
if count < half then
Clk <= '0';
else
Clk <= '1';
end if;
end process;
end arch;

Multiplexacin en el tiempo para uso de display de 7 segmentos

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity disp_mux is
port (
clk, reset: in std_logic;
in3, in2, in1, in0: in std_logic_vector(7 downto 0);
an: out std_logic_vector (3 downto 0);
sseg : out std_logic_vector (7 downto 0)
);
end disp_mux ;
architecture arch of disp_mux is
-- Refresco cerca de los 800Hz ( 50 MHz / 2^16 )
constant N : integer :=18;
signal q_reg , q_next : unsigned (N-1 downto 0);
signal sel: std_logic_vector (1 downto 0);
begin
--registro
process (clk, reset)
begin
if reset='l' then
q_reg <= ( others = > '0');
elsif (clk'event and clk='l') then
q_reg <= q_next;
end if;
end process ;
-- proximo estado logico para el contador
q_next <= q_reg + 1;
-- Los 2 MSB del contador controlan el multiplexor 4 a 1
-- y generan la seal de habilitacin del nodo
sel <= std_logic_vector(q_reg(N-1 downto N-2));
process (sel, in0, in1, in2, in3)
begin
case sel is
when "00" =>
an <= "1110";
sseg <= in0;
when "01" =>
an <= "1101";
sseg <= inl;
when "10" =>
an <= "1011";
sseg <= in2;

when others = >

an <= "0111";
sseg <= in3;
end case;
end process;
end arch;

Mquina de Estados tipo Mealy

library ieee;
use IEEE.std_logic_1164.all;
entity fsm_mealy is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end fsm_mealy;
architecture behavioral of fsm_mealy is
type state_type is (s0,s1,s2,s3); --Tipo Maquina de Estado
signal current_s,next_s: state_type; --Estado actual y proximo estado
begin
process (clk,reset)
begin
if (reset='1') then
current_s <= s0; --Estado inicial.
elsif (rising_edge(clk)) then --o elsif (clk'event and clk = '1')
then
current_s <= next_s;
--Cambio de estado.
end if;
end process;
--Process de la Maquina de Estado.
process (current_s,input)
begin
case current_s is
when s0 =>
--Cuando el estado actual es "s0"
if(input ='0') then
output <= '0';

next_s <= s1;

else
output <= '1';
next_s <= s2;
end if;
when s1
if(input
output
next_s
else
output
next_s
end if;

=>;
--Cuando el estado actual es "s1"
='0') then
<= '0';
<= s3;
<= '0';
<= s1;

when s2 =>
--Cuando el estado actual es "s2"
if(input ='0') then
output <= '1';
next_s <= s2;
else
output <= '0';
next_s <= s3;
end if;

when s3 =>
if(input
output
next_s
else
output
next_s
end if;
end case;
end process;

--Cuando el estado actual es "s3"

='0') then
<= '1';
<= s3;
<= '1';
<= s0;

end behavioral;

Buffer Triestado

Los registros de tres estados (buffers tri-estado) tienen diversas aplicaciones, ya sea como
salidas de sistemas (modo buffer) o como parte integral de un circuito. En VHDL estos
dispositivos son definidos a travs de los valores que manejan (0,1 y alta impedancia 'Z').
En la figura se observa el diagrama correspondiente a este circuito, y a continuacin el
cdigo que describe su funcionamiento.

library ieee;
use ieee.std_logic_1164.all ;
entity tri_est is port(
enable, entrada: in std_logic;
salida: out std_logic);
end tri_est;
architecture arq_buffer of tri_est is

begin
process (enable, entrada) begin
if enable = '0' then
salida <= 'Z';
else
salida <= entrada;
end if;
end process ;
end arq_buffer;