CS623 – CAD for VLSI

Lecture 43 – Static Timing Analysis

Shankar Balachandran
Dept. of Computer Science and Engineering
IIT-Madras
shankar@cse.iitm.ernet.in

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Timing Analysis
• Identify the potential performance of a circuit
• Many variations in timing
– Rise time vs Fall time
– Setup, Hold violations
– Gate delays and interconnect delays
– Exponential number of paths
– Clock skew and jitter

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Dynamic Timing Analysis
• Give test vectors at inputs
• Observe the changes in all gates
• Follow it through to the outputs
• Find the worst case time

• Not a simple problem :

– Order of inputs matter
– Simulation is tedious
– Mixes logic and timing, which failed and why is
difficult to discern
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A Simplified Model
• Assume rise and fall times are similar
• Gate delays are characterized ahead of time
• Many good models for predicting interconnect
delay
• Assume clock skew = 0

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A Simple Problem?
• Let’s ignore interconnect delays for now
• What do we need to do :
– Perform timing analysis between all flops to flops
– Find the worst case delay in each sequential stage
– Assign clock accordingly
– Design algorithms
• Does not solve the inputs and the order of
supply though

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A Naïve Algorithm
• Enumerate all paths
• Calculate delay on each path
• Find the worst case delay
• Problem?
– Exponential Number of Paths
– Exponential algorithm
• Why is this bad?
– Timing analysis done many times during synthesis,
place and route

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Static Timing Analysis
• Done without specifying vectors
• A very powerful technique, widely used
• A big turn in the EDA industry
– Hitchcock’s Algorithm
– Exhaustive without specifying vectors
– Linear in number of gates
• Not edges, not paths

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Basic Sketch
• Find when outputs are required at the different
gates
• Find out when they are actually arriving
• If the signals arrive at every gate before they
are required in every single gate, we are done
– Circuit is safe
• Else
– Pick better gates
– Restructure the circuit

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Arrival Time

0 1 7 13 18
1 4 6 5

0 3 9 22
3 6 6 15 7

0 1 7 18
4 14
1 5 4

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Required Time

1 4 6 5
4 5 9 15 22

22
3 6 6 15 7
0 3 9
15

1 4 5 4
8 9 13 18 22

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Which Nodes are Critical?
• Any node where signals arrive just in time
• Simply put
– Required Time (i) = Arrival Time (i)
• Not every node is critical
• A path with all nodes that are critical is called
the critical path

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Which Are Critical?

0 1 7 13 18
1 4 6 5
4 5 9 15 22

0 3 9 15 22
3 6 6 7
0 3 9 15

0 1 7 18
4 14
1 5 4
8 9 13 18 22

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Definitions
• Arrival Time
– AT(i) = max [AT(j)] + delay (i) where j є fanin(i)
• Required Time
– RT(i) = min [RT(j)) – delay (j)] where j є fanout(i)
– Remember that delay (j) is subtracted here
– Also, notice that min encompasses subtraction
• Define Slack
– Slack(i) = RT(i) – AT(i)
– Slack == 0 => Node is critical
– A path whose nodes all have slack 0 = critical path

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Slacks

4 4 2 2 4
1 4 6 5

0
3
0
6 0 6 0 7 0

8 8 6 4 4
1 4 5 4

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Let’s Change Required Time
0 1 7 13 18
1 4 6 5
2 3 7 13 20

0 3 9 15 22
3 6 6 7
-2 1 7 13 20
13
Arrive in 0 1 7 18
14
the past? 1 4 5 4
6 7 11 16 20

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Let’s Redo Slacks
Critical Edges

2 2 0 0 2
1 4 6 5

Failing Path

-2
3
-2
6 -2 6 -2 7 -2

6 6 4 2 2
1 4 5 4

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Specifying Required Time
• Run as fast as you can
– First case
– Pick the max(AT) as RT(outputs)
• Can the circuit run as fast as T
– Second case
– Fix RT(outputs) = T
• Calculate Arrival Times as before
• Calculate slacks as before
• Check if there are paths that are violating timing

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Observations on Slacks
• For a circuit to run safely
– All slacks ≥ 0
• When slacks are less than 0
– Relax the constraints
– Pick gates with lesser delays
• The model ignores interconnect delay
– Easily extendable for interconnect delay
• More discussion later

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