KNL4343

VLSI Design And Technology

Lecture 06: Static CMOS Logic
Norhuzaimin Julai

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

Review: CMOS Process at a Glance

Define active areas
Etch and fill trenches

One full photolithography

sequence per layer
(mask)

Built (roughly) from the

bottom up

Implant well regions

Deposit and pattern

polysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windows

Deposit and pattern metal layers

4
2
3
1

metal
polysilicon
exception!
source and drain diffusions
tubs (aka wells, active areas)

CMOS Circuit Styles

Static complementary CMOS - except during switching,

output connected to either VDD or GND via a lowresistance path

high noise margins

- full rail to rail swing
- VOH and VOL are at VDD and GND, respectively

low output impedance, high input impedance

no steady state path between VDD and GND (no static power
consumption)
delay a function of load capacitance and transistor resistance
comparable rise and fall times (under the appropriate transistor
sizing conditions)

Dynamic CMOS - relies on temporary storage of signal

values on the capacitance of high-impedance circuit
nodes

simpler, faster gates

increased sensitivity to noise

Static Complementary CMOS

Pull-up network (PUN) and pull-down network (PDN)

VDD

PMOS transistors only

In1
In2

PUN

InN
In1
In2
InN

pull-up: make a connection from VDD to F

when F(In1,In2,InN) = 1
F(In1,In2,InN)

PDN

pull-down: make a connection from F to

GND when F(In1,In2,InN) = 0
NMOS transistors only

PUN and PDN are dual logic networks

Threshold Drops
VDD

PUN

VDD

VDD
D

0 VDD

VGS

CL

VDD 0

PDN
D

VDD
S

CL

0 VDD - VTn
CL

VGS

VDD |VTp|
S

CL

Construction of PDN

NMOS devices in series implement a NAND function

AB
A
B

NMOS devices in parallel implement a NOR function

A+B

Dual PUN and PDN

PUN and PDN are dual networks

DeMorgans theorems
A+B=AB

[!(A + B) = !A !B or !(A | B) = !A & !B]

AB=A+B

[!(A B) = !A + !B or !(A & B) = !A | !B]

a parallel connection of transistors in the PUN corresponds to a

series connection of the PDN

Complementary gate is naturally inverting (NAND,

NOR, AOI, OAI)

Number of transistors for an N-input logic gate is 2N

CMOS NAND

AB

A
B

A
B

CMOS NOR

B
A
A+B
A

A
B

Complex CMOS Gate

B
A
C
D
OUT = !(D + A (B + C))
A
D

Standard Cell Layout Methodology

Routing
channel
VDD

signals

GND

What logic function is this?

OAI21 Logic Graph

B
X = !(C (A + B))
C
A

PUN

X
B

VDD
j

B
A
B
C

GND

A
PDN

Two Stick Layouts of !(C (A + B))

VDD

VDD

GND

GND

uninterrupted diffusion strip

Consistent Euler Path

An uninterrupted diffusion strip is possible only if there

exists a Euler path in the logic graph

Euler path: a path through all nodes in the graph such that
each edge is visited once and only once.
X
C
i

X
B

VDD
j

GND

A
A B C

For a single poly strip for every input signal, the Euler
paths in the PUN and PDN must be consistent (the same)

OAI22 Logic Graph

X
D

X = !((A+B)(C+D))
C

C
VDD

X
B

A
B
C
D

PUN

GND

PDN

OAI22 Layout
A

VDD

GND

Some functions have no consistent Euler path like

x = !(a + bc + de) (but x = !(bc + a + de) does!)

XNOR/XOR Implementation
XNOR

XOR

A
AB

A
B

AB

A
B
AB

How many transistors in each?

Can you create the stick transistor

layout for the lower left circuit?

AB

VTC is Data-Dependent
0.5/0.25 NMOS
0.75 /0.25 PMOS

M3 B

M4
2

A,B: 0 -> 1
B=1, A:0 -> 1
A=1, B:0->1

F= A B
D

S
D

M1

VGS1 = VB

M2

VGS2 = VA VDS1

weaker
PUN

Cint

0
0

The threshold voltage of M2 is higher than M1 due to the

body effect ()
VTn1 = VTn0
VTn2 = VTn0 + ((|2F| + Vint) - |2F|)
since VSB of M2 is not zero (when VB = 0) due to the presence of Cint

Static CMOS Full Adder Circuit

!Cout = !Cin & (!A | !B) | (!A & !B)

!Sum = Cout & (!A | !B | !Cin) | (!A & !B & !Cin)

B

B
A

Cin

Cin

Cin

!Cout

!Sum

A
A

Cin
A

Cin

Cout = Cin & (A | B) | (A & B)

Sum = !Cout & (A | B | Cin) | (A & B & Cin)

Next Time: Pass Transistor Circuits

AB

Next Lecture and Reminders

Next lecture

Pass transistor logic

- Reading assignment Rabaey, et al, 6.2.3

Reminders