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Hex Inverter Buffer Driver
Hex Inverter Buffer Driver
SN54LS06 . . . J PACKAGE
SN74LS06, SN74LS16 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
Design
Open-Collector Driver for Indicator Lamps
and Relays
Inputs Fully Compatible With Most TTL
Circuits
1A
1Y
2A
2Y
3A
3Y
GND
description/ordering information
These hex inverter buffers/drivers feature
high-voltage open-collector outputs to interface
with high-level circuits (such as MOS), or for
driving high-current loads, and also are
characterized for use as inverter buffers for driving
TTL inputs. The LS06 devices have a rated output
voltage of 30 V, and the SN74LS16 has a rated
output voltage of 15 V. The maximum sink current
for the SN54LS06 is 30 mA, and for the
SN74LS06 and SN74LS16 it is 40 mA.
14
13
12
11
10
VCC
6A
6Y
5A
5Y
4A
4Y
1Y
1A
NC
VCC
6A
SN54LS06 . . . FK PACKAGE
(TOP VIEW)
2A
NC
2Y
NC
3A
1 20 19
18
17
16
15
14
9 10 11 12 13
6Y
NC
5A
NC
5Y
3Y
GND
NC
4Y
4A
NC No internal connection
ORDERING INFORMATION
PDIP N
0C
0
C to 70
70C
C
ORDERABLE
PART NUMBER
PACKAGE
TA
TOP-SIDE
MARKING
Tube
SN74LS06N
Tube
SN74LS06D
SN74LS06DR
SOP NS
SN74LS06NSR
74LS06
SSOP DB
SN74LS06DBR
LS06
Tube
SN54LS06J
SN54LS06J
Tube
SNJ54LS06J
SNJ54LS06J
Tube
SNJ54LS06FK
SNJ54LS06FK
SOIC D
CDIP J
55C
55
C to 125
125C
C
LCCC FK
SN74LS06N
LS06
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
2A
3A
4A
5A
6A
1Y
2Y
11
10
13
12
3Y
4Y
5Y
6Y
2.5 k
15 k
1 k
Output
2.5 k
Input
2 k
2 k
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Output voltage, VO (see Notes 1 and 2): SN54LS06, SN74LS06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. This is the maximum voltage that should be applied to any output when it is in the off state.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54LS06
VCC
VIH
Supply voltage
VIL
NOM
MAX
MIN
NOM
MAX
4.5
5.5
4.75
5.25
LS06
VOH
IOL
TA
0.8
0.8
30
30
15
30
55
125
V
V
SN74LS16
UNIT
MIN
V
V
40
mA
70
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
MIN
VIK
VCC = MIN,
SN74LS06
SN74LS16
SN54LS06
TEST CONDITIONS
PARAMETER
TYP
II = 12 mA
IOH
VCC = MIN,
VIL = 0.8 V
LS06, VOH = 30 V
SN74LS16, VOH = 15 V
VOL
VCC = MIN,
VIH = 2 V
IOL = 16 mA
IOL = 30 mA
IOL = 40 mA
MAX
MIN
TYP
UNIT
MAX
1.5
1.5
0.25
0.25
0.25
0.25
0.4
0.25
V
mA
0.4
0.7
V
0.7
II
IIH
VCC = MAX,
VCC = MAX,
VI = 7 V
VI = 2.4 V
20
20
IIL
ICCH
VCC = MAX,
VCC = MAX
VI = 0.4 V
0.2
0.2
mA
18
18
mA
60
mA
ICCL
VCC = MAX
60
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V, and TA = 25C.
mA
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
TEST CONDITIONS
RL = 110 ,
CL = 15 pF
MIN
MAX
15
10
20
UNIT
ns
VCC
RL
(see Note B)
From Output
Under Test
CL
(see Note A)
High-Level
Pulse
1.3 V
S2
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3V
Timing
Input
1.3 V
5 k
Test
Point
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
S1
(see Note B)
CL
(see Note A)
RL
CL
(see Note A)
RL
From Output
Under Test
VCC
From Output
Under Test
Test
Point
1.3 V
0V
tw
Low-Level
Pulse
1.3 V
tsu
0V
In-Phase
Output
(see Note D)
3V
1.3 V
1.3 V
0V
tPZL
tPLZ
tPHL
VOH
1.3 V
1.3 V
Waveform 1
(see Notes C
and D)
VOL
tPZH
tPLH
VOH
1.3 V
1.3 V
VOL
Waveform 2
(see Notes C
and D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
1.3 V
VOL
tPHL
Out-of-Phase
Output
(see Note D)
1.3 V
0V
Output
Control
(low-level
enabling)
1.3 V
tPLH
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.3 V
3V
Data
Input
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
th
VOL + 0.5 V
tPHZ
VOH
1.3 V
VOH 0.5 V
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
www.ti.com
24-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
5962-9861701Q2A
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
59629861701Q2A
SNJ54LS
06FK
5962-9861701QCA
ACTIVE
CDIP
14
TBD
A42
-55 to 125
5962-9861701QC
A
SNJ54LS06J
SN54LS06J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
SN54LS06J
SN74LS06D
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
SN74LS06DBLE
OBSOLETE
SSOP
DB
14
TBD
Call TI
Call TI
0 to 70
SN74LS06DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS06
SN74LS06DBRG4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS06
SN74LS06DG4
ACTIVE
SOIC
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS06
SN74LS06DR
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS06
SN74LS06DRE4
ACTIVE
SOIC
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
LS06
SN74LS06N
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN74LS06N
SN74LS06NE4
ACTIVE
PDIP
14
25
Pb-Free
(RoHS)
CU NIPDAU
0 to 70
SN74LS06N
SN74LS06NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS06
SN74LS06NSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
74LS06
SN74LS16D
OBSOLETE
SOIC
14
TBD
Call TI
Call TI
0 to 70
SN74LS16DR
OBSOLETE
SOIC
14
TBD
Call TI
Call TI
0 to 70
SN74LS16N
OBSOLETE
PDIP
14
TBD
Call TI
Call TI
0 to 70
SNJ54LS06FK
ACTIVE
LCCC
FK
20
TBD
POST-PLATE
-55 to 125
Addendum-Page 1
LS06
5962-
Samples
www.ti.com
24-Apr-2015
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
9861701Q2A
SNJ54LS
06FK
SNJ54LS06J
ACTIVE
CDIP
14
TBD
A42
-55 to 125
5962-9861701QC
A
SNJ54LS06J
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 2
Samples
www.ti.com
24-Apr-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LS06, SN74LS06 :
Catalog: SN74LS06
Military: SN54LS06
NOTE: Qualified Version Definitions:
Addendum-Page 3
8-Apr-2013
Device
SN74LS06DBR
DB
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
8.2
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
6.6
2.5
12.0
16.0
Q1
8-Apr-2013
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LS06DBR
SSOP
DB
14
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
08
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
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