Physical Address Extension

In computing, Physical Address Extension (PAE) is a

memory management feature for the IA-32 architecture,
rst introduced in the Pentium Pro. It denes a page table
hierarchy of three levels, with table entries of 64 bits each
instead of 32, allowing these CPUs to access a physical
address space larger than 4 gigabytes (232 bytes).

and (in a at memory model) is limited to 4 gigabytes

of virtual address space. Operating systems supporting
this mode use page tables to map the regular 4 GB address space into the physical memory, which, depending
on the operating system, may be as big as 64 GB. The
mapping is typically applied separately for each process,
The page table structure used by x86-64 CPUs when op- so that the extra memory is useful even though no single
erating in 64-bit mode further extends the page table hier- regular application can access it all simultaneously.
archy to four levels, extending the virtual address space, Later work associated with AMDs development of x86and uses additional physical address bits at all levels of 64 architecture expanded the theoretical possible size of
the page table, extending the physical address space. It physical addresses to 52 bits.
also uses the topmost bit of the 64-bit page table entry as
an NX bit.

3 Page table structures

1

History

In protected mode, x86 processors use a two-level page

translation scheme, where the control register CR3 points
PAE was rst implemented in the Intel Pentium Pro to a single 4 KB long page directory divided into 1024 4
in 1995,[1] although the accompanying chipsets usually byte entries that point to 4 KB long page tables, similarly
lacked support for the required extra address bits.[2]
consisting of 1024 4 byte entries pointing to 4 KB long
PAE is supported by Intel Pentium Pro and later Pentium- pages.
series processors except most 400 MHz-bus versions of Enabling PAE (by setting bit 5, PAE, of the system regthe Pentium M. It was also available on AMD processors ister CR4) causes major changes to this scheme. By deincluding the AMD Athlon[3] (although the chipsets for fault, the size of each page remains as 4 KB. Each entry in
these were limited to 4 GB RAM[4] ) and later AMD pro- the page table and page directory becomes 64 bit long (8
cessor models.
bytes), instead of 32 bits, to allow for additional address
When AMD dened their AMD64 architecture as an ex- bits. However, the size of tables does not change, so both
tension of x86, they dened an enhanced version of PAE table and directory now have only 512 entries. Because
to be used while the processor was in 64-bit mode ("long this allows only one quarter of the entries of the original
mode"). It supports up to 48-bit virtual addresses,[5](p120) scheme, an extra level of hierarchy has been added, so
52-bit physical addresses,[5](p24) and includes NX bit CR3 now points to Page Directory Pointer Table, a short
functionality. This version of PAE is the mandatory table containing four pointers to page directories.
memory paging model in long mode on x86-64 proces- The entries in the page directory have an additional ag
sors; there is no non-PAE mode while in long mode.[6] in bit 7, named PS (for page size). If the system has set
The documentation for Intel 64, the Intel version of this bit to 1, the page directory entry does not point to
x86-64, refers to these page table formats as IA-32e pag- a page table but to a single, large 2 MB page (Page Size
ing rather than PAE.[7]
Extension).

In all page table formats supported by x86 and x86-64,

the 12 least signicant bits of the page table entry are either interpreted by the memory management unit or are
reserved for operating system use. In processors that implement the no-execute or execution disable feature,
the most signicant bit (bit 63) is the NX bit. The next
eleven most signicant bits (bits 52 through 62) are reserved for operating system use by both Intel and AMDs
architecture specications. Thus, from 64 bits in the page
table entry, 12 low-order and 12 high-order bits have
other uses, leaving 40 bits (bits 12 though 51) for the

Design

With PAE, IA-32 architecture is augmented with additional address lines used to select the additional memory,
so physical address size increases from 32 bits to 36 bits.
This increases the physical memory addressable by the
system from 4 GB to 64 GB. The 32-bit size of the virtual address is not changed, so regular application software continues to use instructions with 32-bit addresses
1

physical page number. Combined with 12 bits of oset within page from the page table entry, a maximum
of 52 bits are available to address physical memory. This
allows a maximum RAM conguration of 252 bytes, or 4
petabytes (about 4.51015 bytes).
On x86-64 processors in native long mode, the address
translation scheme uses PAE but adds a fourth table, the
512-entry page-map level 4 table, and extends the page
directory pointer table to 512 entries instead of the original 4 entries it has in protected mode. Currently 48 bits
of virtual page number are translated, giving a virtual address space of up to 256 TB.[5](p120) In the page table entries, in the original specication, 40 bits of physical page
number are implemented.
Page table structures
No PAE, 4 KB pages

OPERATING SYSTEM SUPPORT

the 4 GB address limit. However, it led to compatibility problems with 3rd party drivers which led Microsoft
to remove this capability in Windows XP Service Pack
2. Windows XP SP2 and later, by default, on processors
with the no-execute (NX) or execute-disable (XD) feature, runs in PAE mode in order to allow NX.[15] The no
execute (NX, or XD for execution disable) bit resides in bit
63 of the page table entry and, without PAE, page table
entries on 32-bit systems have only 32 bits; therefore PAE
mode is required in order to exploit the NX feature. However, client versions of 32-bit Windows (Windows XP
SP2 and later, Windows Vista, Windows 7) limit physical address space to the rst 4 GB for driver compatibility [11] via the licensing limitation mechanism,[10] even
though these versions do run in PAE mode if NX support
is enabled.
Windows 8 will only run on processors which support
PAE, in addition to NX and SSE2.[16]

No PAE, 4 MB pages
With PAE; 4 KB pages
With PAE; 2 MB pages

Support

See also: CPUID

Software can identify via the CPUID ag PAE whether a
CPU supports PAE mode or not. A free-of-charge program for Microsoft Windows is available which will list
many processor capabilities, including PAE support.[8] In
Linux, commands such as cat /proc/cpuinfo can list the
pae ag when present,[9] as well as other tools such as the
SYSLINUX Hardware Detection Tool.

5.2 OS X
All Intel versions of OS X support PAE and the NX bit.
Mac Pro and Xserve systems can use up to 64 GB of
RAM.[17]

5.3 Linux
See also: Executable space protection Linux

The Linux kernel includes full PAE mode support starting

with version 2.3.23,[18] enabling access of up to 64 GB of
memory on 32-bit machines. A PAE-enabled Linux kernel requires that the CPU also support PAE. The Linux
kernel supports PAE as a build option and major distributions provide a PAE kernel either as the default or as
To use PAE, motherboard and operating system support an option.
is required.
The NX bit feature requires a kernel built with PAE
support.[19]

Operating system support

Linux distributions now commonly use a PAE-enabled

kernel as the default, a trend that began in 2009.[20] As
of 2012 many, including Red Hat Enterprise Linux /
5.1 Microsoft Windows
CentOS, Ubuntu (and derivatives like Linux Mint),[21][22]
Microsoft Windows supports PAE if booted with the ap- have stopped distributing non-PAE kernels, thus making
propriate option, but according to Geo Chappell, Mi- PAE hardware mandatory.
crosoft may limit 32-bit versions of Windows to 4 GB Distributions that still provide a non-PAE option, inas a matter of its licensing policy.[10] Microsoft Tech- cluding Debian (and derivatives like LMDE), Slackware,
nical Fellow Mark Russinovich says that some drivers and LXLE typically do so with i386, i486 or retro
were found to be unstable when encountering physical ad- labels.[23][24]
dresses above 4 GB.[11]
The following table shows the hard memory limits for IA5.4 Others
32-based versions of Microsoft Windows, with PAE enabled:
FreeBSD and NetBSD also support PAE as a kernel build
The original releases of Windows XP and Windows XP option. FreeBSD supports PAE in the 4.x series startSP1 used PAE mode to allow RAM to extend beyond ing with 4.9, in the 5.x series starting with 5.1, and in

3
all 6.x and later releases. Support requires the kernel
PAE conguration-option. Loadable kernel modules can
only be loaded into a kernel with PAE enabled if the
modules were built with PAE enabled; the binary modules in FreeBSD distributions are not built with PAE enabled, and thus cannot be loaded into PAE kernels. Not
all drivers support more than 4 GB of physical memory; those drivers won't work correctly on a system with
PAE.[25]
OpenBSD has had support for PAE since 2006 with the
standard GENERIC i386 kernel. GeNUA mbH supported the initial implementation.[26] Since release 5.0
PAE has had a series of changes, in particular changes
to i386 MMU processing for PMAP, see pmap(9).[27]
Solaris supports PAE beginning with Solaris version 7.
However, third-party drivers used with version 7 which
do not specically include PAE support may operate erratically or fail outright on a system with PAE.[28]

[6] Volume 2: System Programming (PDF). AMD64 Architecture Programmers Manual. Advanced Micro Devices. November 1, 2009. pp. 124143. Retrieved
2015-02-07. Long-mode page translation requires the use
of physical-address extensions (PAE). Before activating
long mode, PAE must be enabled by setting CR4.PAE to
1. Activating long mode before enabling PAE causes a
general-protection exception (#GP) to occur.
[7] Volume 3A: System Programming Guide, Part 1 (PDF).
Intel 64 and IA-32 Architectures Software Developers
Manual. Intel Corporation. January 2015. pp. 419
through 429. Retrieved 2015-02-07. A logical processor uses IA-32e paging if CR0.PG = 1, CR4.PAE = 1, and
IA32_EFER.LME = 1.
[8] Microsoft Sysinternals: Coreinfo. Windows Sysinternals. Microsoft. 19 December 2013. Retrieved 20 April
2014.
[9] Detecting your Hardware. Gentoo. October 8, 2008.
Retrieved 2013-04-28.

Haiku added initial support for PAE sometime after the

R1 Alpha 2 release. With the release of R1 Alpha 3 PAE [10] Chappell, Geo. Licensed Memory in 32-Bit Windows
is now ocially supported.
Vista. geochappell.com. WP:SPS. Retrieved 20 April
2014.

See also
Page Size Extension
PCI hole
PSE-36
Architecture of Windows NT
3 GB barrier
Large Physical Address Extension (LPAE) in the
ARM architecture

References

[1] T. Shanley (1998). Pentium Pro and Pentium II System Architecture. Addison-Wesley Professional. p. 439. ISBN
978-0-201-30973-7.
[2] Operating Systems and PAE Support. Hardware Developers Center. 14 July 2006. Retrieved 20 April 2014.
[3] AMD Athlon 500 - AMD-K7500MTR51B C. Cpuworld.com. 26 March 2014. Retrieved 20 April 2014.
[4] AMD-762 System Controller (p. 2): Supports up to 4
Gbytes of memory
[5] AMD Corporation (September 2012). Volume 2: System Programming (PDF). AMD64 Architecture Programmers Manual. AMD Corporation. Retrieved 201502-07.

[11] Mark Russinovich (2008-07-21). Pushing the Limits of

Windows: Physical Memory. Retrieved 2010-07-11.
[12] Memory Limits for Windows releases.
MSDN.
Microsoft. December 5, 2007. Retrieved 2007-12-10.
[13] Intel Physical Addressing Extensions (PAE) in Windows
2000. Support. Microsoft. October 26, 2007. Retrieved
2007-12-29.
[14] Overview of Windows Server 2003 R2 Datacenter Edition. TechNet. Microsoft. Retrieved 2009-05-15.
[15] The RAM reported by the System Properties dialog box
and the System Information tool is less than you expect in
Windows Vista or in Windows XP Service Pack 2 or later
version (MSKB 888137)". Knowledge Base. Microsoft.
Retrieved 2009-01-30.
[16] Khurshid, Usman (2 November 2012). How To Check If
Your Processor Supports PAE, NX And SSE2 For Windows 8 Installation. technize.net. Technize. Retrieved 20
April 2014.
[17] Road to Mac OS X 10.6 Snow Leopard: 64-Bits. 200809-26. Retrieved 2008-09-26.
[18] 2.3.23-pre4 x86 64 GB RAM changes [HIGHMEM
patch] explained a bit.
[19] Professional Linux Kernel Architecture, Figure 3.16 Code
ow for paging_init, Execute Disable Protection is also
enabled if supported by processor and if the kernel was
compiled with PAE support; unfortunately, the feature is
otherwise not available.
[20] x86 Specics for Fedora 11.
[21] EnablingPAE. Retrieved 2013-04-28.

8 FURTHER READING

[22] RHEL 6 Release Notes, 12.6. General Kernel Updates

12.6.1. Physical Address Extension (PAE)". RedHat.
Retrieved 27 November 2013.
[23] Precise Puppy. puppylinux.org. PuppyLinux. Retrieved
20 April 2014.
[24] 2.1. Supported Hardware. Debian GNU/Linux Installation Guide. SPI. Retrieved 20 April 2014.
[25] FreeBSD PAE(4) man page. 2003-04-08. Retrieved
2007-11-26.
[26] PAE for OpenBSD/i386 by Michael Shalaye, NYC.
2006. Retrieved 2014-09-03.
[27] OpenBSD pmap(9) man page. Retrieved 2014-09-03.
[28] Solaris 7 5/99 Release Notes (Intel Platform Edition), Appendix B: Hardware Compatibility List and Device Conguration Guide (Intel Platform Edition) 5/99.
1999. Retrieved 2007-11-26.

Further reading
Intel 64 and IA-32 Architectures Software Developers Manual, Volume 3A: System Programming
Guide, Part 1. Intel. 11 February 2014.
Physical Address Extension. MSDN. Microsoft.

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