Technical Brief 417

Example
The following example will illustrate the entire process of
compensation design for a synchronous buck converter.

Converter Parameters
Input Voltage:
Output Voltage:
Controller IC:
Osc. Voltage:
Switching Frequency:
Total Output Capacitance:
Total ESR:
Output Inductance:
Inductor DCR:
Desired Bandwidth:

VIN
VOUT
IC
VOSC
fSW
COUT
ESR
LOUT
DCR
DBW

5V
3.3V
ISL6520A
1.5V
300kHz
990F
5m
900nH
3m
90kHz

First, a Type II compensation network will be attempted. The

low ESR of the output capacitance and the low DCR of the
output inductor may make the implementation of a Type II
network difficult.
The guidelines given for designing a Type II network were
followed in order to calculate the following component
values:
R1 = 4.12k (chosen as the feedback component)
R2 = 125.8k
C1 = 8.464pF
C2 = 2.373nF
These calculated values need to be replaced by standard
resistor values before the gain and phase plots can be
plotted and examined.
R1 = 4.12k
R2 = 124k
C1 = 8.2pF
C2 = 2.2nF
Upon analysis of the bode plots in Figure 12, it can be seen
that the system does not meet the stability criteria previously
set. The bode plot for the gain is acceptable. The gain rolls
off at 20dB/decade with a perturbation at the resonant point
of the LC filter. After the perturbation, the gain again begins
to roll off about 20dB/decade until it crosses 0dB right
around 90kHz. The phase plot shows the problem with this
Type II system. The low ESR and DCR values create a very
sharp slope downward at the double pole of the LC filter.

The dive in the phase is so sharp that the 90o phase boost of
the Type II network does not compensate the phase enough
to have sufficient phase margin. At approximately 6kHz, the
phase margin goes below 45o and never recovers. There is
nothing more that the Type II system can do to improve the
phase. The Phase of the compensation is at its peak when
the phase of the filter is at its minimum.
Another problem with the Type II compensation network in
this example is that the compensation gain intersects and
then exceeds the gain of the error amplifier open loop gain.
As the open loop gain of the error amplifier is the limiting
factor to the compensation gain, the actual gain and phase is
affected by the limit and will not exceed it.
Due to these issues, a Type III network will need to be
implemented to compensate for the phase properly.
The guidelines for the Type III network were then followed to
produce the following component values:
R1 = 4.12k (chosen as the feedback component)
R2 = 20.863k
R3 = 151.85
C1 = 0.2587nF
C2 = 2.861nF
C3 = 6.987nF
Again, these calculated values need to be replaced by
standard resistor values before the gain and phase plots can
be plotted and examined.
R1 = 4.12k
R2 = 20.5k
R3 = 150
C1 = 0.22nF
C2 = 2.7nF
C3 = 6.8nF
The gain plot of the Type III compensated system in Figure
13 looks very good. The gain rolls off at -20dB/decade from
low frequency all the way to the 0dB crossover with a small
perturbation from the LC filter double pole resonant point.
The phase plot shows a system that is unconditionally
stable.

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