CH 02

CMOS Technology- Chapter 2
Text Book:
Silicon VLSI Technology

Fundamentals, Practice and
Modeling
g
Authors: J. D. Plummer, M. D. Deal,
and
a
d P. B. G
Griffin
SILICON VLSI TECHNOLOGY

Fundamentals, Practice and Modeling
By Plummer, Deal & Griffin
2000 by Prentice Hall

Upper Saddle River NJ
CMOS TECHNOLOGY
We will describe a modern CMOS process flow.
Typical CMOS technologies in manufacturing today add

additional steps to implement multiple device VTH, TFT
devices for loads in SRAMs, capacitors for DRAMs etc.
Process described here requires 16 masks

and > 100 process steps.
There are many possible variations on the process flow

described here, some of which are described in Chapter
p
2
in the text. e.g. see the STI section in the text.


CMOS Digital Gates

In the simplest CMOS technologies, we need to
realize simply NMOS and PMOS transistors for
circuits like those illustrated below.
+V
+V
IN1
PMOS
IN2
OUTPUT
OUTPUT
INPUT
NMOS
GND
GND
Inverter
2-input NOR
3

2-Level Metal CMOS

D
Sub
Sub
PMOS and NMOS

wafer cross
section after
fabrication
P+
N+
P+
N Well - PMOS Substrate
N+
P Well - NMOS Substrate
PMOS
NMOS
4

Processing Phases

Choosing a Substrate
Active Region
g
N and P Well
Gate
Tip or Extension
Source and Drain
C t t and
Contact
d Local
L
l IInterconnect
t
t
Multilevel Metalization

Choosing a Substrate
1 m
Photoresist
80 nm
40 nm
Si, (100), P Type, 5-50 cm
Substrate selection:
moderately high resistivity
(25-50 ohm-cm)
(100) orientation
P- type.

Si3N4
SiO2
Choose the substrate

(type, orientation,
resistivity, wafer size)
Initial processing:
Wafer cleaning
thermal oxidation, H2O
( 40 nm, 15 min. @ 900C)
nitride LPCVD deposition
( 80 nm)
1st Mask Photoresist
spinning and baking
( 0.5 - 1.0 m)
6

Active Area Definition

Ph
Photolithography
t lith
h
Mask #1 pattern alignment
and UV exposure
y non-pattern
p
PR
Rinse away
Dry etch the Nitride layer
Plasma etch with Fluorine
CF4 or NF4 Plasma
P
Strip Photoresist


Field Oxide Growth

W
Wett Oxide
O id (thick
(thi k SiO2)
H2O ( 500 nm, 45 min. @
1000C)
LOCOS: Local Oxidation of
Silicon
Birds beak surface feature
Strip Nitride layer

Phosophoric acid or
plasma etch
Instead of Si3N4 use

SiO2/PolySi/Si3N4=
Poly Buffered LOCOS
Results in less birds beak

P-well Fabrication
Photolithography
and UV exposure
Rinse away non-pattern PR
Boron
Ion Implantation
B+ ion bombardment
Penetrate thin SiO2 and field
SiO2
150-200 KeV for 1013 cm-2
Implantation Energy and
total dose adjusted for
depth and concentration
P Implant
PMOS
NMOS
P
Strip Photoresist


N-well Fabrication
Photolithography
and UV exposure
Phosphorus
N Implant
Ion Implantation
P+ ion bombardment
Penetrate thin SiO2 and field
SiO2
300-400 KeV for 1013 cm-2
P Implant
PMOS
NMOS
P
Strip Photoresist

10

Thermal Anneal and Diffusion

Thermal Anneal
Repair crystal lattice structure
d
damage
due
d to
t implantation
i l t ti
N Well
N and P Drive-in
Thermal
e a d
diffusion
us o o
of dopa
dopantt to
shallower than desired depth
Drive-in is a cumulative
process!
P Well
2-3 m deep
PMOS
NMOS
Dry Furnace (N2 ambient)

Anneal
30 min @ 800C or
RTA 10 sec @ 1000C
Drive-in
4-6 hours @ 1000 C - 1100 C

11

Threshold Adjustment, P-type NMOS

Photolithography
and UV exposure
Boron
Ion Implantation
B+ ion bombardment
50-75KeV for 1-5 x 1012 cm-2
N Well
P Well
PMOS
NMOS
P
Strip Photoresist

12

Threshold Adjustment, N-type PMOS

Photolithography
and UV exposure
Arsenic
N Well
P Well
PMOS
Ion Implantation
As+ ion bombardment
75-100 KeV for 1-5 x 1012 cm-2
NMOS
P

Strip Photoresist
13

Gate Oxide Growth
Remove existing gate region

oxide
HF etch
N Well
Furnace Steps
Thermal Anneal
30 min @ 800C
800 C
Oxide growth 3-5 nm
O2 ambient
0.5-1 hour @ 800C
P Well
PMOS
NMOS
P

14

Polysilicon Gate Deposition

LPCVD Deposition of Si
Silane
P
N Well
Amorphous or polycrystalline
silicon layer results
0.3-0.5 um
P Well
PMOS
IIon Implantation
I l t ti
P+ or As+ (N+) implant dopes
the poly
((typically
yp
y 5 x 1015 cm-2)
NMOS
P

15

Gate Patterning
N Well
P Well
PMOS
Ph
Photolithography
t lith
h
and UV exposure
y non-pattern
p
PR
Rinse away
Plasma Etch
Anisotropic etch
Vertical etch rate high
Lateral etch rate low
Clorine or Bromine based for
SiO2 selectivity
NMOS
P

16

Extension (LDD) Formation NMOS
Phosphorus
Photolithography
and UV exposure
N - Implant
N Well
P Well
PMOS
Ion Implantation
P+ ion
i
bombardment
b b d
t
50 KeV for 5 x 1013 cm-2
NMOS
P
Strip
p Photoresist
LDD:
Lightly Doped Drain
Reduce short channel effects due to gate voltage
magnitudes and electric fields
Source and Drain must be layered as
NMOS:N+N-P or PMOS: P+P-N
17

Extension (LDD) Formation PMOS
Photolithography
and UV exposure
Boron
P - Implant
N - Implant
N Well
P Well
PMOS
Ion Implantation
B+ iion bombardment
b b d
t
50 KeV for 5 x 1013 cm-2
NMOS
P
Strip
p Photoresist

18

SiO2 Spacer Deposition

CVD or LPCVD Deposition of
SiO2
Silane and Oxygen
N
P- Implant
N- Implant
N Well
P Well
PMOS
Or
0.5 um
P
Provides
id spacing
i between
b t
gate
t
and source-drain.
Reduce field at gate edge
NMOS
P

19

Anisotropic Spacer Etch
P- Implant
N- Implant
N Well
P Well
PMOS
Ph
Photolithography
t lith
h
Mask #6 oversized pattern
alignment and UV exposure
y non-pattern
p
PR
Rinse away
Plasma Etch
Anisotropic etch
Vertical etch rate high
Lateral etch rate low
Flourine based
NMOS
Strip Photoresist

20

NMOS Source and Drain Implant

Screen Oxide Growth
Thin SiO2 layer ~10 nm to
scatter the implanted ions
Reduce channeling
Arsenic
Photolithography
and UV exposure
P
N + Implant
N Well
PMOS
P Well
Ion Implantation
As+
A iion b
bombardment
b d
t
75 KeV for 2-4 x 1015cm-2
NMOS
Strip
p Photoresist
21

PMOS Source and Drain Implant

Photolithography
and UV exposure
Boron
P + Implant
N + Implant
N Well
P Well
PMOS
Ion Implantation
B+ ion bombardment
1 cm-2
2
5-10 KeV for 1-3 x 1015
NMOS
Strip Photoresist

22

Thermal Annealing
Thermal Anneal
Repair crystal lattice structure
d
damage
due
d to
t implantation
i l t ti
P+
N+
P+
NW
Well
ll
N+
N+ and P+ Drive-in
Thermal
e a d
diffusion
us o of
o dopa
dopantt to
shallower than desired depth
Drive-in is a cumulative
process!
P Well
W ll
PMOS
NMOS

Anneal
30 min @ 900C or
RTA 60 sec @ 1000 C - 1050 C
Transient Enhanced Diffusion (TED)

Higher than normal diffusivity due to
crystal damage

23

Contact Openings
P+
P+
N+
N Well
P Well
PMOS
NMOS
N+
HF etch to remove thin SiO2

Remove screen oxide from
drain, source and ploy gate
regions
Dip for a few seconds
LDD and Sidewall structure

NMOS: Lateral N+ N- P N- N+
PMOS: Lateral P+ P- N P- P+

24

Contacts and Interconnects
Titanium sputtering local contacts

Conformal Coat with SiO2
Planarization
Tungsten Plug vias
Aluminum Metal Deposition
Repeat

Coatt
C
Planarize
Plug
Metal deposition
25

Titanium Deposition
P+
P+
N+
N Well
N+
P Well
PMOS
NMOS
Ti is deposited by
sputtering
(typically 100 nm).
Ti target hit with
Ar+ ions in a
vacuum chamber
h b
P+
P+
N+
NW
Well
ll
N+
P Well
W ll
PMOS
NMOS
P

26
Th
The Ti is
i reacted
d in
i an
N2 ambient,
Forms TiSi2 and TiN
(typically 1 min @ 600 700 C).
TiSi2 has excellent
contact characteristics
TiN does
d
not,
t but
b t can
be used for local wiring
Local TiN Interconnect
P+
P+
N+
N Well
P Well
PMOS
NMOS
Photolithography
and UV exposure
N+
TiN etch
NH4OH:H202:H20 (1:1:5)
Strip Photoresist
Thermal Treat in Ar
1 min @ 800 C

27

Conformal Coat and Planarize

P+
P+
N+
N Well
N+
P Well
PMOS
NMOS
Conformal layer of
SiO2 is deposited by
CVD or LPCVD
(typically 1 m)
PSG or BPSG
Surface passivation
Glass reflow
reflo for
partial planarization
P+
P+
N+
N Well
N+
P Well
PMOS
Chemical Mechanical
Polishing (CMP)
Planarize the wafer
surface
Polish with high pH
silica slurry
NMOS
P

28

Vias to 1st Metal
P+
P+
N+
N Well
PMOS

Photolithography
and UV exposure
N+
SiO2 plasma etch

Anisotropic
A i t
i etch
t h
P Well
Strip Photoresist
NMOS
29

Via Deposition Tungsten Plugs

TiN
P+
P+
N+
N Well
TiN or Ti/TiN barrier layer

Sputtering or CVD
(few tens of nm)
N+
P Well
CVD Tungsten (W)
PMOS
P+
NMOS
P+
N+
N Well
Chemical Mechanical
Polishing (CMP)
Planarize the wafer
surface
Polish with high pH
silica slurry
N+
P Well
PMOS
NMOS
P

30

Damascene Process
Etch Contact Holes or Line Trenches
Fill etched regions
g
Planarize
CMP process
Also
Al removes material
t i l th
thatt overflowed
fl
dh
holes
l or ttrenches
h
Also used in reference to copper line metal layer

deposition

31

Metal #1 Deposition
Photolithography
g p y
and UV exposure
P+
P+
N+
N Well
Sputtered Aluminum
Al with small amounts of
Si and Cu
Cu reduces electromigration
N+
P Well
PMOS
NMOS
Anisotropic plasma etch
Strip Photoresist

32

Multiple Metal Layers
P+
P+
N+
N Well
N+
Final passivation layer of

Si3N4 is deposited by
PECVD and patterned with
Mask #16.
P Well
PMOS
Deposits Oxide Layer

CMP
Ph t lith
Photolithography
h M
Mask
k #14
Etch Vias
Deposit via material
CMP
C
Photolithography Mask #15
Deposit Next Metal Layer
NMOS
P
Final anneal and alloy in

forming gas (10% H2 in N2)
30 min @ 400
400-450
450 C
C
33

Intel processor chip
52MB SRAM chips on a 12 wafer
Photos of state-of-the-art CMOS chips (from Intel website).

90 nm technology.


Summary of Key ideas

This chapter serves as an introduction to CMOS technology.
It provides a perspective on how individual technologies like oxidation and
ion implantation are actually used.
There are many variations on CMOS process flows used in industry.
The process described here is intended to be representative, although it is
simplified compared to many current process flows.
Some process options are described in Chapter 2 in the text.
Perhaps the most important point is that while individual process steps like
oxidation and ion implantation are usually studied as isolated technologies,
technologies
their actual use is complicated by the fact that IC manufacturing consists of
many sequential steps, each of which must integrate together to make the
whole process flow work in manufacturing.
35


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CMOS Technology- Chapter 2

Silicon VLSI Technology

SILICON VLSI TECHNOLOGY

2000 by Prentice Hall

CMOS Technology- Chapter 2

We will describe a modern CMOS process flow.

Typical CMOS technologies in manufacturing today add

Process described here requires 16 masks

There are many possible variations on the process flow

SILICON VLSI TECHNOLOGY

2000 by Prentice Hall

CMOS Technology- Chapter 2

CMOS Digital Gates

2000 by Prentice Hall

CMOS Technology- Chapter 2

2-Level Metal CMOS

PMOS and NMOS

N Well - PMOS Substrate

P Well - NMOS Substrate

2000 by Prentice Hall

CMOS Technology- Chapter 2

SILICON VLSI TECHNOLOGY

2000 by Prentice Hall

CMOS Technology- Chapter 2

Si, (100), P Type, 5-50 cm

SILICON VLSI TECHNOLOGY

Choose the substrate

2000 by Prentice Hall

CMOS Technology- Chapter 2

Active Area Definition

SILICON VLSI TECHNOLOGY

2000 by Prentice Hall

CMOS Technology- Chapter 2

Field Oxide Growth

Birds beak surface feature

Strip Nitride layer

Instead of Si3N4 use

2000 by Prentice Hall

CMOS Technology- Chapter 2

SILICON VLSI TECHNOLOGY

2000 by Prentice Hall

CMOS Technology- Chapter 2

SILICON VLSI TECHNOLOGY

2000 by Prentice Hall

CMOS Technology- Chapter 2

Thermal Anneal and Diffusion

Dry Furnace (N2 ambient)

SILICON VLSI TECHNOLOGY

2000 by Prentice Hall

CMOS Technology- Chapter 2

Threshold Adjustment, P-type NMOS

SILICON VLSI TECHNOLOGY

2000 by Prentice Hall

CMOS Technology- Chapter 2

Threshold Adjustment, N-type PMOS

SILICON VLSI TECHNOLOGY

2000 by Prentice Hall

CMOS Technology- Chapter 2

Gate Oxide Growth

Remove existing gate region

SILICON VLSI TECHNOLOGY

2000 by Prentice Hall

CMOS Technology- Chapter 2