Professional Documents
Culture Documents
Documentsdkfgk
Documentsdkfgk
10
Journal of Semiconductors
October 2014
Abstract: A continuous-time modulator with a third-order loop filter and a 3-bit quantizer is realized. The
modulator is robust to the excess loop delay, clock jitter, and RC product variations. When designing the integrator,
an op-amp with novel GBW extension structure, improving the linearity of the loop filter, is adopted. The prototype
chip is designed in a 130 nm CMOS technology, targeting FM radio applications. The experimental results show
that the prototype modulator achieves a 72 dB dynamic range and a 70.7 dB signal to noise and distortion ratio over
a 500 kHz bandwidth with a 26 MHz clock, consuming 2.52 mW power from a 1.2 V supply.
Key words: continuous-time sigmadelta modulator; FM radio; oversampling A/D converters
DOI: 10.1088/1674-4926/35/10/105004
EEACC: 2220
1. Introduction
It may be surprising that today an almost ancient standard
such as FM is still featured in one of the most used consumer
products, the in-car radio, which is driving research on innovative and state-of-the-art A/D converters1 4 . Without a doubt,
in-car FM radio can be considered a true high-end system due
to the vast dynamic range differences between FM channels.
The full antenna input dynamic range (for FM) is in the order
of 140 dB, exceeding the requirements of, for example, super
audio CD. However, there is no receiver on the market today
that handles that dynamic range without desensitization or using external high-Q filters. Hence, any increase in the dynamic
range of the A/D converter results in a higher quality radio with
better sensitivity and a lower cost system, which is the aim of
every car radio set maker.
Figure 1 presents the conventional direct conversion radio architecture in a modern FM radio receiver. An RF LNA,
which is controlled by an automatic gain control loop (AGC),
processes the received FM signal band (76108 MHz). Then,
a quadrature mixer down-converts the RF signal to baseband.
The mixer pair is controlled by quadrature local oscillator (LO)
signals that have 90 degrees phase difference. After the downconversion, the base band signal is adjusted by a programmable
gain amplifier (PGA) and it is then digitized by a modulator. The modulator is followed by digital comb filters, which
perform most of the required channel filtering prior to the DSP.
The anti-alias filtering and A/D conversion functions can be
combined by using a continuous-time (CT) modulator.
This is helpful to reduce the system cost. In our system, each
modulator has an input sample rate of 26 MHz, which is
the clock rate of the whole system, and should achieve at least
65 dB of dynamic range over the FM bandwidth of 200 kHz.
In the future, this modulator will be shared by a Bluetooth receiver with a similar architecture, thus the bandwidth should
be extended to 500 kHz to accommodate Bluetooth signals.
As mentioned above, a modulator is one of the core
blocks in the tuner and it will have an important impact on the
2. System architecture
2.1. CT modulator architecture
The loop filter design of a CT A/D modulator is nontrivial in that it has a strong dependence on the pulse of the feedback DAC. Because discrete time (DT) modulator loop filters
can be easily designed, the most common method to design a
CT modulator loop filter is to first find the equivalent DT modulator loop filter and then transform it to continuous-time using
105004-1
H.s/ D Kfb2 Ks .sT /2 C Kfb1 K1 Ks Kff sT
C Kfb1 K1 K2 Ks .sT /2 C Kfb K2 Ks sT
: (2)
(3)
(4)
H.Z/ D
H.S / D
105004-2
105004-3
over 70 dB, the clock jitter should be kept below 15 ps. The
typical jitter performance of the 26 MHz crystal oscillator is
less than 10 ps. This leaves enough margin for the SNDR to
be larger than 70 dB. In addition, the quantizer delay should
be lower than 10.6 ns for stable operation of the modulator.
The typical delay of the quantizer that is comprised of a preamplifier and a high speed latch is only 1 ns (see Section 3.2).
This also confirms the SNDR to be larger than 70 dB.
2.4. Noise consideration
The device noise at the modulator front-end is not attenuated and, thus, it is a limiting factor in the total input referred
noise of the modulator. There are three sources for the noise of
the front-end:
(1) Noise of the two input resistors;
(2) Noise of the op-amp;
(3) Noise of the current steering DAC1 feedback to the
virtual grounds of the op-amp.
The following integrator contributes little noise due to the
high gain of the preceding stage. In our design, the dominant
noise source is the noise from two input resistors. The choice
of the input resistor value is a trade off process between chip
area and noise. For a given time constant, a larger resistor has
a smaller capacitor area but larger noise. The resistor value
should be fixed during the architecture design stage. The total in-band noise power of the two input resistor is expressed
by:
VR2in D 8kTRin f;
(5)
where k represents the Boltzmann constant, T represents absolute temperature, and f is the signal bandwidth, which equals
500 kHz. In our design, the value of the input resistor is chosen
to be 6 k, generating a thermal noise power that is 98.6 dB
lower than the full scale input signal. The input resistor of the
following integration stage could be scaled up to minimize the
capacitor area. The simulation shows that the resistors of the
following stage can be scaled up to less than 3 compared to
the former stage in order to make little in-band noise contribution. Thus, in our design, the R2 and R3 are chosen to be 16 k
and 36 k, respectively.
105004-4
Fig. 7. (a) Op-amp schematic and (b) its differential mode small signal equivalent circuit.
is started. This latch has a very small regenerative time constant and amplifies the voltage difference to full logic levels.
Simulation shows that the quantizer delay is only 1ns, which is
much smaller than the upper limit of the value that will cause
instability of the modulator (see Section 2.3).
3.3. Feedback DACs
Since the loop filter implements one feed-forward path,
only two DACs would be necessary to realize the differentiated return-zero (RZ) feedback. DAC1 realizes an input to the
loop filter and, hence, has the highest requirements on linearity and noise performance, which requires a large device size
to get the necessary matching and flicker noise performance.
DAC2 realizes the second feedback. As any non-idealities of
DAC2 are suppressed by the gain of the first two integrators,
the requirements on noise and linearity can be relaxed. For both
105004-5
Fig. 10. Schematic of (a) the pre-amp and (b) the latch in the comparator.
4. Experimental results
The proposed modulator is fabricated in a TSMC 130 nm
CMOS process and it occupies an area of 0.66 mm2 . Figure 16
gives a die photograph of this modulator.
105004-6
Fig. 11. Schematic of (a) the DAC and (b) the low swing buffer.
Fig. 12. Transient simulation results of flash ADC and feedback DAC.
5. Conclusion
Fig. 13. Illustration of DWA.
In this paper, a continuous-time modulator that is fabricated in a 130 nm CMOS technology is proposed for the application FM/Bluetooth tuner. The proposed modulator consumes 2.1 mA current from a 1.2 V supply and occupies an
area of 0.66 mm2 . Table 2 gives performance summary of this
work and a comparison with other related works11 14 .
Acknowledgments
The author would like to thank Yang Zhengxiu, Liu Cong,
Yin Jinlin and Li Canyang for their help in layout and testing.
References
[1] Breems L J, van der Zwan E J, Dijkmans E C, et al. A 1.8 mW
105004-7
Parameter
Supply voltage (V)
Technology
Fs (MHz)
BW (MHz)
SNDR (dB)
DR (dB)
Power (mW)
Chip area (mm2 /
FoM* (pJ/conv.)
1:73/=6:02 /.
This work
1.2
130 nm CMOS
26
0.5
70.7
72
2.52
0.66
0.89
Fig. 17. Measured output spectrum of the modulator with 75.8 kHz
and 4 dBFS input signal.
CMOS sigma delta modulator with integrated mixer for A/D conversion of IF signals. IEEE J Solid-State Circuits, 2000, 35(4):
468
[2] Van der Zwan E J, Philips K, Bastiaansen C A A. A 10.7-MHz
IF-to-baseband sigma delta A/D conversion system for AM/FM
radio receivers. IEEE J Solid-State Circuits, 2000, 35(12): 1810
[3] Silva P, Breems L J, Makinwa K, et al. A 118 dB DR CT IFto-baseband modulator for AM/FM/IBOC radio receivers.
IEEE ISSCC Dig Tech Papers, 2006: 66
[4] Breems L J, Rutten R, van Veldhoven R, et al. A 56 mW CT
quadrature cascaded sigma delta modulator with 77 dB DR in a
near zero-IF 20 MHz band. IEEE ISSCC Dig Tech Papers, 2007:
238
105004-8
4 dBFS input
[5] Paton S, Giandomenico A D, Hernandez L, et al. A 70-mW 300MHz CMOS continuous-time sigma delta ADC with 15-MHz
bandwidth and 11 bits of resolution. IEEE J Solid-State Circuits,
2004, 39(7): 1056
[6] Mitteregger G, Ebner C, Mechnig S, et al. A 20-mW 640-MHz
CMOS continuous-time sigmadelta ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB. IEEE
J Solid-State Circuits, 2006, 41(12): 2641
[7] Schoofs R, Steyaert M S J, Sanse W M C. A design-optimized
continuous-time deltasigma ADC for WLAN applications.
IEEE Trans Circuits Syst I, 2007, 54(1): 209
[8] Li Z M, Fiez T S. A 14 bit continuous-time deltasigma A/D
modulator with 2.5 MHz signal bandwidth. IEEE J Solid-State
Circuits, 2007, 42(9): 1873
[9] Yan S L, Sanchez-Sinencio E. A continuous-time modulator
with 88-dB dynamic range and 1.1-MHz signal bandwidth. IEEE
105004-9