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Basic Concept of HDL
Basic Concept of HDL
Basic Concept of HDL
ACCESS IC LAB
Outline
Hierarchical Design Methodology
Basic Concept of Verilog HDL
Switch Level Modeling
Gate Level Modeling
Simulation & Verification Tools
Huai-Yi Hsu
pp. 2
Structural
Gate (AND, OR )
Switch (PMOS, NOMS, JFET )
Huai-Yi Hsu
pp. 3
Huai-Yi Hsu
pp. 4
sub
block 1
leaf
cell
leaf
cell
sub
block 2
leaf
cell
leaf
cell
sub
block 3
leaf
cell
Huai-Yi Hsu
sub
block 4
leaf
cell
leaf
cell
leaf
cell
pp. 5
macro
cell 1
leaf
cell
leaf
cell
macro
cell 2
leaf
cell
leaf
cell
macro
cell 3
leaf
cell
Huai-Yi Hsu
macro
cell 4
leaf
cell
leaf
cell
leaf
cell
pp. 6
M2
M3
Add_rca_4
Add_rca_4
Add_rca_4
Add_rca_4
M1
M2
M3
M4
Add_full
xor
nand
Add_full
M4
Add_full
Add_full
M1
M2
M3
M4
Add_half
Add_half
norf201
invf101
not
xor
nand
not
[HW]
Basic Concept 2004.03.05
Huai-Yi Hsu
pp. 7
Design Encapsulation
Encapsulate structural and functional details in a
module
module <Module Name> (<PortName List>);
// Structural part
<List of Ports>
<Lists of Nets and Registers>
<SubModule List> <SubModule Connections>
// Behavior part
<Timing Control Statements>
<Parameter/Value Assignments>
<Stimuli>
<System Task>
endmodule
Huai-Yi Hsu
pp. 8
Instances
A module provides a template from which you can
create actual objects.
When a module is invoked, Verilog creates a unique
object from the template.
Each object has its own name, variables, parameters
and I/O interface.
Huai-Yi Hsu
pp. 9
(a b) c_in
sum
a
Add_half_0_delay
sum w1
a
b
Add_half_0_delay
(ab)
b
c_out
w2
ab
c_out
sum
c_out
(a + b) c_in + ab
MODELING TIP
MODELING TIP
w3
(a b) c_in
Huai-Yi Hsu
pp. 10
Multi-line comments:
/* Do not /* nest multi-line comments*/ like this */
Huai-Yi Hsu
pp. 11
Language Conventions
Case-sensitivity
Verilog is case-sensitive.
Some simulators are case-insensitive
Advice: - Dont use case-sensitive feature!
Keywords are lower case
Huai-Yi Hsu
pp. 12
Huai-Yi Hsu
pp. 13
Huai-Yi Hsu
pp. 14
Port Declaration
Three port types
Input port
input a;
Output port
output b;
Bi-direction port
module
inout c;
input
output
reg or net
inout
net
net
net
Huai-Yi Hsu
pp. 15
Data Types
nets are further divided into several net types
wire, wand, wor, tri, triand, trior, supply0, supply1
Huai-Yi Hsu
pp. 16
real delta;
initial delta = 4e10;
time sim_time;
initial sim_time = $time;
Huai-Yi Hsu
pp. 17
Data Types
Nets ( wire or reg (in combinational always block)
Connects between structural elements
Must be continuously driven by
Continuous assignment (assign)
Module or gate instantiation (output ports)
Huai-Yi Hsu
pp. 18
Net Types
The most common and important net types
wire and tri
for standard interconnection wires
trireg
for net with capacitive storage
If all drivers at z, previous value is retained
Huai-Yi Hsu
pp. 19
Register Types
reg
any size, unsigned
Huai-Yi Hsu
pp. 20
Huai-Yi Hsu
pp. 21
Huai-Yi Hsu
pp. 22
Wired Logic
The family of nets includes the types wand and wor
A wand net type resolves multiple driver as wired-and logic
A wor net type resolves multiple drivers as wired-or logic
Huai-Yi Hsu
pp. 23
a;
b;
[3:0]
c;
[7:0]
bus;
[1:4]
d;
(small) store;
// scalar register
// scalar net of type wand
// 4-bit register
// tri-state 8-bit bus
// 4-bit
// specify logical strength (rare used)
a
c
b
wand/triand
wor/trior
Huai-Yi Hsu
pp. 24
Vector
wire and reg can be defined vector, default is 1bit
vector is multi-bits element
Format: [High#:Low#] or [Low#:High#]
Using range specify part signals
wire
a;
wire [7:0] bus;
reg
clock;
reg [0:23] addr;
bus[7]
// bit #7 of vector bus
bus[2:0] // Three least significant bits of vector bus
// using bus[0:2] is illegal because the significant bit should
// always be on the left of a range specification
addr[0:1] // Two most significant bits of vector addr
Huai-Yi Hsu
pp. 25
Array
Arrays are allowed in Verilog for reg, integer, time,
and vector register data types.
Multidimensional array are not permitted in Verilog.
integer
reg
time
reg [4:0]
integer
count[0:7];
bool[31:0];
chk_ptr[1:100];
port_id[0:7];
matrix[4:0][4:0]
count[5]
chk_ptr[100]
port_id[3]
Huai-Yi Hsu
pp. 26
Memories
In digital simulation, one often needs to model register files,
RAMs, and ROMs.
Memories are modeled in Verilog simply as an array of registers.
Each element of the array is known as a word, each word can
be one or more bits.
It is important to differentiate between
n 1-bit registers
One n-bit register
reg mem1bit[0:1023];
// Memory mem1bit with 1K 1-bit words
reg [7:0] mem1byte[0:1023]; // Memory mem1byte with 1K 8-bit words
mem1bit[255]
Mem1byte[511]
Huai-Yi Hsu
pp. 27
Strings
String: a sequence of 8-bits ASCII values
module string;
reg [8*14:1] strvar;
initial
begin
strvar = Hello World;
strvar = Hello World!!;
end
endmodule
// stored as 000000486561726c64
// stored as 00486561726c642121
Special characters
\n newline
\\ \ character
%% % character
\t tab character
\ character
\abc ASCII code
Huai-Yi Hsu
pp. 28
Four-valued Logic
Verilogs nets and registers hold four-valued data
0 represent a logic zero or false condition
1 represent a logic zero or false condition
z
Output of an undriven tri-state driver
high-impedance value
Models case where nothing is setting a wires value
x
Models when the simulator cant decide the value uninitialized
or unknown logic value
Initial state of registers
When a wire is being driven to 0 and 1 simultaneously
Output of a gate with z inputs
Huai-Yi Hsu
pp. 29
Logic System
Four values: 0, 1, x or X, z or Z
a
b
a
b
y
Huai-Yi Hsu
x z
x z
x z
x z
pp. 30
Huai-Yi Hsu
pp. 31
Syntax
<NetType> <Strength> <Range>
trireg
(large)
[1:4]
<Delay>
#5
<Variables>;
c1;
Strength level
weakest
strongest
Huai-Yi Hsu
pp. 32
Number Representation
Format: <size><base_format><number>
<size> - decimal specification of number of bits
default is unsized and machine-dependent but at least 32 bits
Huai-Yi Hsu
pp. 33
Number Representation
Examples:
6b010_111
8b0110
4bx01
16H3AB
24
5O36
16Hx
8hz
gives 010111
gives 00000110
gives xx01
gives 0000001110101011
gives 00011000
gives 11100
gives xxxxxxxxxxxxxxxx
gives zzzzzzzz
Huai-Yi Hsu
pp. 34
Net Concatenations
A easy way to group nets
Representation
Meanings
{cout, sum}
{cout, sum}
{b[7:4],c[3:0]}
{a,b[3:1],c,2b10}
{4{2b01}}
8b01010101
{{8{byte[7]}},byte}
Sign extension
Huai-Yi Hsu
pp. 35
Parameter Declaration
Parameters are not variables, they are constants.
Typically parameters are used to specify delays and
width of variables
Examples
Huai-Yi Hsu
pp. 36
endmodule
Huai-Yi Hsu
pp. 37
module top;
endmodule
Huai-Yi Hsu
module annotate;
defparam
top.U0.width = 2;
top.U0.delay = 1;
top.U1.width = 4;
top.U1.delay = 2;
top.U2.width = 3;
top.U2.delay = 1;
endmodule
pp. 38
Conventional modules
Behavior statements
Structural statements
Switch Level Modeling (using transistors)
Delay Specification
Specify gate delay
Specify module path delay
Huai-Yi Hsu
pp. 39
Resistive
gates
and
buf
nmos
rnmos
pullup
nand
not
pmos
rpmos
pulldown
or
bufif0
cmos
rcmos
nor
bufif1
tran
rtran
xor
notif0
tranif0 rtranif0
xnor
notif1
tranif1 rtranif1
Huai-Yi Hsu
pp. 40
MOS Switches
Two types of MOS switches can be defined with the keywords, nmos
and pmos
nmos is used to model NMOS transistors
nmos n1(out, data, control);
out
data
out
data
control
control
NMOS transistor
PMOS transistor
Huai-Yi Hsu
H: stands for 1 or z
L: stands for 0 or z
pp. 41
CMOS Switches
CMOS switches are declared with the keyword cmos.
A cmos device can be modeled with a nmos and a
pmos device.
cmos c1(out, data, ncontrol, pcontrol);
pcontrol
out
data
ncontrol
CMOS
Huai-Yi Hsu
pp. 42
Bidirectional Switches
NMOS, PMOS, CMOS gates conduct from drain to source.
It is important to have devices that conduct in both directions.
In such cases, signals on either side of the device can be the
driver signal.
Bidirectional switches are typically used to provide isolation
between buses or signals.
tran
tranif0
tranif1
t1(inout1, inout2);
t2(inout1, inout2, control);
t3(inout1, inout2, control);
control
inout1
inout2
tran
Basic Concept 2004.03.05
inout1
control
inout2
tranif1
Huai-Yi Hsu
inout1
inout2
tranif0
pp. 43
supply1
supply0
vdd;
gnd;
assign a = vdd;
assign b = gnd;
// connect a to vdd
// connect b to gnd
Huai-Yi Hsu
pp. 44
Resistive Switches
Resistive switches have the same syntax as regular switches.
Resistive devices have a high source-to-drain impedance. Regular
switches have a low source-to-drain impedance.
Resistive switches reduce signal strengths when signals pass through.
Regular switches retain strength levels of signals from input to output.
Input Strength
Output Strength
Supply
Pull
Strong
Pull
Pull
Weak
Weak
Medium
Large
Medium
Medium
Small
Small
Small
High
High
Huai-Yi Hsu
pp. 45
Switches Example
a
out
pwr
out;
a, b;
// internal wires
wire c;
out
gnd
endmodule
Huai-Yi Hsu
pp. 46
Huai-Yi Hsu
pp. 47
Huai-Yi Hsu
pp. 48
Example UDP
select
Huai-Yi Hsu
pp. 49
Alternative model
table
// Shorthand notation:
// ? represents iteration of the table entry over the values 0,1,x.
// i.e., don't care on the input
select
0
0
0
1
?
?
:
:
0;
1;
1
1
?
?
0
1
:
:
0;
1;
?
0
?
1
endtable
0
1
:
:
0;
1;
mux_out
Huai-Yi Hsu
// ? = 0, 1, x shorthand notation.
pp. 50
MODELING TIP
The output of a sequential user-defined primitive must be
declared to have type reg.
Huai-Yi Hsu
pp. 51
enable data
1
1
1
0
0
?
:
:
:
state
?
?
?
q_out/next_state
:
1;
:
0;
:
- ;
0
1
:
:
0
1
:
:
-;
-;
Huai-Yi Hsu
pp. 52
data
q_out
d_prim1
clock
? :
- ;
?
(??) :
endtable
endprimitive
- ;
Huai-Yi Hsu
pp. 53
preset
q_out
j
k
clk
clear
J-K functionality:
- preset and clear override clock
- no change if j=0, k=0
- drive to 1 if j=1, k=0
- drive to 0 if j=0, k=1
- toggle if j=1, k=1
Huai-Yi Hsu
pp. 54
clr
1
1
state q_out/next_state
:
:
0
*
:
:
clr
0
1
1
1
1
1
?
:
:
:
:
:
:
?
1
:
:
1;
1;
?
0
:
:
0;
0;
state q_out/next_state
0
:
?
:
?
:
?
:
0
:
1
:
?
:
1;
- ;
0;
1;
1;
0;
-;
clr
?
?
:
:
state q_out/next_state
?
:
?
:
-;
-;
1
?
1
?
1
?
1
1
?
:
:
:
:
:
:
:
:
:
?
0
1
?
?
0
1
1
0
:
:
:
:
:
:
:
:
:
-;
-;
-;
-;
-;
-;
-;
-;
-;
pp. 55
ACCESS IC LAB
Huai-Yi Hsu
pp. 57
Huai-Yi Hsu
pp. 58
Huai-Yi Hsu
pp. 59
Huai-Yi Hsu
pp. 60
a
b
#5
e
#4
c
d
#7
out
Huai-Yi Hsu
pp. 61
a
b
e
#11
out
and
a1(e, a, b);
and
a2(f, c, d);
and #11 a3(out, e, f);
endmodule
Huai-Yi Hsu
pp. 62
a
b
out
c
Huai-Yi Hsu
pp. 63
Huai-Yi Hsu
pp. 64
Parallel/Full Connection
(a => out) = 9;
(b => out) = 9;
(c => out) = 11;
(d => out) = 11;
(a => out) = 9;
Huai-Yi Hsu
pp. 65
Specparam Statement
Special parameters can be declared for use inside a
specify block.
Instead of using hardcoded delay numbers to specify
pin-tp-pin delays
module and4(out, a, b, c, d);
endmodule
Basic Concept 2004.03.05
Huai-Yi Hsu
pp. 66
Huai-Yi Hsu
pp. 67
Huai-Yi Hsu
pp. 68
Timing Checks
setup and hold checks
clock
data
setup
time
hold
time
specify
$setup(data, posedge clock, 3);
endspecify
specify
$hold(posedge clock, data, 5);
endspecify
Huai-Yi Hsu
pp. 69
Timing Checks
Width check
clock
width of
the pulse
specify
$width(posedge clock, 6);
endspecify
Huai-Yi Hsu
pp. 70
Structural Models
Verilog primitives encapsulate pre-defined functionality of common logic gates
The counterpart of a schematic is a structural model composed of Verilog
primitives
Model structural detail by instantiating and connecting primitives
module name
primary
inputs
primary
output
AOI_str
x_in1
y1
x_in2
x_in3
x_in4
x_in5
module ports
y_out
y2
Huai-Yi Hsu
pp. 71
Structural Connectivity
Wires in Verilog establish connectivity between primitives and/or
modules
Data type: nets (Example: wire)
The logic value of a wire (net) is determined dynamically during
simulation by what is connected to the wire.
An undeclared identifier is treated by default as a wire
Use nets to establish structural connectivity
Port connection by name
Add_half_0_delay M1(.b(b),.c_out(w2),.a(a),.sum(w1));
Huai-Yi Hsu
pp. 72
ACCESS IC LAB
Test Methodology
Task: systematically verify the functionality of a model.
Approaches: Simulation and/or formal verification
Simulation:
(1) detect syntax violations in source code
(2) simulate behavior
(3) monitor results
Design_Unit_Test_Bench (DUTB)
Stimulus
Generator
Unit_Under_Test (UUT)
D
SET
CLR
Response
Monitor
Huai-Yi Hsu
pp. 74
Components of a Simulation
Stimulus Block
Input
Patterns
Design Block
Stimulus
Block
Output
Results
Output
Results
Design
Block
Huai-Yi Hsu
pp. 75
Event-Driven Simulation
A change in the value of a signal (variable) during simulation is
referred to as an event
Spice-like analog simulation is impractical for VLSI circuits
Event-driven simulators update logic values only when signals
change
Huai-Yi Hsu
pp. 76
Inertial Delay
Not scheduled
x_in1
Descheduled
=1
3
tpd = 2
tsim = 4
x_in2
=6
3
y_out1
x_in1
tpd = 2
x_in2
y_out2
5
11
Note: The falling edge of x_in1 occurs before the response to the rising edge occurs.
Huai-Yi Hsu
pp. 77
Testbench Template
Consider the following template as a guide for simple testbenches:
module t_DUTB_name (); // substitute the name of the UUT
reg ;
// Declaration of register variables for primary inputs of the UUT
wire ;
// Declaration of primary outputs of the UUT
parameter
time_out = // Provide a value
UUT_name M1_instance_name ( UUT ports go here);
initial $monitor ( );
initial
begin
// Behavioral statements generating waveforms
// to the input ports, and comments documenting
// the test. Use the full repertoire of behavioral
// constructs for loops and conditionals.
end
endmodule
Basic Concept 2004.03.05
Huai-Yi Hsu
pp. 78
Example: Testbench
module t_Add_half();
wire
sum, c_out;
reg
a, b;
// Storage containers for stimulus waveforms
Add_half_0_delay M1 (sum, c_out, a, b);
initial begin
#100 $finish;
end
initial begin
#10 a = 0; b = 0;
#10 b = 1;
#10 a = 1;
#10 b = 0;
end
endmodule
//UUT
// Time Out
// Stopwatch
// Stimulus patterns
// Statements execute in sequence
Huai-Yi Hsu
pp. 79
Huai-Yi Hsu
pp. 80
Signal Generators
MODELING TIP
Use procedural assignments to describe stimulus patterns in
a testbench.
Huai-Yi Hsu
pp. 81
Simulation Results
MODELING TIP
A Verilog simulator assigns an initial value of x to all
variables.
Huai-Yi Hsu
pp. 82
Propagation Delay
Gate propagation delay specifies the time between an input
change and the resulting output change
Transport delay describes the time-of-flight of a signal transition
Verilog uses an inertial delay model for gates and transport
delay for nets
Inertial delay suppresses short pulses (width less than the
propdelay value)
MODELING TIP
All primitives and nets have a default propagation delay of 0.
Huai-Yi Hsu
pp. 83
#1
Huai-Yi Hsu
pp. 84
Huai-Yi Hsu
pp. 85
Huai-Yi Hsu
pp. 86
System Tasks
Displaying information
$display(ID of the port is %b, port_id);
ID of the port is 00101
Monitoring information
$monitor($time, Value of signals clk = %b rst = %b, clk, rst);
0 Value of signals clk = 0 rst = 1
5 Value of signals clk = 1 rst = 1
10 Value of signals clk = 0 rst = 0
Huai-Yi Hsu
pp. 87
Compiler Directives
The `define directive is used to define text macros
`define WORD_SIZE 32
`define STOP $stop;
`define WORD_REG reg[31:0]
`timescale <reference_time_unit>/<time_precision>
`timescale 1 ns / 10 ps
`timescale 100 ns / 1ns
Huai-Yi Hsu
pp. 88
Summary
Understand switch level modeling
Understand gate level modeling
Specify timing delay
Function simulation
Timing simulation
Huai-Yi Hsu
pp. 89
Homework #1
Try to build your design by using gate-level
Check your syntax!! And record your miss errors!!
Writing your testbench to verify your design
Simulate and Verify your design
Optional:
Simulation with delay information on gate-level
Design example:
16-bits Adder, 4-bits multiplier (booth)
Counter, Clock generator (OSC)
Huai-Yi Hsu
pp. 90