EE 177 Logic Circuits and Digital Electronics (LAB)

Laboratory 5

Introduction to VHDL
Binary Adder Circuits
1

Student ID No.

NAME

2011-1001

Ian James S. Anonas

Objectives
In this lab you will design, test, and simulate a basic logic circuit using the Quartus II development software. we
will build a full adder and then use that module to build a 4-bit ripple carry adder/subtractor circuit using both
behavioral and structural VHDL coding.

Introduction
This lab is an introduction to the VHDL language (scientific). The goal of this lab is to present the two methods
in design (behavioral - structural), also we will learn the language syntax and we will stop at each word of the
program explaining what it is and things related to it since these are the first programs.
Also we will illustrate the differences between structural and behavioral modeling in VHDL. We will build a full
adder as an example. As an exercise you will be asked to design and implement a 4-bit binary adder.
Below is a schematic diagram of the complete circuit. The component make-up includes four full adders and four
XOR logic gates. The inputs are two four-bit numbers; A and B, and an add/subtract selection input; Sel. The
outputs are four-bit sum; Sum, and a carry-out output; Cout.

Figure 1. 4-Bit Binary Adder/Subtractor Schematic Diagram

1.

You can now test the program on the DE2 board by using the toggle switches located along the bottom
of the board.
SW17 is the add/subtract selector. Low is for
addition. SW0 through SW3 are the four bits of data
for A. SW10 through SW13 are the four bits of data
for B.
The output of the operation is displayed on the last four green LEDs located above the blue push buttons on
the DE2 board.
LEDR0 is the indicator for Cout.

Post Lab Questions

1.

How many rows would a truth table require for an n-input logic circuit?

2n rows
2.

What do the True and False Boolean constants represent in reality?

True represents On and false represents Off

3.

What are your favorite part of this lab, and least favorite part? Why?
My favorite part of this lab is when I started to run the simulated. That was my favorite part
because I can already see the results of my inputs sing the hardware that I just designed.

Demo and Submission

Give a demo to the lab instructor and have him sign off in your lab worksheet. The demo is due on the
day the lab is scheduled.
Submit an individual lab report at the beginning of the next lab session with the following sections
and requirements:
1. First page of this worksheet
2. The inner pages which contains:
i.
Objective
Briefly describe the objective of the experiment,
ii.
Design
Explain your design and its purpose, testing results, obstacles encountered and how you resolve
them.
iii. Result and Conclusion
Briefly discuss what you have observed and learned from the experiment, and how it relates to
digital logic circuit.
3. Post Lab Questions
Answer all questions completely
4. Complete Adder/Subtractor VHDL code
5. Last page of this worksheet with the instructors signature (from the demo)

Date Performed:

11/ 4_/ 15

Date Submitted:

11/ 4_/ 15

Objective
The objective of this lab is to design, examine, and
simulate a basic logic circuit using the Quartus II
development software. In this lab we will be able to build a
full adder and then use that module to build a 4-bit ripple
carry adder/subtractor circuit using both behavioral and
structural VHDL coding.
i.

Design
This design is made up of 2 components types, the XOR
logic gate and the full adder. There are 4 XOR logic gates
and 4 full adders. Its purpose is to add or subtract a 4 bit
from a 4 bit binary number. The obstacle that I have
encountered is when mapping its ports because one small
mistake may affect the whole result and I did resolve them
by looking again at the diagram and examining the code
again.

ii.

Result and Conclusion

I observed that for every design or an entity you make
you should take all behaviors of that design in mind
because it may also be used as a component of a larger
entity. The relation of this to the digital logic circuit is that
for every larger components there should be smaller ones
that makes the whole thing and we should be familiar of
what the smaller components will do.

-- Adder/Subtractor VHDL code

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY AdderSubtractor IS
PORT (A: IN std_logic_vector(3 DOWNTO 0);
B: IN std_logic_vector(3 DOWNTO 0);
Sel: IN std_logic;
Sum: OUT std_logic_vector(3 DOWNTO 0);
Cout: OUT std_logic);
END AdderSubtractor;
ARCHITECTURE AddSub_struct OF AdderSubtractor IS
COMPONENT Gate_XOR2 IS
PORT (x, y: IN std_logic;
f: OUT std_logic);
END COMPONENT;
COMPONENT FullAdder IS
PORT (A, B, Cin: IN std_logic;
Sum, Cout: OUT std_logic);
END COMPONENT;
SIGNAL XOR2_0_out, XOR2_1_out, XOR2_2_out, XOR2_3_out: std_logic;
SIGNAL c1, c2, c3: std_logic;
BEGIN
XOR2_0:
XOR2_1:
XOR2_2:
XOR2_3:

Gate_XOR2
Gate_XOR2
Gate_XOR2
Gate_XOR2

FullAdder_0:
FullAdder_1:
FullAdder_2:
FullAdder_3:
END AddSub_struct;

PORT
PORT
PORT
PORT

FullAdder
FullAdder
FullAdder
FullAdder

MAP(B(0),
MAP(B(1),
MAP(B(2),
MAP(B(3),
PORT
PORT
PORT
PORT

Sel,
Sel,
Sel,
Sel,

MAP(A(0),
MAP(A(1),
MAP(A(2),
MAP(A(3),

XOR2_0_out);
XOR2_1_out);
XOR2_2_out);
XOR2_3_out);
XOR2_0_out,
XOR2_1_out,
XOR2_2_out,
XOR2_3_out,

Sel, Sum(0), c1);

c1, Sum(1), c2);
c2, Sum(2), c3);
c3, Sum(3), Cout);