CS-421 Parallel Processing

Discussion-03

BE (CIS) Batch 2005-06

An Introductory Analysis of Pipelines

Consider a 5-stage instruction pipeline as shown below:
IF

ID

EX

WB

stages

A time-space diagram is used to describe the progress of instructions through the pipeline.
WB
M
EX
ID
IF

I1
1

I1
I2
2

I1 I2 I3
I1 I2 I3 I4
I1 I2 I3 I4 I5
I2 I3 I4 I5 I6
I3 I4 I5 I6 I7
3
4
5
6
7
Clock Cycles
(Pipelined Execution)

I4
I5
I6
I7
I8
8

I5
I6
I7
I8
I9
9

I6
I7
I8
I9
I10
10

Weve assumed that every stage takes one clock cycle and there are no hazards in the instruction stream.
Instruction Latency (the time it takes to complete an instruction) = 5 cycles
Instruction Throughput = 6/10 IPC = 0.6 IPC
In order to gain better appreciation of pipelined execution, we draw time-space diagram for non-pipelined
execution as shown below:
WB
M
EX
ID
IF

I2

I1
I1

I2

I1
I1
I1
1

I2
I2

I2
4
5
6
7
8
Clock Cycles
(Non-Pipelined Execution)
3

10

Instruction Latency = 5 cycles

Instruction Throughput = 2/10 IPC = 0.2 IPC
This is evident that pipelined execution improves instruction throughput. However, it doesnt improve instruction
latency. (In practice, pipelining increases instruction latency due to delay of pipeline registers as will be explained
subsequently.)
Speedup
Suppose that a k-stage instruction pipeline executes a program containing n instructions. Let be the cycle time.
Execution time on non-pipelined computer is given as
tnp = nk

----------(1)

Execution time on pipelined computer is given as

tp = (k 1 + n) ----------(2)
where, k 1 cycles are required to fill up the pipeline (also called pipeline setup time).
By definition, speedup S of pipelined execution over non-pipelined execution is given as
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CS-421 Parallel Processing

Discussion-03

BE (CIS) Batch 2005-06

S=
=

time before enhancement

time after enhancement
t np
tp

nk
(k 1 + n )
nk
=
(3)
k 1+ n
=

Clearly, for a given pipeline, greater speedup is achieved, as more and more instructions are executed. We can
compute the upper bound on speedup as follows:
Lim
S ideal = n

k
k 1
+1
n

=k

We regard it as ideal speedup because its derivation is based on the assumption of no pipeline hazards. As can be
seen, even ideal speedup cannot go beyond pipeline depth (i.e. number of pipeline stages).
Instruction Throughput
Instruction throughput is defined as the number of instructions executed per unit time. This is calculated as:
=

(k 1 + n )

(4)

Multiplying numerator and denominator of (4) by k, we can express in terms of speedup S as:
=

S
k

The upper bound on is similarly found:

Lim
ideal = n

1
k

+ 1

= 1/

CPI
Cycles per instruction (CPI) of pipelined execution can be found as:
CPI =

(k 1 + n )

n
k 1
=
+1
n

The lower bound on CPI is

k 1
Lim
CPI ideal = n

+ 1
n

=1

******
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