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Vlsi - CHP06
SiC Technology
The VLSI Handbook.
Ed. Wai-Kai Chen
Boca Raton: CRC Press LLC, 2000
6
SiC Technology
6.1
6.2
Introduction
Fundamental SiC Material Properties
SiC Crystallography: Important Polytypes and
Definitions SiC Semiconductor Electrical Properties
6.3
6.4
6.5
6.6
Philip G. Neudeck
NASA Glenn Research Center at
Lewis Field
6.7
6.1 Introduction
Silicon carbide (SiC)-based semiconductor electronic devices and circuits are presently being developed
for use in high-temperature, high-power, and/or high-radiation conditions under which conventional
semiconductors cannot adequately perform. Silicon carbides ability to function under such extreme
conditions is expected to enable significant improvements to a far-ranging variety of applications and
systems. These range from greatly improved high-voltage switching14 for energy savings in public electric
power distribution and electric motor drives, to more powerful microwave electronics for radar and
communications,57 to sensors and controls for cleaner-burning more fuel-efficient jet aircraft and automobile engines. In the particular area of power devices, theoretical appraisals have indicated that SiC
power MOSFETs and diode rectifiers would operate over higher voltage and temperature ranges, have
superior switching characteristics, and yet have die sizes nearly 20 times smaller than correspondingly
rated silicon-based devices.8 However, these tremendous theoretical advantages have yet to be realized in
experimental SiC devices, primarily due to the fact that SiCs relatively immature crystal growth and
device fabrication technologies are not yet sufficiently developed to the degree required for reliable
incorporation into most electronic systems.9
This chapter briefly surveys the SiC semiconductor electronics technology. In particular, the differences
(both good and bad) between SiC electronics technology and well-known silicon VLSI technology are
highlighted. Projected performance benefits of SiC electronics are highlighted for several large-scale
applications. Key crystal growth and device-fabrication issues that presently limit the performance and
capability of high-temperature and/or high-power SiC electronics are identified.
FIGURE 6.1
mission)
TABLE 6.1
Schematic cross-section {(1120) plane} of the 6H-SiC polytype. (Modified from Ref. 10. With per-
Comparison of Selected Important Semiconductors of Major SiC Polytypes with Silicon and GaAs
Property
Bandgap (eV)
Relative dielectric constant
Breakdown field ND = 1017 cm3
(MV/cm)
Thermal conductivity (W/cm-K)
Intrinsic carrier concentration (cm3)
Electron mobility @ ND =1016 cm3
(cm2/V-s)
Silicon
1.1
11.9
0.6
GaAs
1.42
13.1
0.6
4H-SiC
3.2
9.7
//c-axis: 3.0
1.5
1010
1200
0.5
1.8 106
6500
420
320
1.0
P: 45
As: 54
B: 45
1.2
Si: 5.8
30
Be, Mg, C:
28
15
3C-SiC
2.3
9.7
>1.5
35
~107
//c-axis: 800
c-axis:
800
115
6H-SiC
3.0
9.7
// c-axis: 3.2
c-axis: >1
35
~105
//c-axis: 60
c-axis:
400
90
2
N: 45
P: 80
Al: 200
B: 300
5
2
N: 85
P: 80
Al: 200
B: 300
5
2.5
N: 50
Note: Data compiled from Refs. 1113, 15, and references therein. (With permission.)
35
~10
750
40
Al: 270
None
other semiconductor materials must be evaluated. To varying degrees, the major SiC polytypes exhibit
advantages and disadvantages in basic material properties compared to silicon. The most beneficial
inherent material superiorities of SiC over silicon listed in Table 6.1 are its exceptionally high breakdown
electric field, wide bandgap energy, high thermal conductivity, and high carrier saturation velocity. The
electrical device performance benefits that each of these properties enable are discussed in the next
section, as are system-level benefits enabled by improved SiC devices.
FIGURE 6.2 Cross-section of power MOSFET structure showing various internal resistances. The resistance RD of
the N-Drift Region is the dominant resistance in high-voltage power devices. (From Ref. 8. With permission.)
FIGURE 6.3 Simulated forward conduction characteristics of ideal Si and SiC 3000 V power MOSFETs and Schottky
rectifiers. The high breakdown field of SiC relative to silicon (Table 6.1) enables the blocking voltage region (N-Drift
Region in Fig. 6.2) to be roughly 10X thinner and 10X heavier-doped, permitting a roughly 100-fold increase in onstate current density for the 3000-V SiC devices relative to 3000-V silicon devices. (From Ref. 8. With permission.)
power converters is highly desirable because it permits use of proportionally smaller capacitors, inductors,
and transformers, which in turn can greatly reduce overall system size and weight.
While SiCs smaller on-resistance and faster switching help minimize energy loss and heat generation,
SiCs higher thermal conductivity enables more efficient removal of waste heat energy from the active
device. Because heat energy radiation efficiency increases greatly with increasing temperature difference
between the device and the cooling ambient, SiCs ability to operate at high junction temperatures permits
much more efficient cooling to take place, so that heatsinks and other device-cooling hardware (i.e., fan
cooling, liquid cooling, air conditioning, etc.) typically needed to keep high-power devices from overheating can be made much smaller or even eliminated.
While the preceding discussion focused on high-power switching for power conversion, many of the
same arguments can be applied to devices used to generate and amplify RF signals used in radar and
communications applications. In particular, the high breakdown voltage and high thermal conductivity,
coupled with high carrier saturation velocity, allow SiC microwave devices to handle much higher power
densities than their silicon or GaAs RF counterparts, despite SiCs disadvantage in low-field carrier
mobility (Section 6.6).6,7,23
and availability are a prerequisite for commercial mass-production of semiconductor electronics. Many
semiconductor materials can be melted and reproducibly recrystallized into large, single crystals with
the aid of a seed crystal, such as in the Czochralski method employed in the manufacture of almost all
silicon wafers, enabling reasonably large wafers to be mass-produced. However, because SiC sublimes
instead of melting at reasonably attainable pressures, SiC cannot be grown by conventional melt-growth
techniques. This prevented the realization of SiC crystals suitable for mass-production until the late
1980s. Prior to 1980, experimental SiC electronic devices were confined to small (typically ~1 cm2),
irregularly shaped SiC crystal platelets (Fig. 6.4, right side) grown as a by-product of the Acheson process
for manufacturing industrial abrasives (e.g., sandpaper)27 or by the Lely process.28 In the Lely process,
SiC sublimed from polycrystalline SiC powder at temperatures near 2500C are randomly condensed on
the walls of a cavity forming small hexagonally shaped platelets. While these small, nonreproducible
crystals permitted some basic SiC electronics research, they were clearly not suitable for semiconductor
mass-production. As such, silicon became the dominant semiconductor fueling the solid-state technology
revolution, while interest in SiC-based microelectronics was limited.
FIGURE 6.4 Mass-produced 2.5-cm diameter 6H-SiC wafer manufactured circa 1990 via seeded sublimation by
Cree Research (left), and 6H-SiC Lely and Acheson platelet crystals (right) representative of single-crystal SiC
substrates available prior to 1989. 5.1-cm diameter seeded sublimation SiC wafers entered the commercial market
in 1997.
structural defects such as stacking faults, microtwins, and inversion domain boundaries.30,31 Furthermore,
the as-grown surface morphology of 3C-SiC grown on silicon is microscopically textured, making submicron lithography somewhat problematic. Other large-area wafer materials, such as sapphire, siliconon-insulator, TiC, etc.), have been employed as substrates for heteroepitaxial growth of SiC epilayers, but
the resulting films have been of comparably poor quality with high crystallographic defect densities.
While some limited semiconductor electronic devices and circuits have been implemented in 3C-SiC
grown on silicon,32,33 the performance of these electronics can be summarized as severely limited by the
high density of crystallographic defects to the degree that almost none of the operational benefits
discussed in Section 6.3 have been viably realized. Among other problems, the crystal defects leak
parasitic current across reverse-biased device junctions where current flow is not desired. Because excessive crystal defects lead to electrical device shortcomings, there are as yet no commercial electronics
manufactured in 3C-SiC grown on large-area substrates.
Despite the lack of major technical progress, there is strong economic motivation to continue to pursue
heteroepitaxial growth of SiC on large-area substrates, as this would provide cheap wafers for SiC
electronics that would be immediately compatible with silicon integrated circuit manufacturing equipment. If ongoing work ever solves the extremely challenging crystallographic defect problems associated
with the heteroepitaxial growth of SiC, it would likely become the material of choice for mass-production
of SiC-based electronics. Given the present electrical deficiencies of heteroepitaxial SiC, 3C-SiC grown
on silicon is more likely to be commercialized as a mechanical material in microelectromechanical systems
(MEMS) applications (Section 6.6) instead of being used purely as a semiconductor in traditional solidstate electronics.
TABLE 6.2 Commercial Vendors and Specifications of Selected Sublimation-Grown SiC SingleCrystal Wafers.
Vendor [Ref.]
Cree
[38]
Cree
[38]
Year
1993
1997
1998
1997
1997
1997
Sterling and
ATMI/Epitronics
[144][145]
1998
Product
6H n-type, Si-face, R-Grade
6H n-type, Si-face, P-Grade
6H n-type, C-face, P-Grade
6H p-type, Si-face, P-Grade
4H n-type, Si-face, R-Grade
4H n-type, Si-face, R-Grade
4H n-type, Si-face, P-Grade
4H n-type, Si-face, P-Grade
4H n-type, Si-face, R-Grade
4H n-type, Si-face, P-Grade
4H p-type, Si-face, R-Grade
4H Semi-Insulating, R-Grade
6H n-type, Si-face, P-Grade
6H p-type, Si-face, P-Grade
4H n-type
4H n-type, Quality I
4H n-type, Quality III
4H n-type, Quality I
6H n-type, Quality I
6H n-type
4H n-type
Wafer
Diameter
3.0 cm
3.0 cm
3.0 cm
3.0 cm
3.0 cm
3.5 cm
3.5 cm
3.5 cm
5.1 cm
5.1 cm
3.5 cm
3.5 cm
3.5 cm
3.5 cm
2.5 cm
3.5 cm
3.5 cm
2.5 cm
3.5 cm
3.5 cm
3.5 cm
Micropipes
(#/cm2)
2001000
2001000
2001000
2001000
2001000
100200
100200
<30
<200
<200
<200
<200
<200
<200
NA
<200
4001000
<200
<200
<100
<100
Price
(U.S.$)
1000
2900
3000
3300
3800
750
1300
2300
2100
3100
1900
4800
1000
2200
NA
1200
900
600
1200
800
800
defects such as micropipes and closed-core screw dislocations discussed in the next subsection, commercial SiC wafers also exhibit significantly rougher surfaces, and larger warpage and bow than is typical for
silicon and GaAs wafers.39 This disparity is not surprising considering that silicon and GaAs wafers have
undergone several decades of commercial process refinement, and that SiC is an extraordinarily hard
material, making it very difficult to properly saw and polish. Nevertheless, ongoing wafer sawing and
polishing process improvements should eventually alleviate wafer surface quality deficiencies.
SiC Wafer Crystal Defects
While the specific electrical effects of SiC crystal defects are discussed later in Section 6.6, the micropipe
defect (Table 6.2) is regarded as the most damaging defect that is limiting upscaling of SiC electronics
capabilities.9,40 A micropipe is a screw dislocation with a hollow core and a larger Burgers vector, which
becomes a tubular void (with a hollow diameter on the order of micrometers) in the SiC wafer that
extends roughly parallel to the crystallographic c-axis normal to the polished c-axis wafer surface.4144
Sublimation-grown 4H- and 6H-SiC wafers also contain high densities of closed-core screw dislocation
defects that, like micropipes, cause a considerable amount of localized strain and SiC lattice deformation.42,43,45,46 Similar to horizontal branches on a tree with its trunk running up the c-axis, dislocation
loops emanate out along the basal plane from screw dislocations.41,47 As shown in Table 6.2, micropipe
densities in commercial SiC wafers have shown steady improvement over a 5-year period, leading to
wafers with less than 30 micropipes per square centimeter of wafer area. However, as discussed in Section
6.6, SiC wafer improvement trends will have to accelerate if some of SiCs most beneficial high-power
applications are going to reach timely commercial fruition.
SiC Epilayers
Most SiC electronic devices are not fabricated directly in sublimation-grown wafers, but are instead
fabricated in much higher quality epitaxial SiC layers that are grown on top of the initial sublimationgrown wafer. Well-grown SiC epilayers have superior electrical properties and are more controllable and
reproducible than bulk sublimation-grown SiC wafer material. Therefore, the controlled growth of highquality epilayers is highly important in the realization of useful SiC electronics.
FIGURE 6.5 Cross-sectional schematic representation of off-axis polished SiC surface used for homoepitaxial
growth. When growth conditions are properly controlled and there is a sufficiently short distance between steps, Si
and C atoms impinging onto the growth surface find their way to steps where they bond and incorporate into the
crystal. Thus, ordered lateral step-flow growth takes place, which enables the polytypic stacking sequence of the
substrate to be exactly mirrored in the growing epilayer. (Modified from Ref. 10. With permission.)
coalescence of multiple SiC growth steps (i.e., step bunching) during epitaxy. Pre-growth wafer polishing as well as growth initiation procedures have been shown to strongly impact the formation of
undesirable epitaxial growth features.39,48 Further optimization of pre-growth treatments and epitaxial
growth initiation processes are expected to reduce undesired morphological growth features.
SiC Epilayer Doping
In situ doping during CVD epitaxial growth is primarily accomplished through the introduction of
nitrogen (usually N2) for n-type and aluminum (usually trimethyl- or triethylaluminum) for p-type
epilayers.12 Some alternative dopants such as phosphorous, boron, and vanadium have also been investigated for n-type, p-type, and semi-insulating epilayers, respectively. While some variation in epilayer
doping can be carried out strictly by varying the flow of dopant gasses, the site-competition doping
methodology53,54 has enabled a much broader range of SiC doping to be accomplished. In addition, sitecompetition epitaxy has also made moderate epilayer dopings more reliable and repeatable. The sitecompetition dopant-control technique is based on the fact that many dopants of SiC preferentially
incorporate into either Si lattice sites or C lattice sites. As an example, nitrogen preferentially incorporates
into lattice sites normally occupied by carbon atoms. By epitaxially growing SiC under carbon-rich
conditions, most of the nitrogen present in the CVD system (whether it is a residual contaminant or
intentionally introduced) can be excluded from incorporating into the growing SiC crystal. Conversely,
by growing in a carbon-deficient environment, the incorporation of nitrogen can be enhanced to form
very heavily doped epilayers for ohmic contacts. Aluminum, which is opposite to nitrogen, prefers the
Si-site of SiC, and other dopants have also been controlled through site competition by properly varying
the Si/C ratio during crystal growth. SiC epilayer dopings ranging from 9 1014 to 1 1019 cm3 are
commercially available, and researchers have reported obtaining dopings nearly a factor of 10 larger and
smaller than this range for n-type and p-type dopings. Commercial epilayer thickness and doping
tolerances are presently specified at 25% and 100%, respectively,38 while doping uniformities of 7% and
thickness uniformities of 4% over a 30-mm wafer have been reported in developmental research.48
SiC Epilayer Crystal Defects
Improvements in epilayer quality are needed as SiC electronics upscale toward production integrated
circuits, as there are presently many observable defects present in state-of-the-art SiC homoepilayers.
Non-ideal surface morphological features, such as growth pits, 3C-SiC triangular inclusions (triangle defects) introduced in Section 6.4, are generally more prevalent in 4H-SiC epilayers than 6HSiC epilayers. Most of these features appear to be manifestations of non-optimal step flow during
epilayer growth arising from substrate defects, non-ideal substrate surface finish, contamination,
and/or unoptimized epitaxial growth conditions. While by no means trivial, it is anticipated that SiC
epilayer surface morphology will greatly improve as refined substrate preparation and epilayer growth
processes are developed.
Many impurities and crystallographic defects found in sublimation-grown SiC wafers do not propagate
into SiC homoepitaxial layers. For example, basal-plane dislocation loops emanating from micropipes
and screw dislocations in sublimation-grown SiC wafers (Section 6.4) are not generally observed in SiC
epilayers.47 Unfortunately, however, screw dislocations (both micropipes and closed-core screw dislocations) present in commercial c-axis wafers do replicate themselves up the crystallographic c-axis into SiC
homoepilayers grown on commercial wafers. Therefore, as discussed later in Section 6.6, devices fabricated in commercial epilayers are still subject to electrical performance and yield limitations imposed by
commercial substrate screw-dislocation defect densities.
Alternative Growth Methods to Reduce SiC Epilayer Dislocations
As of this writing, there is no known practical method of realizing screw-dislocation-free 4H- or 6H-SiC
homoepilayers on conventional sublimation-grown substrates. Some non-conventional epitaxial growth
techniques have been attempted in an effort to prevent the propagation of micropipes into an epilayer.55,56
While these approaches have scored modest success in closing and covering up micropipes, to date there
has been little, if any, improvement demonstrated in electrical devices fabricated in the resulting material.
This is perhaps due to the fact that screw dislocations and associated harmful stresses may still be present
in the epilayer, despite the fact that some open cores may have been converted to closed cores.
Because screw dislocations propagate up the c-axis, one could conceivably alleviate screw dislocations
by growing epilayers on SiC wafers with their surface parallel to the c-axis using a-axis wafers. Unfortunately, efforts directed at realizing a-axis wafers and epilayers have to date been much less successful
than c-axis wafers and epilayers, primarily because defects that form and propagate up the basal plane
(the vertical wafer and epilayer growth direction in a-axis-oriented wafers) have proven more harmful
and difficult to eliminate than screw dislocations in conventional c-axis wafers and epilayers.36,37
Selected-area epitaxial growth techniques have recently led to startling reductions in GaN epilayer
defect densities.57 While selective-area epitaxial growth of 3C-SiC has been demonstrated, the applicability
of similar techniques to realizing superior electrical-quality SiC will be much more difficult due to the
step-flow homoepitaxial growth mechanism of -SiC as well as high growth temperatures (>1400C),
which are incompatible with conventional growth-masking materials like SiO2.
patterned high-temperature masking material. The elevated temperature during implantation promotes
some lattice self-healing during the implant, so that damage and segregation of displaced silicon and
carbon atoms does not become excessive, especially in high-dose implants often employed for ohmic
contact formation.59,60 Co-implantation of carbon with p-type dopants has recently been investigated
as a means to improve the electrical conductivity of implanted p-type contact layers.61
Following implantation, the patterning mask is stripped and a much higher temperature (~1200 to
1800C) anneal is carried out to achieve maximum electrical activation of dopant donor or acceptor ions.
The final annealing conditions are crucial for obtaining desired electrical properties from ion-implanted
layers. At higher implant anneal temperatures, the SiC surface morphology can seriously degrade as
damage-assisted sublimation etching of the SiC surface begins to take place.62 Because sublimation etching
is driven primarily by loss of silicon from the crystal surface, annealing in silicon overpressures can be
used to prevent surface degradation during high-temperature anneals. Such overpressure can be achieved
by close-proximity solid sources, such as using an enclosed SiC crucible with SiC lid and/or SiC powder
near the wafer, or by annealing in a silane-containing atmosphere.
6H-SiC (~104 to 106 ohm-cm2) than to p-type 4H- and 6H-SiC (~103 to 105 ohm-cm2). Consistent
with narrow-bandgap ohmic contact technology, it is easier to make low-resistance ohmic contacts to
heavily doped SiC. While it is possible to achieve ohmic contacts to lighter-doped SiC using hightemperature annealing, the lowest-resistance ohmic contacts are most easily implemented on SiC degenerately doped by site competition (Section 6.4) or high-dose ion implantation (Section 6.5). If the SiC
doping is sufficiently degenerate, many metals deposited on a relatively clean SiC surface are ohmic in the
as deposited state.68 Regardless of doping, it is common practice in SiC to thermally anneal contacts to
obtain the minimum possible ohmic contact resistance. Most SiC ohmic contact anneals are performed
at temperatures around 1000C in non-oxidizing environments. Depending on the contact metallization
employed, this anneal generally causes limited interfacial reactions (usually metal-carbide or metal-silicide
formation) that broaden and/or roughen the metalsemiconductor interface, resulting in enhanced conductivity through the contact.
Truly enabling harsh-environment SiC electronics will require ohmic contacts that can reliably
withstand prolonged harsh-environment operation. Most reported SiC ohmic metallizations appear
sufficient for long-term device operation up to 300C. SiC ohmic contacts that withstand heat soaking
under no electrical bias at 500 to 600C for hundreds or thousands of hours in non-oxidizing gas or
vacuum environments have also been demonstrated. In air, however, there has only been demonstration to date of a contact that can withstand heat soaking (no electrical bias) for 60 hours at 650C.69
Some very beneficial aerospace systems will require simultaneous high-temperature (T > 300C) and
high current density operation in oxidizing air environments. Electromigration, oxidation, and other
electrochemical reactions driven by high-temperature electrical bias in a reactive oxidizing environment are likely to limit SiC ohmic contact reliability for the most demanding applications. The
durability and reliability of SiC ohmic contacts is one of the critical factors limiting the practical
high-temperature limits of SiC electronics.
SiC Schottky Contacts
Rectifying metalsemiconductor Schottky barrier contacts to SiC are useful for a number of devices,
including metalsemiconductor field-effect transistors (MESFETs) and fast-switching rectifiers. References 64, 65, 67, and 70 summarize electrical results obtained in a variety of SiC Schottky studies to date.
Due to the wide bandgap of SiC, almost all unannealed metal contacts to lightly doped 4H- and 6H-SiC
are rectifying. Rectifying contacts permit extraction of Schottky barrier heights and diode ideality factors
by well-known current-voltage (I-V) and capacitance-voltage (C-V) electrical measurement techniques.63
While these measurements show a general trend that Schottky junction barrier height does somewhat
depend on metalsemiconductor workfunction difference, the dependence is weak enough to suggest
that surface state charge also plays a significant role in determining the effective barrier height of SiC
Schottky junctions. At least some experimental scatter exhibited for identical metals can be attributed to
cleaning and metal deposition process differences, as well as different barrier height measurement procedures. The work by Teraji et al.,71 in which two different surface cleaning procedures prior to titanium
deposition lead to ohmic behavior in one case and rectifying behavior in the other, clearly shows the
important role that process recipe can play in determining SiC Schottky contact electrical properties.
It is worth noting that barrier heights calculated from C-V data are often somewhat higher than
barrier heights extracted from I-V data taken from the same diode. Furthermore, the reverse current
drawn in experimental SiC diodes, while small, is nevertheless larger than expected based on theoretical
substitution of SiC parameters into well-known Schottky diode reverse leakage current equations
developed for narrow-bandgap semiconductors. Bhatnagar et al.72 proposed a model to explain these
behaviors, in which localized surface defects, perhaps elementary screw dislocations where they intersect
the SiC-metal interface, cause locally reduced junction barriers in the immediate vicinity of defects.
Because current is exponentially dependent on Schottky barrier height, this results in the majority of
measured current flowing at local defect sites instead of evenly distributed over the entire Schottky
diode area. In addition to local defects, electric field crowding along the edge of the SiC Schottky barrier
can also lead to increased reverse-bias leakage current and reduced reverse breakdown voltage.15,16,63
Schottky diode edge termination techniques to relieve electric field edge crowding and improve Schottky
rectifier reverse properties are discussed later in Section 6.6. Quantum mechanical tunneling of carriers
through the barrier may also account for some excess reverse leakage current in SiC Schottky diodes.73
The high-temperature operation of rectifying SiC Schottky diodes is primarily limited by reverse-bias
thermionic leakage of carriers over the junction barrier. Depending on the specific application and the
barrier height of the particular device, SiC Schottky diode reverse leakage currents generally grow to
excessive levels at around 300 to 400C. As with ohmic contacts, electrochemical interfacial reactions
must also be considered for long-term Schottky diode operation at the highest temperatures.
highlighting the difficulties facing SiC MOSFET development, it is important to keep in mind that early
silicon MOSFETs faced similar developmental challenges that took many years of dedicated research
effort to successfully overcome.
From a purely electrical point of view, there are two prime operational deficiencies of SiC oxides and
MOSFETs compared to silicon MOSFETs. First, effective inversion channel mobilities in most SiC MOSFETs are much lower (typically well under 100 cm2/V-s for inversion electrons) than one would expect
based on silicon inversion channel MOSFET carrier mobilities. This seriously reduces the transistor gain
and current-carrying capability of SiC MOSFETs, so that SiC MOSFETs are not nearly as advantageous
as theoretically predicted. Second, SiC oxides have not proven as reliable and immutable as well-developed
silicon oxides, in that SiC MOSFETs are more prone to threshold voltage shifts, gate leakage, and oxide
failures than comparably biased silicon MOSFETs. The excellent works by Cooper80 and Brown et al.83
discuss noteworthy differences between the basic electrical properties of n-type versus p-type SiC MOS
devices. SiC MOSFET oxide electrical performance deficiencies appear mostly attributable to differences
between silicon and SiC thermal oxide quality and interface structure that cause the SiC oxide to exhibit
undesirably higher levels of interface state densities (~1011 to 1013 eV1cm2), fixed oxide charges (~1011
to 1012 cm2), charge trapping, carrier oxide tunneling, and roughness-related scattering of inversion
channel carriers.
One of the most obvious differences between thermal oxidation of silicon and SiC to form SiO2 is the
presence of C in SiC. While most of the C in SiC converts to gaseous CO and CO2 and escapes the oxide
layer during thermal oxidation, leftover C species residing near the SiCSiO2 interface nevertheless appear
to have a detrimental impact on SiO2 electrical quality.80,81 Cleaning treatments and oxidation/anneal
recipes aimed at reducing interfacial C appear to improve SiC oxide quality. Another procedure employed
to minimize detrimental carbon effects has been to form gate oxides by thermally oxidizing layers of
silicon deposited on top of SiC.84 Likewise, deposited insulators also show promise toward improving
SiC MOSFET characteristics, as Sridevan et al.85 have recently reported greatly improved SiC inversion
channel carrier mobilities (>100 cm2/V-s) using thick deposited gate insulators.
SiC surfaces are well known to be much rougher than silicon surfaces, due to off-angle polishing
needed to support SiC homoepitaxy (Fig. 6.5) as well as step-bunching (particularly pronounced in 4HSiC) that occurs during SiC homoepilayer growth (Section 6.4).39,86 The impact of surface morphology
on inversion channel mobility is highlighted by the recent work of Scharnholz et al.,87 in which improved
mobility (>100 cm2/V-s) was obtained by specifically orienting SiC MOSFETs in a direction such that
current flowed parallel to surface step texture. The interface roughness of SiC may also be a factor in
poor oxide reliability by assisting unwanted injection of carriers that damage and degrade the oxide.
As Agarwal et al.88 have pointed out, the wide bandgap of SiC reduces the potential barrier impeding
tunneling of damaging carriers through SiC thermal oxides, so that perfectly grown oxides on atomically
smooth SiC would not be as reliable as silicon thermal oxides. Therefore, it is highly probable that
alternative gate insulators will have to be developed for optimized implementation of inversion-channel
SiC FETs for the most demanding high-power and/or high-temperature electronic applications.
SiC RF Devices
The main use of SiC RF devices appears to lie in high-frequency solid-state high-power amplification at
frequencies from around 600 MHz (UHF-band) to perhaps around 10 GHz (X-band). As discussed in
better detail in Refs. 6, 7, 23, 96, and 97, the high breakdown voltage and high thermal conductivity,
coupled with high carrier saturation velocity, allow SiC RF transistors to handle much higher power
densities than their silicon or GaAs RF counterparts, despite SiCs disadvantage in low-field carrier
mobility (Section 6.2). This power output advantage of SiC is briefly illustrated in Fig. 6.6 for the specific
case of a Class A MESFET-based RF amplifier. The maximum theoretical RF power of a Class A MESFET
operating along the DC load line shown in Fig. 6.6 is approximated by7:
I dson ( V b V knee )
P max = ------------------------------------8
(6.1)
The higher breakdown field of SiC permits higher drain breakdown voltage (Vb), permitting RF operation
at higher drain biases. Given that there is little degradation in Idson and Vknee for SiC vs. GaAs and silicon,
the increased drain voltage directly leads to higher SiC MESFET output power densities. The higher
thermal conductivity of SiC is also crucial in minimizing channel self-heating so that phonon scattering
does not seriously degrade channel carrier velocity and Idson. As discussed in Refs. 7 and 97, similar RF
output power arguments can be made for SiC-based static induction transistors (SITs).
FIGURE 6.6 Piecewise linear MESFET drain characteristic showing DC load line used in Class A RF amplifier
operation. The higher breakdown voltage Vb enabled by SiCs higher breakdown field enables operation at higher
drain biases, leading to higher RF power densities. (From Ref. 7. With permission.)
The high power density of high-frequency SiC transistors could prove very useful in realizing solidstate transmitters for cell phone base stations, high-definition television (HDTV) transmitters, and radar
transmitters, because it reduces the number of devices needed to generate sufficient RF power for these
applications. Fewer transistors capable of operating at higher temperatures reduces matching and cooling
requirements, leading to reduced overall size and cost of these systems. While excellent for fixed-base
high-power RF transmission systems, SiC RF transistors are not well suited for portable handheld RF
transceivers where drain voltage and power are restricted to function within the operational limitations
of small-sized battery packs.
Because rapid progress is being made toward improving the capabilities of SiC RF power transistors,
the reader should consult the latest electron device literature for up-to-date SiC RF transistor capabilities.
A late-1997 summary of solid-state high-power RF amplification transistor results, including 4H-SiC,
6H-SiC, silicon, GaAs, and GaN device results, is given in Fig. 6.7.7 Despite the fact that SiC RF transistors
are not nearly as optimized, they have still demonstrated higher power densities than silicon and GaAs
RF power transistors. The commercial availability of semi-insulating SiC substrates to minimize parasitic
capacitances is crucial to the high-frequency performance of SiC RF MESFETs. MESFET devices fabricated on semi-insulating substrates are conceivably less susceptible to adverse yield consequences arising
from micropipes than vertical high-power switching devices, primarily because a c-axis micropipe can
no longer short together two conducting sides of a high field junction in most areas of the lateral channel
MESFET structure. In addition to micropipes, other nonidealities, such as variations in epilayer doping
and thickness, surface morphological defects, and slow charge trapping/detrapping phenomena causing
unwanted device I-V drift,98 also limit the yield, size, and manufacturability of SiC RF transistors.
However, increasingly beneficial SiC RF transistors should continue to evolve as SiC crystal quality and
device processing technology continues to improve.
In addition to high-power RF transistors, SiC mixer diodes show excellent promise for reducing
undesired intermodulation interference in RF receivers.99 More than 20-dB dynamic range improvement
was demonstrated using non-optimized SiC Schottky diode mixers. Following further development and
optimization, SiC-based mixers should improve the interference immunity of a number of RF systems
where receivers and high-power transmitters are closely located, as well as improve the reliability and
safety of flight RF-based avionics instruments used to guide aircraft in low-visibility weather conditions.
FIGURE 6.7 Theoretical (lines) and experimental (symbols) RF power densities of RF transistors fabricated in
silicon, GaAs, SiC, and GaN as of late 1997. (From Ref. 96. With permission.)
and acceptor dopant ionization energies, so that non-trivial percentages of dopants are not ionized to
produce free carriers that carry current at or near room temperature. Thus, the resistivity of SiC layers
can sometimes initially decrease with increasing temperature as dopant atoms ionize to contribute more
current-conducting free carriers, then decrease similar to silicon after most dopant atoms have ionized
and increased phonon scattering degrades free carrier mobility. Thus, SiC transistor parameters can
exhibit temperature variations not found in silicon devices, so that new device-behavior models are
sometimes necessary to carry out proper design of wider-temperature range SiC integrated circuits.
Because of carrier freeze-out effects, it will be difficult to realize SiC-based ICs operational at temperatures
much lower than 55C (the lower end of the U.S. Mil-Spec. temperature range).
Small-scale prototype logic and analog amplifier SiC-based ICs (one of which is shown in Fig. 6.8)
have been demonstrated using SiC variations of NMOS, CMOS, JFET, and MESFET device topologies.33,83,104108 These prototypes are not commercially viable as of this writing, largely due to their high
cost, unproven reliability, and limited temperature range that is mostly covered by silicon-on-insulatorbased circuitry. However, increasingly capable and economical SiC integrated circuits will continue to
evolve as SiC crystal growth and device fabrication technology continues to improve.
FIGURE 6.8 Optical micrograph of 1 2 mm2 300C 6H-SiC operational amplifier integrated circuit. The chip
contains 14 depletion-mode N-channel MOSFETs integrated with 19 resistors (From Ref. 105. With permission)
FIGURE 6.9 Experimental SiC (symbols) and theoretical SiC and silicon (lines) Schottky diode specific on resistance
plotted as a function of off-state blocking voltage. While the graph clearly shows that the area-normalized performance
of small-area SiC devices is orders of magnitude better than silicon, these results have not been successfully upscaled
to realize large-area high-current SiC devices due to high densities of device-degrading defects present in commercial
SiC wafers and epilayers. (From Ref. 117. With permission.)
of at least an additional order of magnitude will be necessary before reasonably good power device yields
and currents will be obtained.
In addition to micropipe defects, the density of non-hollow core (elementary) screw dislocation defects
in SiC wafers and epilayers has been measured on the order of several thousands per square centimeter
of wafer area (Section 6.4). While these defects are not nearly as detrimental to device performance as
micropipes, recent experiments have shown that they degrade the leakage and breakdown characteristics
of pn junctions.109,110 Less direct experimental evidence exists to suggest that elementary screw dislocations
may also cause localized reductions in minority carrier diffusion lengths111,112 and non-uniformities and
catastrophic localized failure to high-voltage Schottky rectifiers under reverse bias.72,113 While localized
breakdown is well-known to adversely degrade silicon device reliability in high-power switching applications, the exact impact of localized breakdown in SiC devices has yet to be quantified. If it turns out
that SiC power devices roughly adhere to the same reliability physics well-known for silicon power devices,
it is possible that SiC devices containing non-hollow core screw dislocations could prove unacceptably
unreliable for use in the most demanding high-power conversion applications, such as large-motor
control and public power distribution. Thus, these applications might require much larger (i.e., much
longer-term) improvements in SiC material quality so as to eliminate all screw dislocations (both hollow
core and non-hollow core) from any given device.
SiC High-Voltage Edge Termination
For SiC power devices to successfully function at high voltages, peripheral breakdown due to edge-related
electric field crowding15,16,63 must be avoided through careful device design and proper choice of insulating/passivating dielectric materials. The peak voltage of most prototype high-voltage SiC devices has
been limited by often destructive edge-related breakdown, especially in SiC devices capable of blocking
multiple kilovolts.114,115 In addition, most testing of multi-kilovolt SiC devices has required the device to
prototype three-terminal SiC power switches have been demonstrated in recent years. For the most part,
SiC solid-state switches are based on well-known silicon device topologies, like the thyristor, vertical
MOSFETs, IGBT, GTO, etc., that try to maximize power density via vertical current flow using the
substrate as one of the device terminals. Because these switches all contain high-field junctions responsible
for blocking current flow in the OFF-state, their maximum operating currents are primarily restricted
by the material quality deficiencies discussed in Section 6.6. Therefore, while blocking voltages over 2
kV have been demonstrated in low-current devices,116 experimental SiC power switches have only realized
modest current ratings (under 1 A in most devices).
Silicon power MOSFETs and IGBTs are extremely popular in power circuits, largely because their MOS
gate drives are well insulated and require little drive signal power, and the devices are normally off in
that there is no current flow when the gate is unbiased at 0 V. However, as discussed in Section 6.5, the
performance and reliability of SiC power device structures with inversion channel MOS field-effect gates
(i.e., MOSFETs, IGBTs, etc.) are limited by poor inversion channel mobilities and questionable oxide
reliability at high-temperatures. Thus, SiC device structures that do not rely on high-quality gate oxides,
such as the thyristor, appear more favorable for more immediate realization, despite some non-trivial
drawbacks in operational circuit design and switching speed.
Recently, some non-traditional power switch topologies have been proposed to somewhat alleviate
SiC oxide and material quality deficiencies while maintaining normally off insulated gate operation.
Shenoy et al.136 and Hara137 respectively, have implemented lateral and vertical doped-channel depletion/accumulation mode power SiC MOSFETs that can be completely depleted by built-in potentials at
zero gate bias so that they are normally off. Spitz et al.116 recently demonstrated high-voltage SiC lateral
MOSFETs implemented on semi-insulating substrates. These devices could conceivably reduce the adverse
yield consequences of micropipes, because a c-axis micropipe can no longer short together two conducting
sides of a high-field junction in most regions of the device. With the assistance of lateral surface electric
field tailoring techniques, Baliga138 has suggested that lateral-conduction SiC power devices could deliver
better power densities than traditional vertical SiC power device structures. Baliga has also proposed the
advantageous high-voltage switching by pairing a high-voltage SiC MESFET or JFET with a lower-voltage
silicon power MOSFET.138
FIGURE 6.10 Micromachined SiC-based lateral resonator device. The excellent mechanical and electrical properties
of SiC are enabling the development of harsh-environment microelectromechanical systems (MEMS) for operation
beyond the limits of conventional silicon-based MEMS. (From Prof. M. Mehregany, Case Western Reserve University.
With permission.)
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