Two capacitors are connected in parallel through a switch.

C1= 1uF, C2=0.25uF.

Initially the switch is open, C1 is charged to 10V. What happens if we close the switch?
No losses in the wires and capacitors.

A:
Hint from Hitequest
Since there are no losses in the circuit the amount of charge remains the same:
U1C1 + U2C2 = U3(C1+C2)
U3 = (U1C1+U2C2)/(C1+C2) = (10*1 + 0*0.25)/1+0.25 = 8
U3= 8V

Q:
You have 2 switches to control the light in the long corridor.
You want to be able to turn the light on entering the corridor and turn it off at the other end.
Do the wiring circuit.

A:

Q:
There are 3 switches that can turn on and off a light in the room.
How to connect them?
A:

Q:
What will be the voltage level between the 2 capacitors? The Vcc = 10v DC.
Sent by Tanh, VLSI engineer

A:
Q1=C1U1; Q2=C2U2
U2=C1U/(C1+C2)=4v

Q:
You work on a specification of a system with some digital parameters.
Each parameter has Min,Typ and Max colomns.
What colomn would you put setup and hold time?

A:
put SETUP time into the Min colomn, put HOLD time into the Min colomn too.
Example:
usually the data must be set at least (minimum) X nS before the clock and being held at least Y nS after the
clock. You need to specify Min setup and Min hold time.
 =Electronics Hardware Questions=

Q:Design a simple circuit based on combinational logic to double the

output frequency.

A:

______________
____ ____ ____ | | _ _ _ _
| | | | | | | | | |||||||
_| |____| |____| |__ | | _| |_| |_| |_| |_
| |
------------------------------>| |-------------------->
| |
|______________|

|\ |\
|\ |\
____| \o_________| \o______
| | / | / |
| |/ |/ |
| |/ not |/ not |
| |
| | \\----.
| +----\\ \
| || )--------+
---+----------------------------------// /
//----'
XOR

Q: Flip flops

a)The simplest form of FF is Set-Reset FF.See the drawing and gate level schematic below.

.----.
_______ +------\ \
S | | Q o--------+
 -----| |---- ,--+------/ / |
| | | -----' |
| | _ | NOR |
R | | Q | ______________________|
-----| |---- | |
|_______| |__|_____________________
| |
| .----. |
_ +------\ \ |
S R Q Q Comment o--------+
---------------------------------------- +------/ /
0 0 Q !Q Hold condition -----'
1 0 1 0 NOR
0 1 0 1
1 1 x x Not used

b)Gated RS FF

It has two more NAND gates on R and S lines.

_______
S | | Q
-----| |----
enable | |
-----| | _
R | | Q
-----| |----
|_______|

A signal gate_enable =1 enables the work of RS FF,and gate_enable =0 disables it.

c) D-latch

Gated RS FF can be transformed into D latch by addition of an inverter.

_______
D | | Q
___________|S |----
enabl__|________||
__|__ | | _
\ / | | Q
\ / ___|R |----
v | |_______|
 o |
|____|

When gate_enable=1 D latch is transparent (Q=D),

and when gate_enable =0 the data at the output remains latched.

d) Master-Slave FF

_______ _______
| | | |
____|D Q1|_______________|S Q2|---
| | | |
| | | |
| |_______________|R |
| c | | c |
|_______| |_______|
clock | |
___________|_______________o_________|

It contains 2 FF(D-latch and RS) and inverter and works this way:
When the clock = HIGH, Q1=D ; FF2 does not change it's state since it waits for a negative
clock polarity.
On the falling edge of clock master FF1 transfers it's state to the slave FF2.

e)Edge-triggered FF

_______
D | | Q
-----| |----
clock | |
-----> | _
| | Q
| |----
|_______|

_______
D | | Q
-----| |----
clock | |
----o> | _
| | Q
| |----
|_______|

Unlikely to the D-latch these FF are edge triggered. First works on the positive
edge and second on negative edge. Input data must present T_setup time before
clock edge and remain T_hold time after.

f) JK FF

_______
J | | Q
-----| |----
clock | |
-----> | _
K | | Q
-----| |----
|_______|

J K Q Comment
----------------------------------
0 0 Q-1 Hold previous state
1 0 1
0 1 0
1 1 !(Q-1) when J=K=1 the output will change its state every clock pulse

Every transaction takes place when the clock is active (level or edge).Usually JK FF
are edge triggered.JK FF can be easily transformed into D FF by setting invertor between J and K

_______
D | | Q
___________|J |----
| | |
clk --|--------> |
__|__ | | _
\ / | | Q
\ / ___|K |----
v | |_______|
o |
|____|

:What is the difference between a flip-flop and a latch?

_______ _______
D | | Q D | | Q
-----| |---- -----| |----
clock | | enable | |
-----> | _ -----| | _
| | Q | | Q
| |---- | |----
|_______| |_______|
The example shows D-latch and D-FF.
The simplest form of data storage is latch.It's output responds immidiately
to changes at the input and the input state will be remembered, or "latched" onto.
While "enable" input is active the input of the latch is transparant to the output,
once "enable" is disactivated the output remains locked.
Flip-flops use clock as a control input. The transition on output Q occurs only at the edge
of the clock pulse. Input data must present T_setup time before
clock edge and remain T_hold time after.

* RESET input, while it is not shown, is present in most FF.

Direct-conversion ADCs
Direct conversion is also known as a flash conversion. ADCs based on this architecture are extremely fast with
a sampling rate of upto 1GHz . However, their resolution is limited because of the large number of comparators
and reference voltages required.

The input signal is fed simultaneously to all comparators. A priority encoder generates a digital output that
corresponds with the highest activated comparator. The identity of comparators is important, any mismatch can
cause a static error.
Flash ADCs have a short aperture interval - the time when the comparators' outputs are latched.

Successive-approximation ADCs
The conversion technique based on a successive-approximation register (SAR), also known as bit-weighing
conversion, employs a comparator to weigh the applied input voltage against the output of an N-bit digital-to-
analog converter (DAC). Using the DAC output as a reference, this process approaches the final result as a sum
of N weighting steps, in which each step is a single-bit conversion.

Initially all bits of SAR are set to 0. Then, beginning with the most significant bit, each bit is set to 1
sequentially. If the DAC output does not exceed the input signal voltage, the bit is left as a 1. Otherwise it is set
back to 0. It is kind of a binary search. For an n-bit ADC, n steps are required.

SAR converters sample at rates to 1Msps, draw low supply current, and offer the lowest production cost.

Integrating ADCs
A classical dual-slope converter is shown at the drawing.

A current, proportional to the input voltage, charges a capacitor for a fixed time interval Tcharge. At the end of
this interval the device resets its counter and applies an opposite-polarity (negative) reference voltage to the
integrator input. With this opposite-polarity signal applied the cap is discharged by a constant current until the
voltage at the output of the integrator reaches zero again. The time Tdischarge is proportional to the input
voltage level and used to enable a counter. The final count provides the digital output, corresponding to the
input level.
Note that even the clock frequency does not have to have high stability, because both ramp-up and ramp down
time are measured with the same clock.If the clock slows down 10%, the initial ramp will go 10% higher than
normal, requiring 10% longer ramp down time resulting in the same final count.
Only the discharge current produced by precise Vref has to be of high stability.
Integrating ADCs are extremely slow devices with low input bandwidths. But their ability to reject high-
frequency noise and fixed low frequencies such as 50Hz or 60Hz makes them useful in noisy industrial
environments and applications . Provide 10-18 bit resolution. A coversion time for a medium speed 12 bit
integrating ADC is about 20mS.
This type of ADC is most commonnly used in multi-meters.

Sigma-delta ADCs
Sigma-delta converters , also called oversampling converters, consist of 2 major blocks: modulator and digital
filter . The modulator, whose architecture is similar to that of a dual-slope ADC, includes an integrator and a
comparator with a feedback loop that contains a 1-bit DAC. The modulator oversamples the input signal,
transforming it to a serial bit stream with a frequency well above the required sampling rate. The output filter
then converts the bit stream to a sequence of parallel digital words at the sampling rate. The delta-sigma
converters perform high-speed, low resolution (1-bit) A/D conversions, and then remove the resulting high-level
quantization noise by passing the signal through analog and digital filters.
Features: high resolution , high accuracy , low noise, low cost.
Good for applications with a bandwidth upto 1MHz, such as speech, audio.

Basic Transistor Level Schematics

This paper adds a little more details to how a Sigma-Delta ADC works. For a general ADC paper refer to A/D
converters.

In the schematic above the input analog voltage drives an integrator, whose output is compared with a ground
voltage level by a comparator. D-latch controls a switch turning on/off a reference voltage, they both are
composing a 1-bit DAC. As the input voltage increases or decreases, the comparator turns on and off the
reference voltage, that is subtracted from the input signal, aiming to maintain zero on the output of the
integrator.
The counter C1 keeps track of clock periods, while counter C2 counts the number of pulses when the switch is
closed. Suppose the volume of counter C1 is 1000. By the time it gets the final count, the number in counter C2
is proportional to the average level of the input signal during the time of 1000 clock pulses.

Now the name delta-sigma is making a little more sense: delta (the difference) refers to delta modulation, the
principle of coding not the whole input value, but only the difference between the current signal sample and the
feedback signal, corresponding to the previous sample. Obviously, less bits are required to code only the
difference in the amplitudes.
Sigma (the sum) is because the sum of "deltas" is counted during the measured interval. In other words, the
input to the quantizer is the integral of the differences between the input and the output signals.

Technical papers often refer to sigma-delta converter as over-sampling. Traditional converter takes a sample of
the input signal and performs a complete conversion with it. Delta-sigma converter is averaging multiple
samples.
The penalty paid for the high resolution achievable with sigma-delta technology has always been speed - the
hardware has to operate at the oversampled rate, much larger than the maximum signal bandwidth, thus
demanding greater complexity of the digital circuitry. Because of this limitation, these converters have
traditionally been used in high-resolution low frequency applications (up to 1 MHz, such as speech, audio,
precise voltage and temperature measurements).
With an understanding of Boolean Algebra, drawing the transistor level schematic is reasonably easy. In CMOS
layout design, there are two sides to a device. The side that will create the logical 0 output and the side that will
create the logical 1. The Boolean formula indicates one of these sides, while the other is the compliment (exact
opposite).

It turns out that it is impossible to directly make an AND and an OR gate using a CMOS technique. What
happens is that they automatically invert. Therefore, you can make inverted AND gates (called NAND),
inverted OR gates (called NOR). and INVERTERS.

AND |NAND OR |NOR

#1 #2 O|O #1 #2 O|O
-------|- -------|-
0 0 0|1 0 0 0|1
0 1 0|1 0 1 1|0
1 0 0|1 1 0 1|0
1 1 1|0 1 1 1|0

Notice how the NAND gate output is exactly opposite of the AND gate, and the same with the NOR relative to
the OR gate. In an AND and an OR gate, when the condition is met you get a true. However for a NAND and a
NOR gate, you get a false. Literally, just like adding an inverter.

____ ____
A --| \ |\ A --| \ _____
| )--| O-- C | O-- C C = A * B
B --|____/ |/ B --|____/

AND + INV = NAND

____ ____
A --\ \ |\ B --\ \ _____
) )--| O-- C ) O-- C C = A + B
B --/____/ |/ A --/____/

OR + INV = NOR

In the equation for the NAND and NOR gates, the right side of the equation has a long line over it that
represents the inverter. In CMOS, the only way to get an AND function is to run the output of the NAND gate
into an INVERTER, thereby inverting it back. Likewise to get an OR function, a NOR's output goes into an
INVERTER.

Therefore, the Boolean formula tells you exactly what the transistors look like to get the logical 0 voltage. Once
the condition is met the output is a logical 0, NOT a logical 1.

There are two types of transistors used in CMOS (actually, they are called "FETs" or "Field Effect Transistors"
instead of regular transistors). The FETs used on the bottom are N-FETs, while the ones on the upper half of the
gate are P-FETs. They operate the same way except they need opposite voltages to turn "on." N-FETs need a
logical 1 while P-FETs need a logical 0. They also have different schematic symbols.
 | leg #2 | leg #2
| |
|__ |__
|| ||
||---- input ||o--- input
__|| __||
| |
| |
| leg #1 | leg #1

N-FET P-FET

The P-FET symbol is drawn with a little circle on the input, while the N-FET isn't. This can be used to
remember that the P-FET requires a logical 0 to turn on. When the transistor is "off", legs 1 and 2 are not
connected. However, once the transistor is turned on, legs 1 and 2 are connected. Therefore, CMOS FETs act
almost like a switch, On/Off. With that explained, it is possible to make transistor level schematics of various
logic gates.

____
A --| \ _____
| O-- C C=A*B
B --|____/

For C to meet the condition, A AND B must be on. Note, the "condition" will make C a logical 0 instead of 1,
because of the INVERTER. However, it does not change what condition must be met (only the result). This
means that either one being off will violate the condition, so the bottom portion of the gate requires both A AND
B.

__ C
|
_|
A_||
||_
|
_|
B_||
||_
|
|
---
\/
v

For C to "get to" ground (logical 0), represented by the arrow head pointing down, it must pass through A AND
B (series circuit).

_____
A --\ \ _____
) O-- C C=A+B
B --/____/
 _______ C
| |
_| |_
A_|| ||_B
||_ _||
|___|
|
|
---
\/
v

While in an NOR gate, C can pass through either A OR B (parallel circuit). Remember that the P-FETs are
configured the opposite of the N-FETs. The opposite of parallel is series and the opposite of series is naturally
parallel. Therefore, the complete transistor level schematic for a NAND gate and a NOR gate are...

_______ _______
| |
--- _|
| | A_o||
_| |_ ||_
A_o|| ||o_B |
||_ _|| _|
| | B_o||
|___|_____ C ||_
_| |
A_|| _|_____C
||_ | |
| _| |_
_| A_|| ||_B
B_|| ||_ _||
||_ | |
| |___|
| |
--- ---
\/ \/
v v

NAND NOR

The long line on top represents power (logical 1). The transistor level schematic for an INVERTER is simply...

_______
|
_|
A_o||
||_
|
|___B
|
_|
A_||
||_
|
|
---
\/
v

INVERTER

1. What is D-FF?

for question num 1

D-FF stand for Delay-type Flip-Flop.Its a logic gate used in logic design n perform varioyus
functions.its truth table is as follows:
A o/p
11
00

output is same but just delayed it has one input n only one output

2. What is the basic difference between Latches and Flip flops?

Latch is level triggered and Flipflop is edge triggered.

In latch, wn ever clock is 1 wt ever may b the changes in input signals those r replecated in output
signals but in flipflop ,it passes the input to the output only at positive or negitive edge of the clock.

a latch is a level triggered device whereas a flip flop is edge triggered.

latches and flip-flops are the building blocks of sequential circuits. While gates had to be built directly from
transistors, latches can be built from gates, and flip-flops can be built from latches. This fact will make it
somewhat easier to understand latches and flip-flops.
Both latches and flip-flops are circuit elements whose output depends not only on the current inputs, but
also on previous inputs and outputs. The difference between a latch and a flip-flop is that a latch does not
have a clock signal, whereas a flip-flop always does.

Latches are asynchronous, which means that the output changes very soon after the input changes

A flip-flop is a synchronous version of the latch

3. What is a multiplexer?

for quwstion num 3

Multiplexer is “many to one” kind of switch ther r many inputs n allows only one out at a time based on
its status lines.
status lines decides which input to be connected to output. Qus:3 Multiplexer
This is a digital circuit with multiple signal inputs, one of which is selected by separate address inputs to
be sent to the single output.
The multiplexer circuit is typically used to combine two or more digital signals onto a single line, by
placing them there at different times. Technically, this is known as time-division multiplexing.
4. How can you convert an SR Flip-flop to a JK Flip-flop?

First we should know the concept of edge triggering

Consider two RS latchs (R & S as inputs and Q & Q’as outputs), one as master and the other as slave. If
the clock signal is at logic 0 the the resulting output at Q and Q’ are not affected.

If the clock is at Logic 1, any changes at the input are not reflected at the output

If the clock falls from logic 1 to logic 0 then the current state of input latch reaches the output latch.
Therefore the outputs change only when the clock falls from Logic 1 to Logoc 0. This is known as edge
triggering.

The process of adding additional feedback from slave latch to master latch results in JK flipflop

5. How can you convert an JK Flip-flop to a D Flip-flop?

6. What is Race-around problem? How can you rectify it?
7. Which semiconductor device is used as a voltage regulator and why?

for question no 7
the zener diode is used for the voltage regulator because it finishs the ripples from the signals taken.

A Zener diode is used as a Voltage regulator because when the Zener diode is reverse biassed, at a
certain Voltage known as the Zener breakdown, the voltage across the Zener diode remains constant
irrepective of the current passing through it.

8. Explain an ideal voltage source?

An ideal voltage source is a device that supplies constant potential difference across its terminals and is
independent of current it supplies.

9. Explain zener breakdown and avalanche breakdown?

zenner breakdown:- zenner diode is nothing but pn junction diode when current passes through it for
long time the temp of diode increases and if the current flows throgh diode furthur the temp increases
rapidly and hence breakdown occurs called zenner breakdown.

avalaunche breakdown:- zenner diode consist of p-type and n=type material which contains holes and
electrons,when current flows through it the electrons coinside over each other due to which heat is produced
which leads to rise the temp of diode and hece the breakdown occurs

10. What are the different types of filters?

11. What is the need of filtering ideal response of filters and actual response of filters?
12. What is sampling theorem?
 Sampling frequency should be twice the highest frequency component in the signal to be measured.

However, samples recieved in this manner are good only for finding the values of the signal and cannot
be used for reconstructing the signal shape. That would require many more times the sampling
frequency as defined above.

13. What is impulse response?

Consider a filter (LTI), then ” Impulse response is the response of the filter at time ‘n’ to unit impulse
occuring at time ‘0′”

14. Explain the advantages and disadvantages of FIR filters compared to IIR counterparts.
15. What is CMRR?

CMRR IS A PARAMETER USED TO DEFINE THE CHARACTERISTICS OF AN OPERATIONAL

AMPLIFIER. IT ACTUALLY SAYS HOW MUCH OF NOISE SIGNAL IS BEING AMPLIFIED BY
THE OP-AMP.
CMRR= DIFFERENTIAL GAIN/COMMON MODE GAIN(NOISE).FOR A GOOD OP-AMP CMRR
MUST BE VERY HIGH(INFINITY).

16. Explain half-duplex and full-duplex communication?

for question 16
half duplex: It isa the type of communication in which there r is two way communication but not
simultabneously. eg: walki-talki.

Full duplex: It is a type of communication in which there is two way simultaneous communication
between two parties the best eg. is Telephone, Mobile..

17. Which range of signals is used for terrestrial transmission?

18. Why is there need for modulation?

-practicability of antennas..we cant construct antennas having height in kms…

-narrowbanding-by modulating a signal with a high frequency such as 10 mhz we can actually transfer
the whole band without any loss…

We need modulation to make a signal to travel a longer distance..

Modulation is the process of shifting the frequency of the message signal to higher frequency without
affecting the message .
E=hv is a formula formulated by planck. Here h is the planck’s constant and v is the frequency and E is
the energy . If the frequency increases, the energy of the signal also increases which will enable the
signal to travel a long distance before dying out.

In amplitude modulation, there are two frequencies, the carrier frequency and the modulation
frequency.The carrier frequency is very high and has greater energy so that it can travel over large
 distances unaided. On the other hand, the signal frequency is low and is not energetic enough to travel
alone over long distances. So, the signal frequency modulates the carrier amplitude and rides on top of
the carrier frequency so that it gets carried by the latter over large distances.Frequency modulation is
similar but in this case the high frequency of the carrier is moulated and varied by the low frequency of
the signal.

19. Which type of modulation is used in TV transmission?

for question 19
in television FM(frequency modulation)is used rather thn AM(amplitude modulation). both the
Frequency modulation and Amplitude modulation are used in TV transmission. In TV transmission we
have two signals. Picture signal and Sound signal. For Sound signal we use frequency modulation and
for picture signal we use Vestigial side band modulation ( its a type of amplitude modulation ).

20. Why we use vestigial side band (VSB-C3F) transmission for picture?
21. When transmitting digital signals is it necessary to transmit some harmonics in addition to fundamental
frequency?
22. For asynchronous transmission, is it necessary to supply some synchronizing pulses additionally or to
supply or to supply start and stop bit?

for q 22
yes offcourse it is necessary to supply synchronizing pulses or start n stop bits to synchronize the remote
user or the opposite party as for any communication it is necessary to synchronize both the
communicating parties. Tat if the communication is asynchronous it is necessaary to do so.

23. BPFSK is more efficient than BFSK in presence of noise. Why?

24. What is meant by pre-emphasis and de-emphasis?

Pre-emphasis refers to ” Improving the signal to noise ratio by increasing the magnitude of higher
frequency signals with respect to lower frequency signals”.

Deemphasis refers to ” Improving the signal to noise ratio by decreasing the magnitude of higher
frequency signals with respect to lower frequency signals”

25. Explain 3 dB cutoff frequency? Why is it 3 dB, not 1 dB?

 In electronics, cutoff frequency (fc) is the frequency either above which or below which the power
output of a circuit, such as a line, amplifier, or electronic filter is 1 / 2 the power of the passband, and
since voltage V2 is proportional to power P, V is \sqrt{1/2} of the V in the passband. This happens to be
close to −3 decibels, and the cutoff frequency is frequently referred to as the −3 dB point. Also called the
knee frequency, due to a frequency response curve’s physical appearance.

Power value for a signal to be considered faithful = 1/2 the max power for that signal
=> Pacceptable/Pmax = 1/2 = -3 db ( log10(1/2)=-3)
To calculate BW (bandwidth) , this figure is used.

26. Explain ASCII, EBCDIC?

Extended Binary-Coded Decimal Interchange Code. A standard character-to-number encoding (like

ASCII) used by some IBM computer systems. For example, Oracle on OS390 (IBM MVS) stores data as
EBCDIC characters.

What is sampling theorem?

Frequency of sampling needs to be atleast twice the max frequency of the signal to be sampled.

race around - if the input to an edge triggered device changes its state at exactly the clock event - then
should the output be the old state or the new state of the input?

Solution: do not allow the input to change for a certain amount of time (say 20ns) before the clock event.
U also need to take the device setup time into account.

There are three types of filters.

1.low pass filter-low frequency filter.
2.high pass filter-high frequency filter.
3.band pass filter- combination of low
pass and high pass filters

What is Virtual Grounding?

Virtual grounding is the shorting of the inverting and the non-inverting terminals of the op-amp.

The i/p resistance of opamp is v high. thus the base currents are v less, approx 0. thus no current flows thru i/p
resistance. thus we can say that both the NI and INV terminals of opamp are virtually shorted. i.e the voltage
across both terminals is same. thus if NOW one terminal is grounded, due to virtual short other terminal also
will be grounded.
why the input resistance of an op-amp is high whereas it's output resistance is low?
A.Loading at the input point and to pass the maximum output to the load is the requirement of Op-Amp which
is a current exchange device from input side to output side.

Q.what do you understand by microwaves? why these are called micro

A.micro waves are those waves whose wavelength is less than a foot(30 cms) or freq ranging from 1 GHz to
1000 GHz.Because of there tinyness these are called micro.

Q. how do microwave oven works??

A. Heart of microwave oven is magnatron which generates frequency of appox. 2.4 GHz.explain working of
magnatron.

Q.What is CMRR? Explain briefly.

A. CMRR stands for common mode rejection ratio. It is a measure of the ability of a test instrument to reject
interference that is common to both of its measurement input terminals. It is expressed in decibels and it is the
ratio of the actual or common signal level appearing on the
two input terminals together to the measured level

1: What is difference between Microprocessor and Microcontroller ?

2: Why is Zener Diode always used in Reverse Bias condition ?

3: Difference between FM and AM, which is preferred & its advantages.

4: Questions on different coding techniques ?

5: Questions on signal processing techniques ?

6: What is RS in RS-232 ?

7: What is Lenz law ?

8: What is Transmission Frequency of Bluetooth, Wi-Fi and Wi-MAX ?

9: What is difference between Piconet and Scatternet ?

10: What is Moore's Law ?

11: How many satellites comprise the GPS and expand it ?

12: What is ZigBee and its specifications ?

13: What is FPGA ?

14: What is MIMO ?

15: What is VOIP ?

16: On what principle do Transformers work ?

17: What is EDFA ?

18: What are different types of antennas ?

19: What is Yagi-Uda antenna ?

20: What is latest satellite from ISOR ?

1.What are the flags in 8086?

Carry flag, Parity flag, Auxiliary carry flag, Zero flag, Overflow flag, Trace flag, Interrupt flag, Direction flag,
and Sign flag.

2.What are the various interrupts in 8086??

Maskable interrupts, Non-Maskable interrupts

3.What is meant by Maskable interrupts?

An interrupt that can be turned off by the programmer is known as Maskable interrupt.

4.Which interrupts are generally used for critical events??

Non-Maskable interrupts are used in critical events Such as Power failure, Emergency, Shut off etc.

5.What is the Maximum clock frequency in 8086?

5 Mhz is the Maximum clock frequency in 8086.

6.What are the various segment registers in 8086?

Code, Data, Stack, Extra

7.Which Stack is used in 8086?

FIFO (First In First Out) stack is used in 8086.In this type of Stack the first stored information is retrieved first.

1.What are the various registers in 8085?

Accumulator register, Temporary register, Instruction register, Stack Pointer, Program Counter are the various
registers in 8085 .

2.What is Stack Pointer

Stack pointer is a special purpose 16-bit register in the Microprocessor, which holds the address of the top of the
stack

3.What is Program counter?

Program counter holds the address of either the first byte of the next instruction to be fetched for execution or
the address of the next byte of a multi byte instruction, which has not been completely fetched. In both the cases
it gets incremented automatically one by one as the instruction bytes get fetched. Also Program register keeps
the address of the next instruction.

4.Which Stack is used in 8085?

LIFO (Last In First Out) stack is used in 8085.In this type of Stack the last stored information can be retrieved
first.

5.What is meant by a bus?

A bus is a group of conducting lines that carriers data, address, & control signals.

6.What is Tri-state logic?

Three Logic Levels are used and they are High, Low, High impedance state. The high and low are normal logic
levels & high impedance state is electrical open circuit conditions. Tri-state logic has a third line called enable
line.

7.Give an example of one address microprocessor?

8085 is a one address microprocessor.

8.In what way interrupts are classified in 8085?

In 8085 the interrupts are classified as Hardware and Software interrupts.

9.examples of Software interrupts?

RST0, RST1, RST2, RST3, RST4, RST5, RST6, RST7.

10.EXAMPLES of Hardware interrupts?

TRAP, RST7.5, RST6.5, RST5.5, INTR.

11.Which interrupt has the highest priority?

TRAP has the highest priority.

12.Name 5 different addressing modes?

Immediate, Direct, Register, Register indirect, Implied addressing modes.

13.How many interrupts are there in 8085?

There are 12 interrupts in 8085.

14.What is clock frequency for 8085?

3 MHz is the maximum clock frequency for 8085.

15.In 8085 which is called as High order / Low order Register?

Flag is called as Low order register & Accumulator is called as High order Register.

16.Why crystal is a preferred clock source?

Because of high stability, large Q (Quality Factor) & the frequency that doesn’t drift with aging. Crystal is used
as a clock source most of the times.

17.What does Quality factor mean?

The Quality factor is also defined, as Q. So it is a number, which reflects the lossness of a circuit. Higher the Q,
the lower are the losses.

1.what is the differnce between SCR and diode rectifier?

ans: diode is a 2 terminal device, in scr gate controls the rectifing.SCR is used in High frequency applications
but diode is low freuency devices, SCR can be in high temparatures but not diode.

2.whatis intersymbol interference

ans:In telecommunication, intersymbol interference (ISI) means a form of distortion of a signal that causes the
previously transmitted symbols to have an effect on the currently received symbol. This is usually an unwanted
phenomenon as the previous symbols have similar effect as noise, thus making the communication less reliable.
ISI is usually caused by echoes or non-linear frequency response of the channel. Ways to fight against
intersymbol interference include adaptive equalization or error correcting codes (especially soft-decoding with
Viterbi algorithm).

3.Distinguish between Angle modulation and Amplitude modulation.

ans: In amplitude Modulation as the amplitude of given signal varies, the amplitude of carrier signal also varies
in the same way.
In angle modulation, the frequency or phase may vary according to the amplitude of given signal

4.What is Biasing?
ans: biasing is a process of connecting dc voltage to a device by which we can select the operating point of the
device. by biasing actually we select the operating point of the device.

5.What do you mean by ASCII, EBCDIC?

ans:ASCII (American Standard Code for Information Interchange), is a character encoding based on the English
alphabet.

EBCDIC (Extended Binary Coded Decimal Interchange Code) is an 8-bit character encoding used on IBM
mainframe operating systems

6.What do you mean by 3 dB cutoff frequency? Why is it 3 dB, not 1 dB?

ans:3db implies 70%(o.7o7) of the power,i'e we r interested to consider the bandwidth range from peak to 70%
b'coz uptp 70% its reliable.hence 3db is called as half power freq. 3db value is the mean square value which is
70% of the maximum value.

7.What is meant by pre-emphasis and de-emphasis?

ans:Pre-emphasis
" Improving the signal to noise ratio by increasing the magnitude of higher frequency signals with respect to
lower frequency signals"

De-emphasis
" Improving the signal to noise ratio by decreasing the magnitude of higher frequency signals with respect to
lower frequency signals"

8.What is sampling theorem?

ans:It is defined as the sampling frequency should be greater than or equal to twice the sampling frequency then
we can generate the original signal if the condition does not satisfy we get the signal in the distorted mannerit is
given as ( fs >/ 2 fs)

9.What is Race-around problem? How can you rectify it?

ans: A condition in logic network in which the difference in propagation times through two or more signal paths
in the network can produce an erroneous output.in jk flip flop race around problem will occur when both the
inputs are high. it can be prevented by using master slave jk flip flop

10.What is the basic difference between Latches and Flip flops?

ans:latch works without clock signal,but works with a control signal and it is level triggered device.whereas flip
flop is a 1 bit storage element and works with a clock signal.its a edge triggered device. normally latches are
avoided and flip flops are preferred.

11. what is Barkhausen Criterion?

ans:
1./AB/=1,i.e. the magnitude of loop gain must be unity
2.the total prase shift around the closed loop is zero or 360 degrees.

12.what are active and Passive Components?

ans:ACTIVE COMPONENTS The components which produce the energy in the form of current or voltage are
called as active components.Example:transistors etc,.

PASSIVE COMPONENTS
The components which stores the energy in the form of current or voltage are called as passive
components.example:inductors,resistors,capacitors etc
Ideal voltage source is a circuit element where the voltage across it is independent of the current through it. It
only exists in mathematical models of circuits. If the voltage across an ideal voltage source can be specified
independently of any other variable in a circuit, it is called an independent voltage source.

Impulse response of a system is its output when presented with a very brief input signal, an impulse. A system
in the class known as LTI systems (linear, time-invariant systems) is completely characterized by its impulse
response. The Laplace transform of the impulse response function is known as the transfer function. It is usually
easier to analyze systems using transfer functions as opposed to impulse response functions. The Laplace
transform of a system's output may be determined by the multiplication of the transfer function with the input
function in the complex plane, also known as the frequency domain. An inverse Laplace transform of this result
will yield the output function in the time domain. To determine an output function directly in the time domain
requires the convolution of the input function with the impulse response function.

Finite impulse response (FIR) filter is a type of a digital filter. The impulse response, the filter's response to a
Kronecker delta input, is 'finite' because it settles to zero in a finite number of sample intervals. This is in
contrast to infinite impulse response filters which have internal feedback and may continue to respond
indefinitely.
A FIR filter has a number of useful properties which sometimes make it preferable to an infinite impulse
response filter. FIR filters:
* Are inherently stable. This is due to the fact that all the poles are located at the origin and thus are located
within the unit circle.
* Require no feedback. This means that any rounding errors are not compounded by summed iterations. The
same relative error occurs in each calculation.
* They can be designed to be linear phase, which means the phase change is proportional to the frequency.

Infinite impulse response (IIR) is a property of signal processing systems. They have an impulse response
function which is non-zero over an infinite length of time. The simplest analog IIR filter is an RC filter made up
of a single resistor (R) feeding into a node shared with a single capacitor (C). This filter has an exponential
impulse response characterized by an RC time constant.

Common-mode rejection ratio (CMRR) of a differential amplifier (or other device) measures the tendency of
the device to reject input signals common to both input leads. A high CMRR is important in applications where
the signal of interest is represented by a small voltage fluctuation superimposed on a (possibly large) voltage
offset, or when relevant information is contained in the voltage difference between two signals.

Signal-to-noise ratio (often abbreviated SNR or S/N) defined as the ratio of a signal power to the noise power
corrupting the signal. In less technical terms, signal-to-noise ratio compares the level of a desired signal (such
as music) to the level of background noise. The higher the ratio, the less obtrusive the background noise is.

Asynchronous transmission uses start and stop bits to signify the beginning bit ASCII character would
actually be transmitted using 10 bits e.g.: A "0100 0001" would become "1 0100 0001 0". The extra one (or zero
depending on parity bit) at the start and end of the transmission tells the receiver first that a character is coming
and secondly that the character has ended. This method of transmission is used when data is sent intermittently
as opposed to in a solid stream. In the previous example the start and stop bits are in bold. The start and stop bits
must be of opposite polarity. This allows the receiver to recognize when the second packet of information is
being sent.

Synchronous transmission uses no start and stop bits but instead synchronizes transmission speeds at both the
receiving and sending end of the transmission using clock signals built into each component. A continual stream
of data is then sent between the two nodes. Due to there being no start and stop bits the data transfer rate is
quicker although more errors will occur, as the clocks will eventually get out of sync, and the receiving device
would have the wrong time that had been agreed in protocol (computing) for sending/receiving data, so some
bytes could become corrupted (by losing bits). Ways to get around this problem include re-synchronization of
the clocks and use of check digits to ensure the byte is correctly interpreted and received.

Difference between real ground and virtual ground

Virtual ground (sometimes called virtual earth) is an important concept found in electronic circuit designs. It
identifies a point in a circuit as being held close to the circuit's ground or reference level electric potential. It is
called virtual since this point does not have any real electrical connection to ground. The reference may or may
not be the same as the local utility ground or earth
Real ground: Voltage is a differential quantity, which appears between two points. In order to deal only with a
voltage (an electrical potential) of a single point, the second point has to be connected to a reference point
(ground) having usually zero voltage. This point has to have steady potential, which does not vary when the
electrical sources "attack" the ground by "injecting" or "sucking" a current to/from it. Usually, the power supply
terminals serve as grounds; when the internal points of compound power sources are accessible, they can also
serve as real grounds

BUS: In computer architecture, a bus is a subsystem that transfers data between computer components inside a
computer or between computers. Unlike a point-to-point connection, a bus can logically connect several
peripherals over the same set of wires. Each bus defines its set of connectors to physically plug devices, cards or
cables together. Early computer buses were literally parallel electrical buses with multiple connections, but the
term is now used for any physical arrangement that provides the same logical functionality as a parallel
electrical bus.

Pull-up resistors are resistors used in the design of electronic logic circuits to ensure that inputs to logic
systems settle at expected logic levels if external devices are disconnected. Pull-up resistors may also be used at
the interface between two different types of logic devices, possibly operating at different power supply voltages.
The idea of a pullup resistor is that it weakly "pulls" the voltage of the wire it's connected to towards 5V (or
whatever voltage represents a logic "high"). However, the resistor is intentionally weak (high-resistance)
enough that, if something else strongly pulls the wire toward 0V, the wire will go to 0V.

Transponder: An automatic device that receives, amplifies, and retransmits a signal on a different frequency
(see also broadcast translator).

Superconductivity is a phenomenon occurring in certain materials at extremely low temperatures,

characterized by exactly zero electrical resistance and the exclusion of the interior magnetic field. The electrical
resistivity of a metallic conductor decreases gradually as the temperature is lowered. However, in ordinary
conductors such as copper and silver, impurities and other defects impose a lower limit. Even near absolute zero
a real sample of copper shows a non-zero resistance. The resistance of a superconductor, on the other hand,
drops abruptly to zero when the material is cooled below its "critical temperature". An electric current flowing
in a loop of superconducting wire can persist indefinitely with no power source.
Frequently Asked Questions - Electronics Engg.

1. Insights of an inverter. Explain the working?

2. Insights of a 2 input NOR gate. Explain the working?
3. Insights of a 2 input NAND gate. Explain the working?
4. Implement F= not (AB+CD) using CMOS gates?
5. Insights of a pass gate. Explain the working?
6. Why do we need both PMOS and NMOS transistors to implement a pass gate?
7. What does the above code synthesize to?
8. Cross section of a PMOS transistor?
9. Cross section of an NMOS transistor?
10. What is a D-latch? Write the VHDL Code for it?
11. Differences between D-Latch and D flip-flop?
12. Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?
13. What is latchup? Explain the methods used to prevent it?
14. What is charge sharing?
15. While using logic design, explain the various steps that r followed to obtain the desirable design in a well
defined manner?
16. Why is OOPS called OOPS? (C++)
17. What is a linked list? Explain the 2 fields in a linked list?
18. Implement a 2 I/P and gate using Tran gates?
19. Insights of a 4bit adder/Sub Circuit?
20. For f = AB+CD if B is S-a-1, what r the test vectors needed to detect the fault?
21. Explain various adders and diff between them?
22. Explain the working of 4-bit Up/down Counter?
23. A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW for 4 clock
ticks, B = 1. Draw a state diagram for this Spec?
24. Advantages and disadvantages of Mealy and Moore?
25. Id vs. Vds Characteristics of NMOS and PMOS transistors?
26. Explain the operation of a 6T-SRAM cell?
27. Differences between DRAM and SRAM?
28. Implement a function with both ratioed and domino logic and merits and demerits of each logic?
29. Given a circuit and asked to tell the output voltages of that circuit?
30. How can you construct both PMOS and NMOS on a single substrate?
31. What happens when the gate oxide is very thin?
32. What is setup time and hold time?
33. Write a pseudo code for sorting the numbers in an array?
34. What is pipelining and how can we increase throughput using pipelining?
35. Explain about stuck at fault models, scan design, BIST and IDDQ testing?
36. What is SPICE?
37. Differences between IRSIM and SPICE?
38. Differences between netlist of HSPICE and Spectre?
39. What is FPGA?
40. Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly, M1 and
diffusion layers etc?
41. Draw the Layout of an Inverter?
42. If the current thru the poly is 20nA and the contact can take a max current of 10nA how would u overcome
the problem?
43. Implement F = AB+C using CMOS gates?
44. Working of a 2-stage OPAMP?
45. 6-T XOR gate?
46. Differences between blocking and Non-blocking statements in Verilog?
47. Differences between Signals and Variables in VHDL? If the same code is written using Signals and
Variables what does it synthesize to?
48. Differences between functions and Procedures in VHDL?
49. What is component binding?
50. What is polymorphism? (C++)
51. What is hot electron effect?
52. Define threshold voltage?
53. Factors affecting Power Consumption on a chip?
54. Explain Clock Skew?
55. Why do we use a Clock tree?
56. Explain the various Capacitances associated with a transistor and which one of them is the most prominent?
57. Explain the Various steps in Synthesis?
58. Explain ASIC Design Flow?
59. Explain Custom Design Flow?
60. Why is Extraction performed?
61. What is LVS, DRC?
62. Who provides the DRC rules?
63. What is validation?
64. What is Cross Talk?
65. Different ways of implementing a comparator?
66. What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?
67. What is clock feed through?
68. Implement an Inverter using a single transistor?
69. What is Fowler-Nordheim Tunneling?
70. Insights of a Tri-state inverter?
71. If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
72. Differences between Array and Booth Multipliers?
73. Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
74. Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?
75. Insights of a Tri-State Inverter?
76. Basic Stuff related to Perl?
77. Have you studied buses? What types?
78. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the
latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
79. How many bit combinations are there in a byte?
80. For a single computer processor computer system, what is the purpose of a processor cache and describe its
operation?
81. Explain the operation considering a two processor computer system with a cache for each processor.
82. What are the main issues associated with multiprocessor caches and how might you solve them?
83. Explain the difference between write through and write back cache.
84. Are you familiar with the term MESI?
85. Are you familiar with the term snooping?
86. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in
heads.
87. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
88. You have a driver that drives a long signal & connects to an input device. At the input device there is either
overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
89. What are the total number of lines written by you in C/C++? What is the most complicated/valuable
program written in C/C++?
90. What compiler was used?
91. What is the difference between = and == in C?
92. Are you familiar with VHDL and/or Verilog?
93. What types of CMOS memories have you designed? What were their size? Speed?
94. What work have you done on full chip Clock and Power distribution? What process technology and budgets
were used?
95. What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
96. Process technology? What package was used and how did you model the package/system? What parasitic
effects were considered?
97. What types of high speed CMOS circuits have you designed?
98. What transistor level design tools are you proficient with? What types of designs were they used on?
99. What products have you designed which have entered high volume production?
100. What was your role in the silicon evaluation/product ramp? What tools did you use?
101. If not into production, how far did you follow the design and why did not you see it into production?
102. What types of CMOS memories have you designed? What were their size? Speed? Configuration Process
technology?
103. What work have you done on full chip Clock and Power distribution? What process technology and
budgets were used?
104. What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
Process technology? What package was used and how did you model the package/system? What parasitic
effects were considered?
105. What types of high speed CMOS circuits have you designed?
106. What transistor level design tools are you proficient with? What types of designs were they used on?
107. What products have you designed which have entered high volume production?
108. What was your role in the silicon evaluation/product ramp? What tools did you use?
109. If not into production, how far did you follow the design and why did not you see it into production?

The following questions are used for screening the candidates during the first interview. The questions apply
mostly to fresh college grads pursuing an engineering career at Intel.
1. Have you studied buses? What types?
2. Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the
latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
3. How many bit combinations are there in a byte?
4. For a single computer processor computer system, what is the purpose of a processor cache and describe its
operation?
5. Explain the operation considering a two processor computer system with a cache for each processor.
6. What are the main issues associated with multiprocessor caches and how might you solve them?
7. Explain the difference between write through and write back cache.
8. Are you familiar with the term MESI?
9. Are you familiar with the term snooping?
10. Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in
heads.
11. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
12. You have a driver that drives a long signal & connects to an input device. At the input device there is either
overshoot, undershoot or signal threshold violations, what can be done to correct this problem?
13. What are the total number of lines written by you in C/C++? What is the most complicated/valuable
program written in C/C++?
14. What compiler was used?
15. What is the difference between = and == in C?
16. Are you familiar with VHDL and/or Verilog?
17. What types of CMOS memories have you designed? What were their size? Speed?
18. What work have you done on full chip Clock and Power distribution? What process technology and budgets
were used?
19. What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?
20. Process technology? What package was used and how did you model the package/system? What parasitic
effects were considered?
21. What types of high speed CMOS circuits have you designed?
22. What transistor level design tools are you proficient with? What types of designs were they used on?
23. What products have you designed which have entered high volume production?
24. What was your role in the silicon evaluation/product ramp? What tools did you use?
25. If not into production, how far did you follow the design and why did not you see it into production?