Comparative Analysis of MCML Compressor with and

without Concept of Sleep Transistor

Keerti Vyas1,3, Ginni Jain1,4,Vijendra K. Maurya1,5, Anu Mehra2,6
1ECE

Department, Geetanjali Institute of Technical Studies, Udaipur, Rajasthan, India,

2 Amity University, Noida , Uttar pradesh ,India
3kkvyas18@gmail.com, 4jain24.ginni@gmail.com,5maurya.vijendra@gmail.com,
6amehra@amity.edu

Abstract: In this paper, an analysis of different compressors are done with and
without the concept of sleep transistor. In VLSI design Compressor is an
important part of multiplier as these are used to reduce the space equipped by
partial products as the maximum space in a multiplication process is taken by
partial products. The compressor architecture given are exclusively based on
combination of three- level MCML gate with concept of sleep transistor as
these are generally suitable for improvement in speed, power consumption and
area the concept of sleep transistor is useful in reducing the leakage current.
16nm, CMOS technology were used for designing using Tanner EDA 14.1
version this results in up to 40% reduction of power consumption.
Keywords: MCML , sleep transistor, compressor, leakage current.

1 Introduction
In many digital signal processors and many microprocessors multiplication is a key
operation .Three steps are there basically there using Booth encoding partial products
are generated at the first than by using Wallace tree formed by using compressor
circuits number of partial products is reduced at the end summation of two rows is
done by using two input adder.
Most critical operation in multiplication is partial product reduction as the area
and performance of the multiplier is mainly influenced by it. As the three rows of
partial product is converted into two by compressor circuit so the name 3 to 2
compressor is given. Alternatively , the concept of sleep transistor can be understood
as a PMOS or NMOS transistor with elevated threshold voltage that connects a
permanent power supply to "virtual power supply". Transistor switching is controlled
by power management unit[5]. Here Several high order compressors with sleep
transistor concept, specifically 4to2, 5to2 and 7to2 compressors, have been designed
in an attempt to reduce leakage current and speed up compression operation.
In previously done work analysis of different architectures up to 7to2 compressor
was done in MCML[3].The CMOS complimentary implementation of compressor
architecture was basically done than these designs were compared with compressor
architectures that are designed using three level MCML gate. Results of this study
shows that compressor designed using these three input MCML gates designed are

better than other implementation in terms of speed , power consumption and silicon
area. figures below shows the earlier proposed 3 input XOR gate and carry generate
circuit using those the architecture was designed.

Fig 1. 3 input XOR gate without

sleep transistor[3].

Fig 2. Carry generate circuit without

sleep transistor[3].

Also as power reduction is an important part of any designing a MCML technology

was presented earlier that reduces the power consumption .Sleep mode and active
mode are two operating modes of that MCML technology. In series with supply
voltage (VDD) a sleep transistor is inserted .In the sleep mode this transistor is
disconnected from VDD to reduce the power consumption and in active mode regular
operation is performed as the transistor is connected to power supply. This will result
into minimization of leakage current[2].

Fig 3. Earlier proposed MCML circuit with sleep transistor.[2]

Here, we have combined the concept of sleep transistor with this compressor
architecture earlier proposed as a result along with increased speed and reduced silicon
area, power consumption and leakage current is also minimized. In section 2 the
compressor architectures used are described , results of simulation are presented in
section 3 and conclusion is given in section 4.

2. Architectures of Compressors
Same architecture of compressor as proposed in[3] is designed with and without sleep
transistor.3to2,4to2,5to2 and 7to2 compressor architectures are shown in this paper
and power consumption results are also compared for all in case of with and without
sleep transistor
3 to 2 compressor:
It is simply a full adder. Equation used for designing is:
X1 + X2 + X3 = Sum + 2 carry.

(1)

Realization of 3 to 2 compressor in MCML can be done using just two three - input
circuits these are XOR and circuit for carry generation given in figure 4 and 5
respectively. A sleep transistor is also added in design which leads to decrease in
leakage current.

Fig 4. Three input XOR gate used for

compressor designing.

Fig 5. MCML carry generation

circuit(CGEN) used for compressor
designing.

Fig 6. Architecture of 3 to 2 compressor

In comparison to earlier presented compressor architectures in [3] this architecture is

better in power consumption and delay as we have considered best compressor
architecture among those which are earlier designed than sleep transistor is added for
reduction of leakage current.
4 to 2 compressors
Equation used for designing is as shown:
X1 + X2 +X3 + X4 + C in = Sum + 2(Carry + C out)

(2)

Fig 7 . Architecture of 4 to 2 compressor

Four inputs X1 ,X2, X3 , X4 and sum weighted same ,while C OUT and carry are
higher by one bit order. The another architecture of compressor which is without
sleep transistor is also simulated.
5 to 2 Compressor :
There are five inputs X1, X2 ,X3, X4 and X5 and carry and sum are outputs.
Additionally, there are two more inputs these are carry bits Cin 1 and Cin2 also two
carry bits output Cout1 and Cout2. the equation used for designing is :
X5+ X4 +X3 +X2 +X1 + Cin2 + Cin1 = Sum+ 2(Carry+ Cout1+Cout2)

(3)

For this also we have implemented two designs. First one was designed without sleep
transistor and another with sleep transistor as shown in figure .The earlier designed
architectures are described in [3].

Fig 8. 5to 2 compressor architecture

7to 2 compressor
Seven inputs are there X1, X2 , X3, X4, X5, X6 and X7 outputs are carry and sum
.Additionally two input carry bits are there Cin1 and Cin2 and two carry bits at
output Cout1 & Cout2 .expression used for designing is :
X4 +X3 +X1+ X2+X5+X6+X7+ Cin1+Cin2 = Sum + 2 x (Carry+Cout1)+4Cout2

(4)

Fig 9. 7 to 2 compressor architecture

In this also the Cout1 and carry are higher by one bit order in weight than X inputs
and sum while Cout2 is 2 bit orders higher. Here also we will compare same
architecture as shown in [3] and with sleep transistor as given in this paper.

3. Results of Simulation
In MCML gates transistors were sized such that compressor is simulated in Tanner
EDA 14.1 version using CMOS 16nm technology. Tanner EDA belongs to Tanner
Research. It provides tools for designing of schematic and simulation of circuits ,
waveform analysis and layout editing, extraction of net list and design rule check
verification .The tables and waveforms display the changes obtained after insertion of
sleep transistor.

Waveform 1.7 to 2 compressor without

sleep transistor(with spikes).

Waveform 2.7 to 2 compressor

architecture with sleep transistor(without
spikes).

From the above given waveforms of 7 to 2 compressor with and without sleep
transistor we can observe that spikes appears during off state of output which aren't
there in case of architecture with sleep transistor this shows that leakage current is
also reduced.
Table 1. Power consumption of same architecture with and wit3hout sleep transistor.

Compres
sor
3 to 2
4 to 2
5 to 2
7 to 2

Without sleep
transistor(watt)
86.97
173.58
259.62
428.86

With sleep transistor

(watt)
47.26
90.47
136.67
220.66

Percentage
Difference
(%)
45.65
47.88
47.36
48.54

Table2 . Delay of same architecture with and without sleep transistor

Compre
ssor
3 to 2
4 to 2
5 to 2
7 to 2

Without sleep
transistor(ns)
20.44
24.27
31.059
25.672

With sleep transistor

(ns)
20.43
22.42
29.838
22.107

Table 1 shows that the same architecture of compressor consumes less power with
sleep transistor than the compressor without sleep transistor on an average it is about
47.35 % and the table 2 shows that delay is also reduced with sleep transistor concept.
The results are also presented in graphical format for making them more clear.

Power consumption (watt)

Power consumption by compressors with and without

sleep transistor concept
500
400
300
200
100
0

compressors without
sleep transistor
compressors with
sleep transistor

Fig 9 .Graph showing the power consumption comparison.

4. Conclusion and Future Scope

This paper presents analysis of different compressors architectures with and
without sleep transistor from this analysis we came to a conclusion that power
consumption done by same architecture with sleep transistor is less as compared to
without sleep transistors on average by 47.35% . Also the leakage current reduces in
case of architecture with sleep transistor which we can see by the waveform of 7 to 2
compressor as shown in result. While many key results for Compressor designing
have already been obtained, there are many more issues that remain to be addressed.
An important issue is how to further decrease the power consumption and delay.
Future work may also involves partitioning of large circuits and addition of concept of
sleep transistor in them too.

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