A Project Report On

Adaptive Equalizer Based On LMS Algorithm

Submitted to

Dr. P. Srihari
By

Aamodh.K (15VL01F)
Dokula Ashok Kumar (15VL08F)
Vikas Bhardwaj (15VL26F)
(M.Tech VLSI Design)

As a part of
VL832: DSP Architectures

Department of Electronics and Communication,

National Institute of Technology Karnataka
Surathkal
20th November 2015

Adaptive LMS Equalizer

ABSTRACT

This project deals with the design of an Adaptive Equalizer. The idea of the
equalizer is to build a filter in the receiver that counteracts the effect of the
channel. In essence, the equalizer must unscatter the impulse response. This
can be solved using different techniques.
In this project, we have implemented an Adaptive Equalizer using Least Mean
Square (LMS) Algorithm. The hardware description language used is Verilog.
Simulation and testing have been carried out in Xilinx ISE 13.1.

Department of E&C, NITK Surathkal

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Adaptive LMS Equalizer

CONTENTS

ABSTRACT

CONTENTS

ii

LIST OF FIGURES

iii

1. Problem Statement

2. Design Description

3. Design Approach

4. Simulation Results and Observations

REFERENCES

Department of E&C, NITK Surathkal

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Adaptive LMS Equalizer

LIST OF FIGURES
Figure 1: Block representation of LMS Equalizer

Figure 2: Circuit diagram of LMS equalizer

Figure 3: Simulation result with stepSize = 1

Figure 4: Simulation result with stepSize = 0

Department of E&C, NITK Surathkal

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Digital Signal Processing Architecture

2015

Problem Statement

What is LMS Equalizer?

An LMS adaptive equalizer is an equalization filter that automatically adapts
to time-varying properties of the communication channel.
It can be implemented to perform tap-weight adjustments periodically or
continually.
Periodic adjustments are accomplished by periodically transmitting a
training sequence of digital data known by the receiver

Project Features:

Minimized hardware (three delay elements reduced).

3 tap LMS adaptive filter.
8 bit input data.
Implemented in Verilog HDL.
FPGA compatible.
Simulation and testing software used: Xilinx ISE 13.1.

Department of E&C, NITK Surathkal

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Digital Signal Processing Architecture

2015

Design Desrciption
The block diagram in Figure 1 depicts all the signals of the LMS Equalizer that are
used for adaptive signal processing.

Figure 1: Block representation of LMS Equalizer

Input signals:
x : This is the 8 bit input signal to the LMS equalizer.
trainSeq : This is the 8 bit training sequence know by the receiver.
iteration : If iteration is 1, the initial FIR filter coefficients are used. Else, the
adapted coefficients are used for equalizaton.
stepSize : This is the adaptation step size.
rst : Clears the output y when HIGH. It is triggered on positive edge.
clk : External clock used to synchronize operations.

Output signal:
y : Output of the LMS equalizer

Department of E&C, NITK Surathkal

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Digital Signal Processing Architecture

2015

Design Approach

Figure 2 shows the circuit diagram of the Adaptive LMS Equalizer.

Figure 2: Circuit diagram of LMS equalizer

If delay elements are absent in edges a, b and c the output of coefficients
multiplier will be indeterminate because there is a conflict between the original
filter coefficients and adapted coefficients which will be indeterminate. In the
circuit of figure 2, this undesired condition in avoided by the usage of the
variable iteration. Thus,
Hardware usage is minimized as 3 less delay elements are required.
But, critical path is increased.
Thus, there is a tradeoff between area and speed.

Department of E&C, NITK Surathkal

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Digital Signal Processing Architecture

2015

Project implementation steps

A 3 tap FIR filter was designed.
Suitable signals were selected which act as the input signal and training
signal.
Adaptive step size was selected according to LMS algorithm.
The updation of filter coefficients was tracked.
The output waveform of the adaptive filter was observed for convergence
and divergence.
Synthesis reports RTL Schematic and Technology Schematic Reports were
generated.

Department of E&C, NITK Surathkal

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Digital Signal Processing Architecture

2015

Simulation Results and Observations

Figure 3: Simulation result with stepSize = 1

Figure 4: Simulation result when stepSize = 0

Observations:
In figure 3, as stepSize is 1, the output y is diverging and saturates at 0xF9.
Thus, the fail case of LMS algorithm is tested.
In figure 4, as stepSize is 0, the output is not always diverging. During
certain periods it is converging.

Department of E&C, NITK Surathkal

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Digital Signal Processing Architecture

2015

REFERENCES

1. P. Srihari, Course notes for VL832: DSP Architectures, National Institute of

Technology Karnataka at Surathkal, Odd semester, 2015.
2. B. Widrow, Video lectures on LMS Algorithm and Adaline, Stanford
University, 2012
3. D. Smalley, Equalization Concepts: A Tutorial, Texas Instruments application
report, October, 1994.

Department of E&C, NITK Surathkal

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