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Dac 8411
Dac 8411
DAC8411
www.ti.com
FEATURES
DESCRIPTION
Relative Accuracy:
1 LSB INL (DAC8311: 14-bit)
4 LSB INL (DAC8411: 16-bit)
microPower Operation: 80A at 2.0V
Power-Down: 0.5A at 5V, 0.1A at 2.0V
Wide Power Supply: +2.0V to +5.5V
Power-On Reset to Zero Scale
Straight Binary Data Format
Low Power Serial Interface with SchmittTriggered Inputs: Up to 50MHz
On-Chip Output Buffer Amplifier, Rail-to-Rail
Operation
SYNC Interrupt Facility
Extended Temperature Range 40C to +125C
Pin-Compatible Family in a Tiny, 6-Pin SC70
Package
The DAC8311 (14-bit) and DAC8411 (16-bit) are lowpower, single-channel, voltage output digital-toanalog converters (DAC). They provide excellent
linearity and minimize undesired code-to-code
transient voltages while offering an easy upgrade
path within a pin-compatible family. All devices use a
versatile, 3-wire serial interface that operates at clock
rates of up to 50MHz and is compatible with standard
SPI, QSPI, MICROWIRE, and digital signal
processor (DSP) interfaces.
234
APPLICATIONS
RELATED
DEVICES
Pin and
Function
Compatible
16-BIT
14-BIT
12-BIT
10-BIT
8-BIT
DAC8411
DAC8311
DAC7311
DAC6311
DAC5311
GND
Power-On
Reset
REF(+)
DAC
Register
14-/16-Bit DAC
Input Control
Logic
SYNC SCLK
Output
Buffer
Power-Down
Control Logic
VOUT
Resistor
Network
DIN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
All other trademarks are the property of their respective owners.
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT
MAXIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
DIFFERENTIAL
NONLINEARITY
(LSB)
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC8411
SC70-6
DCK
40C to 125C
D84
DAC8311
SC70-6
DCK
40C to 125C
D83
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
VALUE
UNIT
AVDD to GND
0.3 to +6
AVOUT to GND
40 to +125
65 to +150
+150
JA thermal impedance
(1)
250
C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
DAC8311
DAC8411
www.ti.com
ELECTRICAL CHARACTERISTICS
At AVDD = +2.0V to +5.5V, RL = 2k to GND, and CL = 200 pF to GND, unless otherwise noted.
DAC8411, DAC8311
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
12
0.5
UNIT
Relative accuracy
16
3.6V to 5V
Differential
nonlinearity
Resolution
DAC8311
Relative accuracy
14
Measured by the line passing through codes 120 and
16200
Differential
nonlinearity
Offset error
(2)
Full-scale error
LSB
LSB
0.125
LSB
0.05
mV
V/C
0.2
Gain error
LSB
Bits
Bits
mV
0.04
0.2
% of FSR
0.05
0.15
% of FSR
AVDD = +5V
0.5
AVDD = +2.0V
1.5
ppm of
FSR/C
0
RL = 2k, CL = 200 pF, AVDD = 5V, 1/4 scale to 3/4 scale
RL = 2M, CL = 470pF
Slew rate
Capacitive load stability
Code change glitch impulse
RL =
RL = 2k
1LSB change around major carry
RL = 2k, CL = 200pF, AVDD = 5V
Power-up time
10
12
0.7
V/s
470
pF
pF
0.5
nV-s
0.5
nV-s
17
mV
0.5
AVDD = +5V
50
mA
AVDD = +3V
20
mA
50
DC output impedance
Short-circuit current
1000
Digital feedthrough
Power-on glitch impulse
AVDD
AC PERFORMANCE
SNR
THD
SFDR
88
dB
66
dB
66
dB
66
dB
17
nV/Hz
110
nV/Hz
SINAD
DAC output noise density (4)
DAC output noise (5)
(1)
(2)
(3)
(4)
(5)
Vpp
Linearity calculated using a reduced code range of 485 to 64714 for 16-bit, and 120 to 16200 for 14-bit, output unloaded.
Straight line passing through codes 485 and 64714 for 16-bit, and 120 and 16200 for 14-bit, output unloaded.
Specified by design and characterization, not production tested.
For more details, see Figure 31.
For more details, see Figure 32.
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.3AVDD
0.1AVDD
Input current
VINL, input low voltage
VINH, input high voltage
0.7AVDD
0.9AVDD
Pin capacitance
1.5
pF
5.5
POWER REQUIREMENTS
AVDD
2.0
Normal mode
IDD
VINH = AVDD and VINL =
All power-down mode
GND, at mid-scale code
Normal mode
Power
dissipation
VINH = AVDD and VINL =
All power-down mode
GND, at mid-scale code
110
160
95
150
80
140
0.5
3.5
0.4
3.0
0.1
2.0
0.55
0.88
0.25
0.54
0.14
0.38
2.50
19.2
1.08
10.8
0.72
8.1
mW
TEMPERATURE RANGE
Specified performance
(6)
(7)
40
+125
DAC8311
DAC8411
www.ti.com
PIN CONFIGURATION
DCK PACKAGE
SC70-6
(TOP VIEW)
SYNC
VOUT
SCLK
GND
DIN
AVDD/VREF
NAME
DESCRIPTION
SYNC
Level-triggered control input (active low). This is the frame sychronization signal for the input data. When
SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th (DAC8411) or 16th (DAC8311) clock cycle,
unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt
and the write sequence is ignored by the DAC8x11. Refer to the DAC8311 and DAC8411 SYNC Interrupt
sections for more details.
SCLK
DIN
AVDD/VREF
GND
VOUT
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Serial Data Input. Data is clocked into the 24-bit (DAC8411) or 16-bit (DAC8311) input shift register on
the falling edge of the serial clock input.
Power Supply Input, +2.0V to 5.5V.
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
t1
SCLK
16
t8
t3
t4
t2
t7
SYNC
t10
t6
t5
DIN
DB15
DB0
DB15
(2)
All specifications at 40C to +125C, and AVDD = +2.0V to +5.5V, unless otherwise noted.
PARAMETER
t1
(3)
t2
t3
t4
t5
t6
t7
t8
t9
t10
(1)
(2)
(3)
TEST CONDITIONS
MIN
50
20
25
10
25
10
4.5
4.5
50
20
100
100
15
15
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
See 14-Bit Serial Write Operation timing diagram.
Maximum SCLK frequency is 50MHz at AVDD = 3.6V to 5.5V and 20MHz at AVDD = 2.0V to 3.6V.
DAC8311
DAC8411
www.ti.com
t1
SCLK
24
t8
t3
t4
t2
t7
SYNC
t10
t6
t5
DIN
DB23
DB0
DB23
(2)
All specifications at 40C to +125C, and AVDD = +2.0V to +5.5V, unless otherwise noted.
PARAMETER
t1
(3)
t2
t3
t4
t5
t6
t7
t8
t9
t10
(1)
(2)
(3)
TEST CONDITIONS
MIN
50
20
25
10
25
10
4.5
4.5
50
20
100
100
15
15
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
See 16-Bit Serial Write Operation timing diagram.
Maximum SCLK frequency is 50MHz at AVDD = 3.6V to 5.5V and 20MHz at AVDD = 2.0V to 3.6V.
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
6
4
2
0
-2
-4
-6
AVDD = 5V
LE (LSB)
LE (LSB)
-2
0.2
DLE (LSB)
DLE (LSB)
0.5
0
-0.5
0
8192
6
4
2
0
-2
-4
-6
2048
4096
6144
8192
10240 12288
Figure 1.
Figure 2.
14336 16384
AVDD = 5V
LE (LSB)
LE (LSB)
-0.1
0
AVDD = 5V
1
0
-1
-2
0.2
DLE (LSB)
1.0
DLE (LSB)
57344 65536
0.5
0
-0.5
0.1
0
-0.1
-0.2
-1.0
0
8192
57344 65536
2048
4096
6144
8192
10240 12288
14336 16384
Figure 3.
Figure 4.
6
4
2
0
-2
-4
-6
AVDD = 5V
LE (LSB)
LE (LSB)
0.1
-0.2
-1.0
AVDD = 5V
1
0
-1
-2
0.2
DLE (LSB)
1.0
DLE (LSB)
0
-1
1.0
0.5
0
-0.5
0.1
0
-0.1
-0.2
-1.0
0
AVDD = 5V
8192
57344 65536
2048
4096
6144
8192
10240 12288
Figure 5.
Figure 6.
14336 16384
DAC8311
DAC8411
www.ti.com
SOURCE CURRENT
AT POSITIVE RAIL
0.4
5.5
AVDD = 5V
0.3
0.2
0.1
0
-40 -25 -10
5.0
4.5
4.0
3.5
3.0
AVDD = 5V
DAC Loaded with FFFFh
2.5
5
20
35
50
65
80
95
110 125
Temperature (C)
Figure 7.
Figure 8.
OFFSET ERROR
vs TEMPERATURE
SINK CURRENT
AT NEGATIVE RAIL
10
10
0.6
AVDD = 5V
DAC Loaded with 0000h
AVDD = 5V
0.4
ISOURCE (mA)
0.6
0.2
0
-0.2
-0.4
-0.6
-40 -25 -10
0.4
0.2
0
5
20
35
50
65
80
95
110 125
Temperature (C)
6
ISINK (mA)
Figure 9.
Figure 10.
FULL-SCALE ERROR
vs TEMPERATURE
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
120
0.06
AVDD = 5.5V
AVDD = 5V
0.04
0.02
0
-0.02
-0.04
-0.06
-40 -25 -10
100
80
60
5
20
35
50
65
80
95
110 125
Temperature (C)
Figure 11.
Figure 12.
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
POWER-DOWN CURRENT
vs TEMPERATURE
140
1.6
AVDD = 5V
AVDD = 5V
130
120
110
100
-40 -25 -10
20
35
50
65
80
95
1.2
0.8
0.4
0
-40 -25 -10
110 125
Temperature (C)
35
50
65
80
95
110 125
Temperature (C)
Figure 13.
Figure 14.
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
POWER-SUPPLY CURRENT
HISTOGRAM
50
2000
SYNC Input (all other digital inputs = GND)
AVDD = 5.5V
45
40
1500
35
Sweep from
0V to 5.5V
Occurrences
20
1000
Sweep from
5.5V to 0V
30
25
20
15
500
10
5
VLOGIC (V)
-40
136
140
128
132
IDD (mA)
Figure 15.
Figure 16.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
94
-50
120
5.0
124
4.5
112
4.0
116
3.5
104
3.0
108
2.5
96
2.0
100
1.5
88
1.0
92
0.5
80
84
AVDD = 5V,
fS = 225kSPS,
-1dB FSR Digital Input,
Measurement Bandwidth = 20kHz
THD
92
SNR (dB)
THD (dB)
-60
2nd Harmonic
-70
90
88
-80
3rd Harmonic
86
-90
84
-100
0
10
fOUT (kHz)
fOUT (kHz)
Figure 17.
Figure 18.
DAC8311
DAC8411
www.ti.com
VOUT (500mV/div)
20
Gain (dB)
-40
-60
-80
-100
AVDD = 5V
Clock Feedthrough Impulse ~0.5nV-s
-120
-140
0
10
15
Time (500ns/div)
20
Frequency (kHz)
Figure 19.
Figure 20.
GLITCH ENERGY
5V, 16-BIT, 1LSB STEP, RISING EDGE
GLITCH ENERGY
5V, 16-BIT, 1LSB STEP, FALLING EDGE
Clock
Feedthrough
~0.5nV-s
AVDD = 5V
From Code: 8000h
To Code: 7FFFh
VOUT (100mV/div)
VOUT (100mV/div)
AVDD = 5V
From Code: 7FFFh
To Code: 8000h
Clock
Feedthrough
~0.5nV-s
Glitch Impulse
< 0.5nV-s
Glitch Impulse
< 0.5nV-s
Figure 22.
GLITCH ENERGY
5V, 14-BIT, 1LSB STEP, RISING EDGE
GLITCH ENERGY
5V, 14-BIT, 1LSB STEP, FALLING EDGE
Glitch Impulse
< 0.5nV-s
Clock
Feedthrough
~0.5nV-s
AVDD = 5V
From Code: 2000h
To Code: 2001h
VOUT (100mV/div)
Time (5ms/div)
Figure 21.
VOUT (100mV/div)
Time (5ms/div)
AVDD = 5V
From Code: 2001h
To Code: 2000h
Clock
Feedthrough
~0.5nV-s
Glitch Impulse
< 0.5nV-s
Time (5ms/div)
Time (5ms/div)
Figure 23.
Figure 24.
11
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
AVDD = 5V
From Code: 0000h
To Code: FFFFh
AVDD = 5V
From Code: FFFFh
To Code: 0000h
Rising Edge
1V/div
Zoomed Rising Edge
100mV/div
Falling Edge
1V/div
Time (2ms/div)
Figure 25.
Figure 26.
Falling
Edge
1V/div
Rising
Edge
1V/div
AVDD = 5V
From Code: 4000h
To Code: C000h
Trigger
Pulse
5V/div
Trigger
Pulse
5V/div
Time (2ms/div)
Figure 28.
POWER-ON RESET TO 0V
POWER-ON GLITCH
POWER-OFF GLITCH
17mV
AVDD (2V/div)
AVDD = 5V
DAC = Zero Scale
Load = 200pF || 10kW
AVDD = 5V
DAC = Zero Scale
Load = 200pF || 10kW
VOUT (20mV/div)
AVDD (2V/div)
VOUT (20mV/div)
12
Time (2ms/div)
Figure 27.
Time (5ms/div)
Time (10ms/div)
Figure 29.
Figure 30.
DAC8311
DAC8411
www.ti.com
300
AVDD = 5V,
DAC = Midscale, No Load
AVDD = 5V
VNOISE (1mV/div)
Noise (nV/Hz)
250
200
150
Midscale
100
3mVPP
Zero Scale
Full Scale
50
0
10
100
1k
10k
Time (2s/div)
100k
Frequency (Hz)
Figure 31.
Figure 32.
POWER-SUPPLY CURRENT
vs POWER-SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs POWER-SUPPLY VOLTAGE
0.4
120
110
100
90
80
0.3
0.2
0.1
70
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
AVDD (V)
AVDD (V)
Figure 33.
Figure 34.
4.5
5.0
5.5
13
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
POWER-SUPPLY CURRENT
vs TEMPERATURE
100
140
AVDD = 3.6V
AVDD = 3.6V
90
80
70
60
50
0
130
120
110
100
90
80
-40 -25 -10
65
80
Figure 36.
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
POWER-DOWN CURRENT
vs TEMPERATURE
95
110 125
95
110 125
1.2
AVDD = 3.6V
50
Figure 35.
300
0.8
0.4
Sweep from
3.6V to 0V
0
-40 -25 -10
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
20
35
50
65
80
Temperature (C)
VLOGIC (V)
Figure 37.
Figure 38.
SOURCE CURRENT
AT POSITIVE RAIL
SINK CURRENT
AT NEGATIVE RAIL
3.7
0.6
AVDD = 3.6V
DAC Loaded with 0000h
3.5
35
Temperature (C)
1200
3.3
3.1
2.9
2.7
AVDD = 3.6V
DAC Loaded with FFFFh
2.5
0
0.4
0.2
0
6
10
ISOURCE (mA)
10
ISINK (mA)
Figure 39.
14
20
Figure 40.
DAC8311
DAC8411
www.ti.com
AVDD = 3.6V
40
Occurrences
35
30
25
20
15
10
5
126
130
118
122
110
114
102
106
94
98
86
90
78
82
70
74
0
IDD (mA)
Figure 41.
15
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
6
4
2
0
-2
-4
-6
AVDD = 2.7V
LE (LSB)
LE (LSB)
-2
0.2
DLE (LSB)
DLE (LSB)
0.5
0
-0.5
0
8192
6
4
2
0
-2
-4
-6
2048
4096
6144
8192
10240 12288
Figure 42.
Figure 43.
14336 16384
AVDD = 2.7V
LE (LSB)
LE (LSB)
-0.1
0
AVDD = 2.7V
1
0
-1
-2
0.2
DLE (LSB)
1.0
DLE (LSB)
57344 65536
0.5
0
-0.5
0.1
0
-0.1
-0.2
-1.0
0
8192
57344 65536
2048
4096
6144
8192
10240 12288
14336 16384
Figure 44.
Figure 45.
6
4
2
0
-2
-4
-6
AVDD = 2.7V
LE (LSB)
LE (LSB)
0.1
-0.2
-1.0
AVDD = 2.7V
1
0
-1
-2
0.2
DLE (LSB)
1.0
DLE (LSB)
0
-1
1.0
0.5
0
-0.5
0.1
0
-0.1
-0.2
-1.0
0
16
AVDD = 2.7V
8192
57344 65536
2048
4096
6144
8192
10240 12288
Figure 46.
Figure 47.
14336 16384
DAC8311
DAC8411
www.ti.com
SOURCE CURRENT
AT POSITIVE RAIL
0.4
2.8
AVDD = 2.7V
0.3
0.2
0.1
0
-40 -25 -10
2.6
2.4
2.2
AVDD = 2.7V
DAC Loaded with FFFFh
2.0
5
20
35
50
65
80
95
110 125
Temperature (C)
Figure 48.
Figure 49.
OFFSET ERROR
vs TEMPERATURE
SINK CURRENT
AT NEGATIVE RAIL
10
10
0.6
AVDD = 2.7V
DAC Loaded with 0000h
AVDD = 2.7V
0.4
ISOURCE (mA)
0.6
0.2
0
-0.2
-0.4
-0.6
-40 -25 -10
0.4
0.2
0
5
20
35
50
65
80
95
110 125
Temperature (C)
6
ISINK (mA)
Figure 50.
Figure 51.
FULL-SCALE ERROR
vs TEMPERATURE
POWER-SUPPLY CURRENT
vs DIGITAL INPUT CODE
100
0.06
AVDD = 2.7V
AVDD = 2.7V
0.04
0.02
0
-0.02
-0.04
-0.06
-40 -25 -10
90
80
70
60
50
5
20
35
50
65
80
95
110 125
Temperature (C)
Figure 52.
Figure 53.
17
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
POWER-DOWN CURRENT
vs TEMPERATURE
120
1.0
AVDD = 2.7V
110
AVDD = 2.7V
100
90
80
70
-40 -25 -10
20
35
50
65
80
95
0.8
0.6
0.4
0.2
0
-40 -25 -10
110 125
20
Temperature (C)
50
65
80
Figure 54.
Figure 55.
POWER-SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
POWER-SUPPLY CURRENT
HISTOGRAM
50
800
SYNC Input (all other digital inputs = GND)
95
110 125
AVDD = 2.7V
45
40
600
35
Occurrences
35
Temperature (C)
Sweep from
0V to 2.7V
400
Sweep from
2.7V to 0V
30
25
20
15
200
10
5
VLOGIC (V)
104
100
96
92
IDD (mA)
Figure 56.
Figure 57.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
88
-20
86
THD
SNR (dB)
-40
THD (dB)
88
3.0
80
2.5
84
2.0
76
1.5
72
1.0
68
0.5
60
64
-60
84
2nd Harmonic
82
-80
3rd Harmonic
80
-100
0
fOUT (kHz)
fOUT (kHz)
Figure 58.
18
Figure 59.
DAC8311
DAC8411
www.ti.com
VOUT (500mV/div)
20
Gain (dB)
-40
-60
-80
-100
AVDD = 2.7V
Clock Feedthrough Impulse ~0.4nV-s
-120
-140
0
10
15
Time (5ms/div)
20
Frequency (kHz)
Figure 60.
Figure 61.
GLITCH ENERGY
2.7V, 16-BIT, 1LSB STEP, RISING EDGE
GLITCH ENERGY
2.7V, 16-BIT, 1LSB STEP, FALLING EDGE
AVDD = 2.7V
From Code: 8000h
To Code: 7FFFh
Glitch Impulse
< 0.3nV-s
Clock
Feedthrough
~0.4nV-s
VOUT (100mV/div)
VOUT (100mV/div)
AVDD = 2.7V
From Code: 7FFFh
To Code: 8000h
Glitch Impulse
< 0.3nV-s
Clock
Feedthrough
~0.4nV-s
Time (5ms/div)
Time (5ms/div)
Figure 62.
Figure 63.
GLITCH ENERGY
2.7V, 14-BIT, 1LSB STEP, RISING EDGE
GLITCH ENERGY
2.7V, 14-BIT, 1LSB STEP, FALLING EDGE
AVDD = 2.7V
From Code: 2001h
To Code: 2000h
Glitch Impulse
< 0.3nV-s
Clock
Feedthrough
~0.4nV-s
VOUT (100mV/div)
VOUT (100mV/div)
AVDD = 2.7V
From Code: 2000h
To Code: 2001h
Clock
Feedthrough
~0.4nV-s
Glitch Impulse
< 0.3nV-s
Time (5ms/div)
Time (5ms/div)
Figure 64.
Figure 65.
19
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
AVDD = 2.7V
From Code: 0000h
To Code: FFFFh
AVDD = 2.7V
From Code: FFFFh
To Code: 0000h
Falling Edge
1V/div
Rising Edge
1V/div
Zoomed Rising Edge
100mV/div
Trigger
Pulse
2.7V/div
Time (2ms/div)
Figure 66.
Figure 67.
AVDD = 2.7V
From Code: 4000h
To Code: C000h
AVDD = 2.7V
From Code: C000h
To Code: 4000h
Falling
Edge
1V/div
Rising
Edge
1V/div
Zoomed Rising Edge
100mV/div
Trigger
Pulse
2.7V/div
Trigger
Pulse
2.7V/div
Time (2ms/div)
Figure 69.
POWER-ON RESET TO 0V
POWER-ON GLITCH
POWER-OFF GLITCH
17mV
AVDD (1V/div)
AVDD = 2.7V
DAC = Zero Scale
Load = 200pF || 10kW
AVDD = 2.7V
DAC = Zero Scale
Load = 200pF || 10kW
VOUT (20mV/div)
AVDD (1V/div)
VOUT (20mV/div)
20
Time (2ms/div)
Figure 68.
Time (5ms/div)
Time (10ms/div)
Figure 70.
Figure 71.
DAC8311
DAC8411
www.ti.com
THEORY OF OPERATION
DAC SECTION
VREF
RDIVIDER
VREF
2
R
AVDD
To Output
Amplifier
R
REF (+)
DAC Register
Resistor String
VOUT
Output
Amplifier
GND
RESISTOR STRING
The resistor string section is shown in Figure 73. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
tested monotonic because it is a string of resistors.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output which gives an output
range of 0V to AVDD. It is capable of driving a load of
2k in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen in
the Typical Characteristics section for each device.
The slew rate is 0.7V/s with a half-scale settling time
of typically 6s with the output unloaded.
21
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
DB14
PD1
PD0
DB0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CLK
SYNC
DIN
DB15
DB0
DB15
DB0
22
DAC8311
DAC8411
www.ti.com
The SYNC line may be brought high after the 18th bit
is clocked in because the last six bits are don't care.
PD0
D1
5
D1
4
D1
3
D1
2
D1
1
D1
0
D9
D8
D7
D6
D5
D4
D3
D2
DB
7
DB
6
DB
5
D1
D0
18
DB
0
X
24
18
24
SYNC
DIN
DB23
DB6
DB5
DB0
DB23
DB6
DB5
DB0
23
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
VOUT
POWER-DOWN MODES
The DAC8x11 contains four separate modes of
operation. These modes are programmable by setting
two bits (PD1 and PD0) in the control register.
Table 4 shows how the state of the bits corresponds
to the mode of operation of the device.
Power-down
Circuitry
Resistor
Network
PD0
OPERATING MODE
Output 1k to GND
High-Z
Normal Operation
Power-Down Modes
24
DAC8311
DAC8411
www.ti.com
APPLICATION INFORMATION
USING THE REF5050 AS A POWER SUPPLY
FOR THE DAC8x11
As a result of the extremely low supply current
required by the DAC8x11, an alternative option is to
use a REF5050 +5V precision voltage reference to
supply the required voltage to the part, as shown in
Figure 77. This option is especially useful if the power
supply is too noisy or if the system supply voltages
are at some value other than 5V. The REF5050
outputs a steady supply voltage for the DAC8x11. If
the REF5050 is used, the current needed to supply
DAC8x11 is typically 110A at 5V, with no load on
the output of the DAC. When the DAC output is
loaded, the REF5050 also needs to supply the
current to the load. The total current required (with a
5k load on the DAC output) is:
110A + (5V/5k) = 1.11mA
The load regulation of the REF5050 is typically
0.002%/mA, resulting in an error of 90V for the
1.11mA current drawn from it. This value corresponds
to a 1.1LSB error at 16bit (DAC8411).
AVDD
R1 ) R 2
2Dn
R1
* AV DD
R2
R1
(1)
Where:
n = resolution in bits; either 14 (DAC8311) or 16
(DAC8411).
D = the input code in decimal; either 0 to 16,383
(DAC8311) or 0 to 65,535 (DAC8411).
With AVDD = 5V, R1 = R2 = 10k:
+5.5V
REF5050
1mF
(2)
110mA
SYNC
SCLK
V O + 10 n D *5V
2
+5V
Three-Wire
Serial
Interface
VOUT = 0V to 5V
R2
10kW
+5V
DAC8x11
DIN
+5.5V
R1
10kW
OPA211
VOUT
AVDD
10mF
5V
DAC8x11
- 5.5V
0.1mF
Three-Wire
Serial
Interface
25
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
MICROPROCESSOR INTERFACING
DAC8x11(1)
Microwire
CS
SYNC
SK
SCLK
SO
DIN
80C51/80L51(1)
DAC8x11(1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
68HC11(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
26
DAC8311
DAC8411
www.ti.com
LAYOUT
A precision analog component requires careful layout,
adequate bypassing, and clean, well-regulated power
supplies.
The DAC8x11 offers single-supply operation; it will
often be used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal
processors. The more digital logic present in the
design and the higher the switching speed, the more
difficult it will be to achieve good performance from
the converter.
Because of the single ground pin of the DAC8x11, all
return currents, including digital and analog return
currents, must flow through the GND pin. Ideally,
GND would be connected directly to an analog
ground plane. This plane would be separate from the
ground connection for the digital components until
they were connected at the power entry point of the
system.
27
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
PARAMETER DEFINITIONS
With the increased complexity of many different
specifications listed in product data sheets, this
section summarizes selected specifications related to
digital-to-analog converters.
STATIC PERFORMANCE
Static performance parameters are specifications
such as differential nonlinearity (DNL) or integral
nonlinearity (INL). These are dc specifications and
provide information on the accuracy of the DAC. They
are most important in applications where the signal
changes slowly and accuracy is required.
Resolution
Generally, the DAC resolution can be expressed in
different forms. Specifications such as IEC 60748-4
recognize the numerical, analog, and relative
resolution. The numerical resolution is defined as the
number of digits in the chosen numbering system
necessary to express the total number of steps of the
transfer characteristic, where a step represents both
a digital input code and the corresponding discrete
analogue output value. The most commonly-used
definition of resolution provided in data sheets is the
numerical resolution expressed in bits.
Least Significant Bit (LSB)
The least significant bit (LSB) is defined as the
smallest value in a binary coded system. The value of
the LSB can be calculated by dividing the full-scale
output voltage by 2n, where n is the resolution of the
converter.
Most Significant Bit (MSB)
Full-Scale Error
Full-scale error is defined as the deviation of the real
full-scale output voltage from the ideal output voltage
while the DAC register is loaded with the full-scale
code (0xFFFF). Ideally, the output should be VDD 1
LSB. The full-scale error is expressed in percent of
full-scale range (%FSR).
Offset Error
Offset error is defined as the difference between
actual output voltage and the ideal output voltage in
the linear region of the transfer function. This
difference is calculated by using a straight line
defined by two codes (for example, for 16-bit
resolution, codes 485 and 64714). Since the offset
error is defined by a straight line, it can have a
negative or positve value. Offset error is measured in
mV.
Zero-Code Error
Zero-code error is defined as the DAC output voltage,
when all '0's are loaded into the DAC register. Zeroscale error is a measure of the difference between
actual output voltage and ideal output voltage (0V). It
is expressed in mV. It is primarily caused by offsets in
the output amplifier.
Gain Error
Gain error is defined as the deviation in the slope of
the real DAC transfer characteristic from the ideal
transfer function. Gain error is expressed as a
percentage of full-scale range (%FSR).
Zero-code error drift is defined as the change in zerocode error with a change in temperature. Zero-code
error drift is expressed in V/C.
Full-scale error drift is defined as the change in fullscale error with a change in temperature. Full-scale
error drift is expressed in units of %FSR/C.
DAC8311
DAC8411
www.ti.com
Digital Feedthrough
Channel-to-Channel DC Crosstalk
Channel-to-channel dc crosstalk is defined as the dc
change in the output level of one DAC channel in
response to a change in the output of another DAC
channel. It is measured with a full-scale output
change on one DAC channel while monitoring
another DAC channel remains at midscale. It is
expressed in LSB.
Channel-to-Channel AC Crosstalk
Slew Rate
DYNAMIC PERFORMANCE
SR = max
DVOUT(t)
Dt
(3)
29
DAC8311
DAC8411
SBAS439B AUGUST 2008 REVISED MAY 2013
www.ti.com
30
DAC8311
DAC8411
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August, 2011) to Revision B
Page
Page
Changed specifications and test conditions for input low voltage parameter ....................................................................... 4
Changed specifications and test conditions for input high voltage parameter ..................................................................... 4
31
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
DAC8311IDCKR
ACTIVE
SC70
DCK
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D83
DAC8311IDCKRG4
ACTIVE
SC70
DCK
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D83
DAC8311IDCKT
ACTIVE
SC70
DCK
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D83
DAC8411IDCKR
ACTIVE
SC70
DCK
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D84
DAC8411IDCKRG4
ACTIVE
SC70
DCK
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D84
DAC8411IDCKT
ACTIVE
SC70
DCK
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D84
DAC8411IDCKTG4
ACTIVE
SC70
DCK
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
D84
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
www.ti.com
10-Jun-2014
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
8-May-2013
Device
DAC8311IDCKR
SC70
DCK
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
177.8
9.7
2.3
2.52
1.2
4.0
8.0
Q3
DAC8311IDCKT
SC70
DCK
250
177.8
9.7
2.3
2.52
1.2
4.0
8.0
Q3
DAC8411IDCKR
SC70
DCK
3000
177.8
9.7
2.3
2.52
1.2
4.0
8.0
Q3
DAC8411IDCKT
SC70
DCK
250
177.8
9.7
2.3
2.52
1.2
4.0
8.0
Q3
Pack Materials-Page 1
8-May-2013
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC8311IDCKR
SC70
DCK
3000
184.0
184.0
50.0
DAC8311IDCKT
SC70
DCK
250
184.0
184.0
50.0
DAC8411IDCKR
SC70
DCK
3000
184.0
184.0
50.0
DAC8411IDCKT
SC70
DCK
250
184.0
184.0
50.0
Pack Materials-Page 2
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