8085 MICROPROCESSOR

1.1 Microprocessor:
A Microprocessor is a programmable integrated device that has computational, decision making
and storing/retrieving capabilities.
1.2 Architecture of 8085:
The microprocessor is a programmable logic device, designed with registers, flip-flops, and timing
elements to manipulate data and to communicate with the peripherals based on the set of
instructions given to it. This process of data manipulation and communication is determined by
the logic design of the microprocessor, called architecture.
The 8085 microprocessor is an 8-bit general purpose processor capable of addressing 64K byte
location/devices. Its data bus is 8-bit wide and address bus is 16-bits wide. The device has forty
pins, requires a +5V single power supply, and can operate with a 3-MHz single phase clock. The
8085A-2 version can operate at the maximum frequency of 5 MHz. The 8085 is an enhanced
version of its predecessor, the 8080A. The 8085 instruction set is upward compatible with that of
8080A, meaning that the 8085 instruction set includes all the 8080A instructions plus some
additional ones. Programs written for 8080A can be executed by the 8085, but the 8085 and
8080 are not pin-compatible.
The internal architecture of 8085 is capable of doing the following operations
(i)

store 8-bit data

(ii)

perform arithmetic and logical operations

(iii)

test for conditions

(iv)

sequence the execution of instructions

(v) store data temporarily during execution in the defined R/W memory locations called stack
To perform these operations, the microprocessor requires registers, an arithmetic/logic unit (ALU)
and internal buses. Fig. 1 shows the internal architecture of 8085.

1
Fig. 1 8085 Internal architecture

Registers:
The 8085 has six general purpose registers to store 8-bit data during a program execution. These
registers are identified as A, B, C, D, E, H, L. The register A is called accumulator that holds the
results of arithmetic/logical operations. The registers B, C, D, E, H, L can be combined as register
pairs BC, DE, HL to perform some 16-bit operations and can also be used as data pointers. The
Temporary Register(8) is used internally by the processor and is not available for the
programmer. Similarly the registers W(8) & Z(8) are used to hold 8-bit data during program
execution of some instructions and are not available to the programmer.
Arithmetic and Logic unit (ALU):
The ALU is a hardware unit built with combinational and sequential circuits for performing
arithmetic and logical operations. Manipulations on the data is done in this unit with the help of
instructions.
Flag:
The flag is a 8-bit register. Out of 8 Bits, only 5 Bits are defined and are called Flags, each flag is
a Flip-Flop. The value each Flag gets altered based on the result of an Arithmetic / Logical
operation. The microprocessor uses the flag to perform testing for data conditions. The flags have
critical importance in decision-making process of the microprocessor. The conditions (set or rest)
of the flags can be tested through software instructions.
D7

D6

D5

D4

D3

D2

D1

D0

AC

CY

- Un-Defined.
Carry Flag (CY)

Parity Flag (P)

gets set to 1, if there exists a bit-out from D7 or into D7

during an arithmetic operation. A 0 otherwise.
gets set to 1, if the result of an arithmetic operation has
even number of 1s. A 0 otherwise.

Auxillary Carry Flag (AC)

gets set to 1, if there exists a bit movement from D3 to D4

or from D4 to D3. A 0 otherwise. The flag is used only
internally for BCD operations and is not available for the
programmer to change the sequence of program with a jump
instruction.

Zero Flag (Z)

gets set to 1, if the result of an arithmetic / logical operation

is zero. A 0 otherwise.

Sign Flag (S)

Example: ADD B

gets set to 1, if the MSB of the result is 1. A 0 otherwise.

Let A=37H, B=F4H

After addition A=12B; CY=1, P=1, AC=0, Z=0, S=0

Program Counter (PC):
The program counter is a 16-bit register that sequence the execution of instructions. The function
of the program counter is to point to the memory address from which the next byte is to be
fetched. The program counter gets incremented by one for every fetch operation.

Stack Pointer (SP):

The stack pointer is also a 16-bit register that points to beginning of the stack or top of the stack.
It is used for storing the data temporarily during execution in the defined R/W memory locations
called the stack.
Buses:
The buses are bunch of wires meant for carrying information between various parts of the
microprocessor.
1.3 Pinout and Signals of 8085 microprocessor:

Fig. 2 The 8085 Microprocessor Pinout and signals

Fig. 2 shows the pinout and signals of 8085 microprocessor. All these signals can be classified
into six groups: (1) Power supply and frequency (2) Address bus (3) Data bus (3) Control and
status (4) externally initiated and (5) Serial I/O Port signals.
Power Supply & frequency:

VCC: +5V Power Supply (Input pin)

VSS: Ground Reference (Input pin)

X1, X2: A crystal is connected at these two pins (Input Pins). The frequency is internally
divided by 2; therefore, to operate a system at 3MHz, the crystal should have a
frequency of 6 MHz.
fclk

1
fcrystal
2

CLK OUT: Clock Out (Output pin). This signal can be used as the system clock for other
devices.

Address Bus:
The address bus is 16-Bit and hence the 8085 can address 64K Byte locations. It is Unidirectional
and its lower 8 lines are multiplexed with Data lines (AD7 AD0). Its upper 8 lines are named as
A15 A8.

Data Bus:
It is Bi-Directional. It is multiplexed with address bus and are named as AD7 AD0. Multiplexing
reduces the number of pins in the processor. During the earlier part of the machine cycle, these
lines are used as address bus and data bus during the later part of the machine cycle. However,
the low-order address bus can be separated from these signals by using a latch.
Control & Status Signals:
This group of signals includes two control signals ( RD &

WR ), three status signals (IO/ M , S1

and S0) to identify the nature of the operation, and one special signal (ALE) to indicate the
beginning of the operation.
ALE Address Latch Enable: This is a positive edge going pulse generated every time the
8085 begins an operation (machine cycle); it indicates that the bits on AD7-AD0 are
address bits. This signal is used primarily to latch the low-order address lines from the
multiplexed bus and generate a separate set of 8 address lines, AD7-AD0.

RD - Read: This is a Read control signal (Active Low output pin). This signal indicates that
the selected I/O or memory device is to be read and data are available on the data bus.

WR - Write: This is a Write control signal (Active Low output pin). This signal indicates
that data on data bus are to be written into a selected memory or I/O location.
IO/ M : This is a status signal used to differentiate between I/O & memory operations.
When it is high, it indicates an I/O operation; when it is low, it indicates it is a memory
operation. This signal is combined with RD &

WR to generate IOR , IOW , MEMR &

MEMW control signals.

S1 & S0: These Status signals, similar to IO/ M , can identify various operations.

Machine
Cycle

Status
IO/

S1

S0

Memory Write

I/O Write

Memory Read

I/O Read

Opcode Fetch

Halt

Hold

Reset

Interrupt
Acknowledge

Control Signals

WR =0
WR =0
RD =0
RD =0
RD =0
INTA =0

RD , WR =Z and INTA =1

Note: Z=Tri-state (High Impedance) X=Unspecified

Externally Initiated Signals:
INTR:

Interrupt Request: (Input) This is used as a general purpose interrupt. The

interrupt signal is initiated through external Hardware.

INTA :

Interrupt Acknowledge: (Output) This used to acknowledge an interrupt.

RST 7.5:

Restart Interrupts: (Input) These vectored and Maskable interrupts. They transfer

RST 6.5:

program control to specific memory location. They have higher priority than

RST 5.5:

INTR interrupt. Among these Three, the priority order is 7.5, 6.5 & 5.5

TRAP:

This is a nonmaskable interrupt and has the highest priority.

HOLD:

It indicates that a peripheral such as a DMA controller is requesting the use of the
address & data buses.

HLDA:

Hold Acknowledge: This signal acknowledge the HOLD request.

READY:

This signal is used to delay the microprocessor Read or Write cycles until a slowresponding peripheral is ready to send or accept data. When this signal goes low,
the microprocessor waits for an integral number of clock cycles until it goes high.

RESETIN :

It is an active low input pin to reset the processor. This pin when grounded
(applied 0), brings the processor to its initial state i.e., all its registers are
initialized to zero, its buses are tri-stated (high impedance state) and all its
maskable interrupts are disabled.

RESET OUT:

It is an active high output pin. This signal indicates that the MPU is being reset.
This can be used to reset the other devices or the peripherals associated with the
processor.

Serial I/O port:

The 8085 has two signals to implement the serial transmission: SID (Serial Input Data) and SOD
(Serial Output Data).
1.4 Interrupts:
Interrupt is a form of disturbance to the processor that may come to it either though hardware or
by means of software. Based on this the interrupts may be classified as Hardware interrupts and
Software interrupts.

Interrupt
Enable
(IE)
Flip-Flop

TRAP
RST 7.5
RST 6.5
RST 5.5

8085
p

INT 0

8085
MicroprocessorAD7

INT 1

Data Bus

INT 2

AD0

External
Device

D0 - D 7

INT 3
INT 4

INTR
INTR

INTR
INTR

INT 5
INT 6

INTA
INTA
INTA

INTA

INT 7

Fig. 3 Interface diagram of 8085 interrupts

1.4.1 8085 Interrupt process (Interrupt handling mechanism):
The 8085 interrupt process is as follows:
1. The interrupt process should be enabled by writing the instruction EI (Enable Interrupt) in
the main program. The instruction EI sets the Interrupt Enable flip-flop. The instruction DI
resets the flip-flop and disables the interrupt process.
2. When

the

microprocessor

is

executing

program, it checks the INTR line during the

execution of each instruction.
3. If the line INTR is high and the interrupt is
enabled, the microprocessor completes the
current

instruction,

disables

the

Interrupt

Enable flip-flop and sends a signal called

INTA

(Interrupt acknowledge). The processor cannot

accept

any

interrupt

requests

until

the

Interrupt Enable flip-flop is enabled again.

4. The signal INTA is used to insert the interrupt
type number in the form of opcode by an
external hardware.
5. When the microprocessor receives an type

Fig. 4 Interrupt Handling mechanism

number (opcode), it saves the memory address of the next instruction on the stack.
6. Using the type number, the processor calculates the address of the Interrupt Service
Routine (ISR) and enters into the ISR to perform the task.
7. The ISR should include the instruction EI to enable the interrupt again.
8. At the end of the subroutine, the RET instruction retrieves the memory address where the
program was interrupted and continues the execution.
The interrupt processing by 8085 is illustrated in Fig. 4.

1.4.2 Hardware Interrupts:

Interrupt is a process where an external device can get the attention of the processor. There are
five hardware interrupts viz., TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
Maskable and Non-Maskable Interrupts:
The 8085 interrupt process can be controlled by the Interrupt Enable flip-flop, which is internal to
the processor and can be set or reset by using software instructions. If the flip-flop is enabled
and the input to the interrupt signal INTR / RST 7.5 / RST 6.5 / RST 6.5 goes high, the
microprocessor is interrupted. These are maskable interrupts and can be disabled. The 8085 has
a non-maskable interrupt i.e., TRAP which is of high priority. This can be noticed from the Fig. 5.
The TRAP has the highest priority, followed by RST 7.5, RST 6.5, RST 5.5 and INTR.

Fig. 5 The 8085 Interrupts and Vector locations

Vectored and Non-Vectored Interrupts:
The interrupts TRAP, RST 7.5, RST 6.5, RST 5.5 are automatically vectored (transferred) to
specific locations, corresponding ISR address, without any external hardware. They do not
require

INTA signal; the necessary hardware is already implemented inside the 8085. The

interrupts and their call locations are as follows:

Interrupt

Call location

TRAP

0024H

RST 7.5

003CH

RST 6.5

0034H

RST 5.5

002CH

The INTR is a non-vectored interrupt, as the vector address is supplied by an external device on
the receipt of INTA signal from the processor.

Edge and Level Triggered interrupts:

The interrupts are sensitive to different types of triggering as detailed below:

RST 7.5: This is positive-edge sensitive and can be triggered with a short pulse. The
request is stored internally by the D flip-flop (Fig. 5) until the microprocessor responds to
the request or until it is cleared Reset or the bit D4 in SIM instruction.

RST 6.5, RST 5.5 and INTR: These interrupts are level sensitive, meaning that the
triggering level should be on until the microprocessor completes the execution of the
current instruction.

1.4.3 Enabling and Disabling 8085 interrupts:

The interrupts, RST 7.5, RST 6.5 and RST 5.5, of 8085 can be enabled or disabled individually
using the instruction SIM.
SIM instruction:
SIM is a 1-bye instruction known as Set Interrupt Mask and can be used for three different
functions

D7

D6

D5

D4

D3

D2

D1

D0

SOD

SDE

XXX

R7.5

MSE

M7.5

M.6.5

M.5.5

One of the functions is to set mask for RST 7.5, 6.5 and 5.5 interrupts using the bits D2 to
D1 i.e., M7.5, M6.5 and M5.5 respectively. This instruction reads the content of the
accumulator and enables or disables the interrupts according to the content of the
accumulator. Bit D3 is a control bit and should be 1 (one) for the bits D0, D1 and D2 to be
effective. Logic 0 (zero) on D0, D1 and D2 will enable the corresponding interrupts and
logic 1 (one) will disable the interrupts.

The second function is to reset RST 7.5 flip-flop (Fig. 5). Bit D4 is additional control for
RST 7.5. If D4=1, then RST 7.5 is reset. This is used to override RST 7.5 without servicing
it.

The third function is to implement serial I/O. Bits D7 and D6 of the accumulator are used
for serial I/O and do not affect the interrupts. Bit D6=1, enables the serial I/O and bit D7
is used to transmit the bits.

RIM instruction:
Because there are several interrupt lines, when one interrupt is being served, other interrupts
may occur and remain pending. RIM instruction helps in sensing the pending interrupts.
RIM is a 1-bye instruction known as Read Interrupt Mask used to do the following functions:

D7

D6

D5

D4

D3

D2

D1

D0

SID

I7.5

I6.5

I5.5

IE

M7.5

M.6.5

M.5.5

To read interrupt masks. This instruction loads the accumulator with 8-bits indicating the
current status of the interrupt masks M7.5, M6.5 and M5.5.

To identify pending interrupts. Bits D4, D5 and D6 identify the pending interrupts.

To receive serial data. Bit D7 is used to receive serial data.

1.4.4 Software interrupts:

There are eight software interrupts Viz., RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.
These are 1-bye call instructions and transfer the program execution to a specific location as
detailed below:
Interrupt

Call location

RST 0

0000H

RST 1

0008H

RST 2

0010H

RST 3

0018H

RST 4

0020H

RST 5

0028H

RST 6

0030H

RST 7

0038H

1.5 Interfacing:
1.5.1 Interfacing I/O Devices:
Comparison of Memory-Mapped I/O and Peripheral Mapped I/O:
S.
No.

Characteristics

Device Address

Control Signals for Input/Output

Instructions Available

Memory-Mapped I/O
16-Bit

MEMR / MEMW
Memory related instructions

Peripheral I/O
8-Bit

IOR / IOW
IN and OUT

such as STA; LDA; LDAX;

STAX; MOV M,R; ADD M;
ANA M etc.,
4

Data Transfer

Between any Register & I/O

Only between I/O and the

Maximum No. of I/Os Possible

The memory map (64K) is

The I/O map is

shared between I/Os &

independent of the

system Memory

memory map; 256 Input &

Accumulator

256 Output devices can be

connected
6

Execution Speed

13 T-states (STA, LDA)

10 T-states

07 T-states (MOV M,R)

7
8

Hardware Requirements
Other Features

More H/W is needed to

Less H/W is needed to

decode 16-Bit address

decode 8-Bit address

Arithmetic or Logical

Not Available

operations can be directly

performed with I/O data

1.6 Instruction set:

10

8085 Instruction Set

S

Flags
A

MVI Rd,D8
MVI M,D8
MOV Rd,Rs
MOV Rd,M
MOV M,Rs
LXI Rp, D16
LXI SP,D16
LHLD A16
SHLD A16
LDA A16
STA A16
LDAX RpB/D
STAX RpB/D
XCHG

ADD Rs
ADD M
ADI D8
ADC Rs
ADC M
ACI D8
SUB Rs
SUB M
SUI D8
SBB Rs
SBB M
SBI D8
DAD Rp
DAD SP
INR Rs
INR M
INX Rp
INX SP
DCR Rs
DCR M
DCX Rp
DCX SP
DAA
CMP Rs
CMP M
CPI D8
ANA Rs
ANA M
ANI D8
ORA Rs
ORA M
ORI D8
XRA Rs
XRA M
XRI D8
CMA
STC
CMC
RAL
RAR

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
1
1
0
0
0
0
0
0
-

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-

Mnemonic

TS

M/C

Description

Data Transfer Instructions

10
2
Move Immediate to Register
10
2
Move Immediate to Memory
4
1
Move register to register
7
2
Move memory to register
7
2
Move register to Memory
10
3
Load Immediate Rp
Load Immediate Stack Pointer
10
3
16
5
Load HL Direct
16
5
Store HL Direct
13
4
Load Accumulator Direct
13
4
Store Accumulator
7
2
Load Accumulator indirect
7
2
Store accumulator indirect
4
1
Exchange HL with DE
ARITHMETIC / LOGICAL Instructions
*
4
1
Add Register to ACC
*
7
2
Add to Memory to ACC
*
7
2
Add Immediate to ACC
*
4
1
Add Register to ACC with CY
*
7
2
Add to Memory to ACC with CY
*
7
2
Add Immediate to ACC with CY
*
4
1
Subtract Register from ACC
*
7
2
Subtract Memory from ACC
*
7
2
Subtract Immediate from ACC
Subtract Register from ACC with CY
*
4
1
Subtract Memory from ACC with CY
*
7
2
Subtract Immediate from ACC with CY
*
7
2
*
10
3
Double Add Rp to HL
*
10
3
Double Add SP to HL
4
1
Increment Register
10
3
Increment Memory
6
1
Increment Rp
6
1
Increment Stack Pointer
4
1
Decrement Register
10
3
Decrement Memory
6
1
Decrement Rp
6
1
Decrement Stack Pointer
*
4
1
Decimal Adjust Accumulator
*
4
1
Compare Register with ACC
*
7
2
Compare Memory with ACC
*
7
2
Compare Immediate with ACC
0
4
1
AND Register and Accumulator
AND Memory and Accumulator
0
7
2
0
7
2
AND Immediate and ACC
0
4
1
Inclusive OR Accumulator
0
7
2
Inclusive OR Accumulator
0
7
2
Inclusive OR Immediate
0
4
1
Exclusive OR Accumulator
0
7
2
Exclusive OR Accumulator
0
7
2
Exclusive OR Immediate
4
1
Complement Accumulator
1
4
1
Set Carry
*
4
1
Complement Carry
*
4
1
Rotate Accumulator Left
*
4
1
Rotate Accumulator Right

Notes

Rd=D8
[HL]=D8
Rd=Rs
Rd=[HL]
[HL]= Rs
Rp= D16
SP=D16
HL=[ A16]
[A16]=HL
A=[A16]
[A16]=A
A=[RpB/D]
[RpB/D]=A
HL<->DE
A=A+Rs
A=A+[HL]
A=A+D8
A=A+CY+Rs
A=A+CY+[HL]
A=A+CY+D8
A=A-Rs
A=A-[HL]
A=A-D8
A=A-CY-Rs
A=A-CY-[HL]
A=A-CY-D8
HL=HL+Rp
HL=HL+SP
Rs= Rs+1
[HL]=[HL]+1
Rp = Rp+1
SP=SP+1
Rs=Rs-1
[HL]=[HL]-1
Rp=Rp-1
SP=SP-1
A=BCD[A]
A-Rs
A-[HL]
A-D8
A=A&Rs
A=A&[HL]
A=A&D8
A=AvRs
A=Av[HL]
A=AvD8
A=A (X-OR) Rs
A=A (X-OR) [HL]
A=A (X-OR) D8
A=~A
CY=1
CY=~CY
A={CY,A}<A=->{CY,A}

11

Flags
A

RLC
RRC

*
*

JMP A16
JC A16
JNC A16
JPE A16
JPO A16
JZ A16
JNZ A16
JP A16
JM A16
PCHL
CALL A16
CC A16
CNC A16
CPE A16
CPO A16
CZ A16
CNZ A16
CP A16
CM A16
RET
RC
RNC
RPE
RPO
RZ
RNZ
RP
RM

PUSH Rp
POP Rp
POP PSW
SPHL
XTHL
IN A8
OUT A8
DI
EI
NOP
HLT
SIM
RIM

4
1
Rotate left circular
4
1
Rotate right circular
Branch Control Instructions
7
3
Jump unconditional
2M/7T
Jump on Carry
if the
Jump on no Carry
condition Jump on Parity Even
is FALSE Jump on Parity Odd
3M/10T
Jump on Zero
if the
Jump on No Zero
condition Jump on Plus
is TRUE
Jump on Minus
6
1
Jump HL indirect
18
5
Call unconditional
2M/9T
Call on Carry
if the
Call on No Carry
condition Call on Parity Even
is FALSE Call on Parity Odd
5M/18T
Call on Zero
if the
Call on No Zero
condition Call on Plus
is TRUE
Call on Minus
10
3
Return
1M/6T
Return on Carry
if the
Return on No Carry
condition Return on Parity Even
is FALSE Return on Parity Odd
3M/12T
Return on Zero
if the
Return on No Zero
condition Return on Plus
is TRUE
Return on Minus
I/O & M/C Control Instructions
12
3
Push Rp
12
3
Push Processor Status Word
10
3
Pop Rp
10
3
Pop Processor Status Word
6
1
Move HL to SP
16
5
Exchange stack Top with HL
10
3
Input
10
3
Output
4
1
Disable Interrupts
4
1
Enable Interrupts
4
1
No Operation
5
2
Halt
4
1
Set Interrupt Mask
4
1
Read Interrupt Mask

RST z

Mnemonic

PUSH PSW

TS

12

M/C

Description

Restart

Notes

A=A<A=->A
PC=A16
If CY=1
If CY=0
If P=1
If P=0
If Z=1
If Z=0
If S=0
If S=1
PC=[HL]
-[SP]=PC, PC= A16
If CY=1
If CY=0
If P=1
If P=0
If Z=1
If Z=0
If S=0
If S=1
PC=[SP]+
If CY=1
If CY=0
If P=1
If P=0
If Z=1
If Z=0
If S=0
If S=1
-[SP]= Rp
-[SP]={PSW,A}
Rp=[SP]+
[PSW,A]=[SP]+
SP=HL
[SP]<->HL
A=[A8]
[A8]=A

Mask=A
A=mask
-[SP]=PC,
PC=HEX(z8)

Rs

Source Register (A, B, C, D, E, H, L)

A8

8-Bit Address

Rd

Destination Register (A, B, C, D, E, H, L)

16-Bit Address

Rp

Register Pair (BC, DE, HL)

A16
PSW

Program Status Word (A & FLAG Register)

R pB/D

Register Pair BC or DE

Number 0 to 7

D8

8-Bit Data

ACC

Accumulator

D 16

16-Bit Data

Memory Pointer (HL Pair)

Affected

Not Affected

Flags
*

Note: Highlighted Instructions take 6 T-states for opcode fetch

12