SSM INSTITUTE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ECE
TRAINING ON DIGITAL ELECTRONICS DEC, 2015
WORK SHEET # 1
1.

The subtraction of a binary number Y from another binary number X, done by adding
2s compliment of Y to X, results in a binary number without overflow. This implies
that the result is
a. Negative and is in normal form
b. Negative an is in 2s compliment form
c. Positive and is in normal form
d. Positive and is in 2s compliment form

2. 2s complement representation of a 16 bit number (one sign bit and 15

magnitude bits) is FFFF. Its magnitude in decimal representation is

3.

a. 0
b. 1
c. 32,767
d. 65,535
An equivalent 2s complement representation of the 2s complement number is 1101
is
a. 110100
b. 001101
c. 110111
d. 111101

4.

Two 2s complement numbers having sign bits x and y are added and the sign bit of
the result is z. Then, the occurrence of overflow is indicated by the Boolean function

5.

The 2s complement representation of 17 is

a. 101110
b. 101111
c. 111110
d. 1 10001
4 bit 2s complement representation of a decimal number is 1000. The number is
a. +8
b. 0
c. -7
d. -8
The range of signed decimal numbers that can be represented by 6 bit 1s complement
form is
a. -31 to +31

6.

7.

b. -63 to +64
c. -64 to +63
d. -32 to +31

8.

11001, 1001 and 111001 correspond to the 2s complement representation of which

one of the following sets of number?
a. 25, 9 and 57 respectively
b. -6, -6 and -6 respectively
c. -7, -7 and -7 respectively
d. -25, -9 and -57 respectively

Decimal 43 in Hexadecimal and BCD number system is respectively

a. B2, 0100 0011
b. 2B, 0100 0011
c. 2B, 0011 0100
d. B2, 0100 0100
10. A new Binary Coded Pentary (BCP) number system is proposed in which every digit
of a base-5 number is represented by its corresponding 3-bit binary code. For
example, the base-5 number 24 will be represented by its BCP code 010100. In this
number system, the BCP code 100010011001 corresponds to the following number in
base-5 system
a. 423
b. 1324
c. 2201
d. 4231
11. X = 01110 and Y = 11001 are two 5 bit binary numbers represented in 2s
compliement format. The sum of X and Y represented in 2s compliment format using
6 bits is
a. 100111
b. 001000
c. 000111
d. 101001
12.
The number of bytes required to represent the decimal number
9.

1856357 in packed BCD (Binary Coded Decimal) form is .

a.
b.
c.
d.

4 Bytes
2 Bytes
3 Bytes
1 Byte

SSM INSTITUTE OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ECE
TRAINING ON DIGITAL ELECTRONICS DEC, 2015
WORK SHEET # 2
1.

For the circuit shown below, the output F is given by

2.

Minimum number of 2 input NAND gates required to implement the function given
below is

a.
b.
c.
d.

3
4
5
6

3.

Indicate which of the following logic gates can be used to realized all possible
combinational logic functions :
a. OR gates only
b. NAND gates only
c. EX-OR gates only
d. EX- NOR gates only

4.

For the logic circuit shown in figure, the output Y is equal to

5.

6.

Boolean expression for the output of XNOR logic gate with inputs A and B is
a. AB + AB
b. (AB) + AB
c. (A + B)(A + B)
d. (A + B)(A + B)
The output of a logic gate is 1 when all its inputs are at logic 0. The gate is either
a. a NAND or an EX-OR gate
b. a NOR or an EX-NOR gate
c. an OR r an EX-NOR gate
d. an AND or an EX-OR gate

7.

The output of the circuit shown in figure is equal to

8.

The minimum number of NAND gates required to implement the Boolean function
A + AB + ABC is equal to
a. Zero
b. 1
c. 4
d. 7
The output of the logic gate shown is

9.

10.

11.

a. 0
b. 1
c. A
d. A
The minimum number of 2 input NAND gates required to implement the Boolean
function Z = ABC, assuming that A, B and C are available, is
a. Two
b. Three
c. Five
e. Six

For the logic circuit shown in the figure, the required input combination (A,B,C) to
make the output X = 1 is

a.
b.
c.
d.
12.

For the logic circuit shown, the simplified Boolean expression for the output Y is

a.
b.
c.
d.
13.

A+B+C
A
B
C

In the figure, the LED

a.
b.
c.
d.

14.

1, 0, 1
0, 0, 1
1, 1, 1
0, 1, 1

Emits light when both S1 and S2 are closed.

Emits light when both S1 and S2 are open.
Emits light when only of S1 or S2 is closed.
Does not emit light, irrespective of the switch positions.

If the input to the digital circuit of the figure, consisting of a cascade of 20 XOR gates
is X, then the output Y is equal to

15.

The logic function implemented by the following circuit at the terminal OUT is

a.
b.
c.
d.

P NOR Q
P NAND Q
P OR Q
P AND Q

16.

Which of the following Boolean expression correctly represents the relation between
P, Q, R and M1?

17.

Match the logic gates in Column A with their equivalents in Column B.

a.
b.
c.
d.

P 2, Q 4, R 1, S 3
P 4, Q 2, R 1, S 3
P 2, Q 4, R 3, S 1
P 4, Q 2, R 3, S 1

SSM INSTITUTE OF
ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ECE
TRAINING ON DIGITAL ELECTRONICS DEC, 2015
WORK SHEET # 3

1. Implement an AND gate using mux?

2. Build a 4:1 mux using only 2:1 mux?
3. Given only two xor gates one must function as buffer and another as inverter?
4. What is slack?
5. Design a four-input NAND gate using only two-input NAND gates?
6. Convert D-FF into divide by 2
7. Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch?
8. How to implement a Master Slave flip flop using a 2 to 1 mux?
9. How many 2 input xor's are needed to implement 16 input parity generators? How do we
Know, if given a circuit, whether it is a Combinational Circuit or a Sequential Circuit?
10. Ben Bit diddle is having a picnic. He wont enjoy it if it rains or if there are ants. Design
a circuit that will output TRUE only if Ben enjoys the picnic.
11. Define negative clock skew and positive clock skew.
12. Define Metastability
13. Design a XNOR. Using only four NOR gates
14. Expand the following: PLA, PAL, CPLD, FPGA.
15. Arrange the following in the increasing order of their complexity: FPGA,PLA,CPLD,PAL.
16. Which is better: synchronous reset or asynchronous reset signal?
17. Expand: DTL, RTL, ECL, TTL, CMOS, BiCMOS.
18. In a certain digital waveform, the period is four times the pulse width. The duty cycle is
________.

19. A pulse has a period of 15 ms. Its frequency is ________.

20. Define noise margin
21. TTL interpret _____ to ____voltage as logic low and ___ to _____ as logic high.
22. What is current sink and current source? Explain TTL current sink and source with
diagram
23. In a 4-bit Johnson counter How many unused states are present?
24. How can you convert a JK flip-flop to a D flip-flop?