A Project Report On

Set Associative Cache

Submitted to

Dr. M S Bhat
By

Aamodh.K (15VL01F)
Dokula Ashok Kumar (15VL08F)
Vikas Bhardwaj (15VL26F)
(M.Tech VLSI Design)

As a part of
VL722: Advanced Computer Architecture

Department of Electronics and Communication,

National Institute of Technology Karnataka
Surathkal
17th November 2015

4 Way Set Associative Cache

CONTENTS

CONTENTS

LIST OF FIGURES

ii

1. Problem Statement

2. Design Description

3. Design Approach

4. Simulation Results and Observations

REFERENCES

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4 Way Set Associative Cache

LIST OF FIGURES
Figure 1: System Block Layout

Figure 2: Physical address split up

Figure 3: 4 way Set Associative Cache block diagram

Figure 4: Cache controller signals

Figure 5: Simulation plot

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Advanced Computer Architecture Project

2015

1. Problem Statement

Goal: To design cache memory for uni-processor system using Verilog HDL.

Cache Memory Specifications:

Number of levels of cache: 1

Size of cache: 16kB
Cache bock size: 16 words
Word size: 1 byte

Features:

Set associative mapping

4 way associativity
Write Hit policy: Write through
Write Miss policy: Write allocate
Replacement policy: Random way replacement
Detect cache hit or miss and send Read miss and Write miss signals to Main Memory
on a cache miss.

The project aims at designing and testing the above mentioned memory hierarchy of cache
memory for uni-processor system and obtain the simulation results using Xilinx ISE
platform.

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Advanced Computer Architecture Project

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2. Design Description

The design consists of one level of cache memory and a cache controller that communicates
between microprocessor and cache memory to carry out memory related operations. The
size and specifications of the cache memory are stated in the problem statement above and
the design approach is described in the next section.

Fig 1: System block layout

The functionality of the design is explained below:
1. Cache controller receives the address that microprocessor wants to access.
2. Cache controller looks for address in cache.
3. If the address is in cache (cache hit occurs), the data from location is provided to the
microprocessor via the data bus.
4. If address is not found in cache, cache miss occurs.
5. Cache controller will request the same address to the main memory.

Note: The functionality in point 5 is not modeled in our project. In our project cache
controller gives a signal (memRead and memWrite in code) to the microprocessor that a
cache miss has occurred in cache. The action taken by microprocessor is not a part of our
project.

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Detailed cache specifications

Designed cache is byte addressable.

Word size: 32 bits (4 bytes)
Cache block size: 128 bits (4 words)
Physical address: 24 bits
o Tag: 12 bits
o Set Select: 8 bits
o Byte Select: 4 bits

Fig 2: Physical address split up

Number of sets per way: 256

Size of way: 32768 bits (4kB)
Number of ways: 4
Total cache size: 16kB

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Advanced Computer Architecture Project

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Cache Memory Architecture

Fig 3: 4 way Set Associative Cache block diagram

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Advanced Computer Architecture Project

2015

Cache Controller
The following diagram depicts all the signals of the cache controller that are used to carry
out all memory related operations between microprocessor and cache.

Fig 4: Cache controller signals

Input signals:
dataIn : Byte input to the cache.
replacementWay : The way that needs to be replaced on a cache miss.
byteAddr : 24-bit physical address of the byte to be accessed.
randomTag : Generates random tags to each cache block. The MSB of randomTag is
Valid Bit.
WE : Asserted when cache Write is to be performed. When not asserted, it means
cache Read operation is requested.
rst : Clears all the memory elements. Active HIGH signal.
clk : External clock.

Output signals:
dataOut : The byte output from the cache.
memWrite : Asserted when main memory write is performed because of cache miss.
It is HIGH if cache write miss has occurred.
memRead : Asserted when main memory read is to be performed because of cache
miss. It is HIGH if cache read miss has occurred.

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Advanced Computer Architecture Project

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3. Design Approach

The project is designed using the Hardware Descriptive Language - Verilog. Xilinx ISE Design
Suite 13.1 was used to simulate the design.
The basic storage element in the memory is modeled using a D flip-flop. Each D flipflop stores a single bit.
An array of 8 such storage elements is created to form a byte of data.
An array of 16 such bytes is formed to create a Cache Block. This cache block contains
4 words of 4 bytes each.
Then, an array of 256 such cache blocks are created to form a Cache Way.
Finally, an array of 4 such Cache Ways are created to form the 4 way Set Associative
Cache.
The tag size in our design is 12 bits. Hence, corresponding to each set, a 12 bit register
is created to store tag using D flip-flop module.
A 12 bit comparator is created to compare the tags of a particular set and the tag field
in the processor generated address.
In case of a cache miss, Random Replacement policy is used.
In case more than one cache block in a set is allocated same tag, in order to avoid
conflict, a 4-to-2 priority encoder module is designed and used. Priority is given to the
cache block in the way with highest index.
Decoders and multiplexers of suitable size are used for the purpose of decoding the
address and selecting required data respectively.

Role of Cache Controller:

All operations in cache are guided by Cache Controller. Any address request from processor
is first directed to the cache controller. The cache controller then looks for the address in
cache. If a cache hit occurs the data from the requested location is transferred to the
processor. In case a cache miss occurs, the cache controller sends out a read miss or write
miss signal.

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Advanced Computer Architecture Project

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4. Simulation Results and Observations

Observations
From the plot shown in next page, the following observations can be made.
1. Until 20ns, there is no instance of cache hit. This can be observed from the fact that
at any instance either memRead is HIGH or memWrite is HIGH. Since no data is
written into cache till now, dataOut is xxxxxxxx.
2. At 20ns, the tag field of processor generated address byteAddr and the tag
corresponding to set select field of byteAddr are the same.
3. At 30ns, i.e, at the next positive clock edge, cache hit is detected. Notice both
memWrite and memRead being LOW. The one cycle latency is because certain
modules are called at one positive clock edge in cache controller module and are
executed at next positive clock edge.
4. At 180ns, dataIn changes. But since there is no cache hit, dataIn is not transferred to
data bus.
5. At 380ns, even though the tag remains same the valid bit (most significant bit of
randomTag) is made 0. Hence there is a cache miss indicated by either memRead or
memWrite being HIGH at a given instant.
6. At 760ns, rst is made HIGH. So, the data bus is cleared. Also, cache hit is not detected
even though the tags are matching.

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Advanced Computer Architecture Project

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Simulation plot

Figure 5: Simulation plot

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REFERENCES:
1. J.L. Hennessy and D. A. Patterson, Computer Architecture A quantitative approach,
4th edition.
2. M.S. Bhat, Course Slides for VL722: Advanced Computer Architecture, National
Institute of Technology Karnataka at Surathkal, Odd semester, 2015.
3. P.K. Biswas, Lectures 19 and 20 of NPTEL Video Lectures for Operating Systems, Indian
Institute of Technology, Kharagpur.

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