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Cmos and Finfet Tech
Cmos and Finfet Tech
Sphere: Technologies | back-bias, bonded wafer, FD-SOI, multi-Vt design, partially depleted
SOI, Soitec, ST-Ericsson
its relatively small Crolles plant, where its FD-SOI process was developed, or at the
GlobalFoundries 28nm and 20nm-capable fabs.
What are the risks and downsides of FD-SOI?
The primary problems with FD-SOI lie in the supply chain. Although it is possible to
create the oxide layers on bulk silicon wafers and then use epitaxy to define silicon
channels on the surface, the surface quality needed for nanometer processes is best
supported through the use of specialized, bonded SOI wafers. As with any nonmainstream process, these wafers are more expensive although some cost savings
could be achieved through simpler processing at the transistor-building stage. For
example, the channel does not need to be doped, which causes fewer problems
with variability and, therefore, device yield.
Although basic models are available and research efforts have generated
increasingly accurate device-level models, some of the effects seen in nanometrescale FD-SOI devices are not yet taken into account in industrial-grade models.
become blurs, and some small features on the mask wont appear on the wafer at
all.
A number of reticle enhancement techniques have been introduced to counteract
the diffraction problem as it has become more acute with each new process node.
Phase-shift masks were introduced at the 180nm process node. They alter the
phase of the light passing through some areas of the mask, changing the way it is
diffracted and so reducing the defocusing effect of mask dimensions that are less
than the wavelength of the illuminating light. The downside of using phase-shift
techniques is that the masks are more difficult and expensive to make.
Optical-proximity correction (OPC) techniques work out how to distort the patterns
on a mask to counter diffraction effects, for example by adding small ears to the
corners of a square feature on the mask so that they remain sharply defined on the
wafer. The technique introduces layout restrictions, has a computational cost in
design, and means that it takes longer and costs more to make the corrected
masks.
There are useful insights into the way in which different reticle enhancement
techniques can interact in this article about lithography-friendly design.
Theres a discussion of how to optimise the parameters of the scripts used to
undertake OPC on a full chip design here, and a piece on using a simulated
annealing technique to optimise multiple script parameters here. Theres also a
discussion of reducing the impact of advanced OPC techniques on mask-making
costs, which rise with increasing complexity, here.
Optical equipment improvements, such as lenses with higher numerical apertures
that can bend the illuminating light more strongly, and immersion techniques that
put layers of liquid between the lens and the wafer to focus the light more strongly,
have also helped extend the lifetime of 193nm lithography. The gains available from
these techniques have been limited by the lack of significantly superior materials
for the lenses and the immersion fluids.
Alternative illumination techniques, such as off-axis illumination and the use of
multiple sources, give designers another way to make diffraction and interference
effects work to their advantage. The technique introduces complexity to the
illumination source in the wafer stepper and to the mask design.
Computational lithography, which blends OPC and alternative illumination by using
computation to start with the desired pattern on the wafer and work backwards to
define how to pre-distort the mask and configure multiple illumination sources to
achieve that pattern on the wafer. This approach takes large amounts of
computation power.
Theres a look at how computational lithography has evolved over the past 12
years here, and an interesting discussion of the potential of source-mask
optimisation and alternative illumination techniques in a paper here.
Double patterning is another technique used to extend the useful lifetime of 193nm
lithography. The process splits dense patterns into two interleaved patterns of lessdense features, defined by two masks. Given sufficiently accurate alignment, the
two patterns marry up on the wafer surface to create much denser features than
could be achieved with one mask.
Where can I use it?
Double patterning will be necessary to define the critical layers of designs being
built using 193nm illumination on process nodes below 30nm.
What are the risks of using double patterning?
Design restrictions. Double patterning will work best on designs whose critical
layers can be split into two separately defined but aligned patterns in a
predictable way. This means that producing a design layout that looks like a
diffraction grating is good, while a design littered with diagonal lines, jogs,
and vias between layers may be less easy to split effectively.
Variability. The emphasis on more regular layout with long linear tracks may
make designs more susceptible to the performance variability brought on by
limited control of the roughness of the edges of patterned .