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313042
313042
148
2nd International Conference on Advances in Electrical and Electronics Engineering (ICAEE'2013) March 17-18, 2013 Dubai (UAE)
1
H ( z) =
N
1 z N
1
1 z
(2)
1 sin( N / 2)
H ( e j ) =
N sin( / 2)
(3)
H ( z) =
1 1 z N
N 1 z 1
(1)
represents the
Fig.1 shows the first order CIC filter; here the clock
divider circuit divides the oversampling clock signal by the
oversampling ratio, M after the integrator stage. The integrator
operates at the input sampling frequency, while the
.
differentiator operates at down sampled clock frequency
149
2nd International Conference on Advances in Electrical and Electronics Engineering (ICAEE'2013) March 17-18, 2013 Dubai (UAE)
G K (F ) sin ( N Fm / Fx )
d cK = c K m =
Gc (0) N sin ( N Fm / Fx )
x[n]
Fx
d =
sin ( N f m / 2 )
(4)
sin ( (1 / N Fm / Fx )
G K (F )
= K c m
=
sin ( Fm / Fx )
Gc (Fx / N Fm )
K
c
Fy = Fx/N
(5)
x[n]
N sin ( f m / 2 )
y[m]
1 1 z N
1
N 1 z
Fx
1 1
N 1 z 1
y[m]
[1 z ]
1 K
Fy = Fx/N
(6)
1 sin( N / 2)
1 sin( N / 2)
3
2
sin(
/
2
)
sin(
/
2
)
N
N
N
N
2
1
1
H sh (ei ) =
L
1 sin( N1 / 2)
N1 sin( / 2)
(7)
where N is decimation factor and N = N 1 * N 2
K is number of stages
150
2nd International Conference on Advances in Electrical and Electronics Engineering (ICAEE'2013) March 17-18, 2013 Dubai (UAE)
[H 1 (z )]
x (n )
[H 2 (z )]L
Fx
y[m]
[H 1 (z )]
2K
-2
N1
Fy = Fx/N
z ( N 2 1) K / 2
First stage
N2
3
Fig. 8 Two-stage implementation of the modified sharpened comb decimator
H ( z ) = h[k ] z k
N 1
(8)
k =0
In expanded form,
y (m ) = h[k ] x[nM k ]
(9)
k =0
x[n]
v[n]
y[m]
M
h[n]
Fx
Fy = Fx/M
(11)
N 1
Fx
(10)
k =0
(13)
(14)
(15)
( )
( )
H ( z ) = E0 z 2 + z 1 E1 z 2
(16)
( )
M 1
H ( z ) = z k Ek z M
k =0
where, Ek ( z ) =
151
[N
M]
h[Mn + k ] z
n =0
(17)
N
, 0 k M 1 (18)
2nd International Conference on Advances in Electrical and Electronics Engineering (ICAEE'2013) March 17-18, 2013 Dubai (UAE)
1 1 zN
1
N 1 z
y[m]
(z )
R
Fy = Fx/M
Fig. 12 Cascade implementation of two-stage decimator composed of a CIC filter and an FIR filter
x[n]
Fx
y[m]
( )
1 1 zN z N
1
N 1 z
N
Fy = Fx/M
Fig. 13 Single-stage equivalent of two-stage decimator composed of a CIC filter and an FIR filter
x (n )
Fx
[H 1 (z )]K
[H 2 (z )]L
-2
N1
z ( N1 1) K / 2
N2
First stage
v0 (m )
v1 (m )
v[n]
[H 1 (z )]2 K
v2 (m )
vR 1 (m )
E0 (z )
E1 ( z )
E 2 (z )
E M 1 ( z )
152
y (m )
Fy = Fx / M
2nd International Conference on Advances in Electrical and Electronics Engineering (ICAEE'2013) March 17-18, 2013 Dubai (UAE)
V. RESULTS
Design the two stage decimator and compute the single
stage equivalent for the specification.
The decimation factor M=16; The overall decimation filter
H(z) is specified by, Passband edge P = 0.05 , and the
decimation of the passband magnitude response are bounded
to a p = 0.15dB. Stopband edge frequency s = /M = 0.1
with the minimal stopband attenuation a s = 50dB. Consider
the phase characteristics is linear.
Solution:
The overall factor 16 decimator is composed cascade of two
decimators.
VI. CONCLUSION
REFERENCES
[1]
[2]
[3]
[4]
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2nd International Conference on Advances in Electrical and Electronics Engineering (ICAEE'2013) March 17-18, 2013 Dubai (UAE)
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
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