CHAPTER-3

3. MICROCONTROLLER
3.1 INTRODUCTION
Microcontrollers are designed to play an increasingly important role in
revolutionizing various industries and influencing our day to day life more
strongly than one can imagine. Since its emergence in the early 1980's the
microcontroller has been recognized as a general purpose building block for
intelligent digital systems. It is finding using diverse area, starting from simple
children's toys to highly complex spacecraft. Because of its versatility and
many advantages, the application domain has spread in all conceivable
directions, making it ubiquitous. As a consequence, it has generate a great deal
of interest and enthusiasm among students, teachers and practicing engineers,
creating an acute education need for imparting the knowledge of
microcontroller based system design and development. It identifies the vital
features responsible for their tremendous impact, the acute educational need
created by them and provides a glimpse of the major application area.
A microcontroller is a complete microprocessor system built on a single
IC. Microcontrollers were developed to meet a need for microprocessors to be
put into low cost products. Building a complete microprocessor system on a
single chip substantially reduces the cost of building simple products, which
use the microprocessor's power to implement their function, because the
microprocessor is a natural way to implement many products. This means the
idea of using a microprocessor for low cost products comes up often. But the
typical 8-bit microprocessor based system, such as one using a Z80 and 8085 is
expensive. Both 8085 and Z80 system need some additional circuits to make a
microprocessor system. Each part carries costs of money. Even though a
product design may require only very simple system, the parts needed to make
this system as a low cost product.

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 To solve this problem microprocessor system is implemented with a single
chip microcontroller. This could be called microcomputer, as all the major parts
are in the IC. Most frequently they are called microcontroller because they are
used they are used to perform control functions.
The microcontroller contains full implementation of a standard
MICROPROCESSOR, ROM, RAM, I/O, CTOCK, TIMERS, and also
SERIAL PORTS. Microcontroller also called "system on a chip" or "single
chip microprocessor system" or "computer on a chip".
A microcontroller is a Computer-On-Chip, or, if you prefer, a single-chip
computer. Micro suggests that the device is small, and controller tells you that
the device' might be used to control objects, processes, or events. Another term
to describe a microcontroller is embedded controller, because the
microcontroller and its support circuits are often built into, or embedded in, the
devices they control.
Today microcontrollers are very commonly used in wide variety of
intelligent products. For example most personal computers keyboards and
implemented with a microcontroller. It replaces Scanning, Debounce, Matrix
Decoding, and Serial transmission circuits. Many low cost products, such as
Toys, Electric Drills, Microwave Ovens, VCR and a host of other consumer
and industrial products are based on microcontrollers.

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3.2 EVOLUTION OF MICROCONTROLLER
Markets for microcontrollers can run into millions of units per
application. At these volumes of the microcontrollers is a commodity items and
must be optimized so that cost is at a minimum. miconductor manufacturers
have produced a mind-numbing array of designs that would seem to meet
almost any need. Some of the chips listed in this section are no longer regular
production, most are current, and a few are best termed as "smoke ware": the
dreams of an aggressive marketing department.

SI Manufacturer Chip Year RAM ROM Other

No. No
Designation of of Features
Pins I/O
4 Bit MC

1. TMS 1000 28 23 64 IK
Texas Mid TED
Instruments 1970 Display
2. Hitachi HMCS 40 - 28 10 32 512
10 bit
ROM
3. Toshiba TLCS47 - 42 35 128 2K
Serial bit
I/O
8 bit MC

1. Intel 8048 1976 40 27 64 IK

External
Memory

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 8K

2 Intel 8051 1980 40 32 128 4K External

Memory
128 K
3. Motorola 6081 1977 - 31 128 2K

4. Motorola 68HC11 1985 52 40 256 8K Serial

Port,
ADC,
5. Zilog Z8 40 32 128 2K External
Memory
128K,

16 Bit MC

1. Intel 80C196 68 40 232 8K External

Memory
64K,
Serial
Port,
ADC,
WDT,
PWM

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2. Hitachi H8/532 84 65 IK 32K External
Memory
1M,
Serial
Port,
ADC,
PWM
3. National HPC16164 68 52 512 16K External
Memory
64K,
ADC,
WDT,
PWM
32 Bit MC

1. Intel 80960 - 132

20 MHz clock, 32 bit bus, 512
byte instruction cache

3.1: Evolution of micro controller

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3.3 ARCHITECTURE OF 89S52

3.1: Architecture of 89s52 .

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 The AT89S52 is a low-power, high-performance CMOS 8-bit
microcontroller with 8Kbytes of in-system programmable Flash memory. The
device is manufactured usingAtmel's high-density nonvolatile memory
technology and is compatible with the industry-standard 80C51 instruction set
and pinout. The on-chip Flash allows the programmemory to be reprogrammed
in-system or by a conventional nonvolatile memory programmer.

By combining a versatile 8-bit CPU with in-system programmable Flash

ona monolithic chip, the Atmel AT89S52 is a powerful microcontroller which
provides ahighly-flexible and cost- effective solution to many embedded
control applications.The AT89S52 provides the following standard features:
8K bytes of Flash, 256 bytesof RAM, 32 I/O lines, Watchdog timer, two data
pointers, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In
addition, the AT89S52 is designed with static logic for operationdown to zero
frequency and supports two software selectable power saving modes.

The Idle Mode stops the CPU while allowing the RAM, timer/counters,
serial port, and interrupt system to continue functioning. The Power-down
mode saves the RAM contents.but freezes the oscillator, disabling all other
chip functions until the next interrupt or hardware reset..

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3.4 FEATURES OF 8-BIT MICRO CONTROLLER (ATMEL
89C52):

Series: 89c51 Family, Technology:Cmos

• 8 Bit CPU optimized for control applications
• Extensive Boolean processing (Single - bit Logic) Capabilities.
• On - Chip Flash Program Memory
• On - Chip Data RAM
• Bi-directional and Individually Addressable I/O Lines
• Multiple 16-Bit Timer/Counters
• Full Duplex UART
• Multiple Source / Vector / Priority Interrupt Structure
• On - Chip Oscillator and Clock circuitry.
• On - Chip EEPROM
• SPI Serial Bus Interface
• Watch Dog Timer

3.5 MICROCONTROLLER CIRCUIT

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 3.2. Circuit Diagram of Microcontroller

The micro controller circuit is connected with reset circuit, crystal

oscillator circuit; LCD circuit the reset circuit is the one, which is an external,
interrupt which is designed to reset the program. And the crystal oscillator
circuit is the one used to generate the pulse to micro controller and it also called

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as the heart of the microcontroller here we have used used 12mhz crystal which
generates pulse.The AT89S52 is a low-power, high-performance CMOS 8-bit
microcontroller with 8K bytes of in-system programmable Flash memory. The
device is manufactured using Atmel's high-density nonvolatile memory
technology and is compatible with the industry- standard 80C51 instruction set
and pinout. The on-chip Flash allows the program memory to be programmed
in-system or by a conventional nonvolatile memory programmer.By combining
a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip,
the Atmel AT89S52 is a powerful microcontroller which provides a highly-
flexible and cost- effective solution to many embedded control
applications.The AT89S52 provides the following standard features: 8K bytes
of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers,
three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full
duplex serial port, on-chip oscillator, and clock circuitry. In addition, the
AT89S52 is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops
the CPU while allowing the RAM, timer/counters, serial port, and interrupt
system to continue functioning. The Power-down mode saves the RAM
contents but freezes the oscillator, disabling all other chip functions until the
next interrupt or hardware reset.

3.6 POWER MODES OF

MICROCONTROLLER(ATMEL 89C52):
To exploit the power savings available in CMOS circuitry, Atmel's Flash
micro controllers have two software-invited reduced power modes.

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3.6.1 IDLE MODE:
The CPU is turned off while the RAM and other on - chip peripherals
continue operating. In this mode current draw is reduced to about 15 percent of
the current drawn when the device is fully active.

3.6.2 POWER DOWN MODE:

All on-chip activities are suspended while the on - chip RAM continues
to hold its data. In this mode, the device typically draws less than 15 Micro
Amps and can be as low as 0.6 Micro Amps
3.6.3 POWER ON RESET:
When power is turned on, the circuit holds the RST pin high for an
amount of time that depends on the capacitor value and the rate at which it
charges.
To ensure a valid reset, the RST pin must be held high long enough to
allow the oscillator to start up plus two machine cycles. On power up, Vcc
should rise within approximately 10ms. The oscillator start-up time depends on
the oscillator frequency. For a 10 MHz crystal, the start-up time is typically
1ms.With the given circuit, reducing Vcc quickly to 0 causes the RST pin
voltage to momentarily fall below 0V. How ever, this voltage is internally 1
limited and will not harm the device.

3.7 MEMORY ORGANIZATION:

* Logical Separation of Program and Data Memory *
All Atmel Flash micro controllers have separate address spaces for
program and data memory. The logical separation of program and data memory
allows the data memory to be accessed by 8 bit addresses, which can be more

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quickly stored and manipulated by an 8 bit CPU Nevertheless 16 Bit data
memory addresses can also be generated through the DPTR register.
Program memory can only be read. There can be up to 64K bytes of
directly addressable program memory. The read strobe for external program
memory is the Program Store Enable Signal (PSEN) Data memory occupies a
separate address space from program memory. Up to 64K bytes of external
memory can be directly addressed in the external data memory space. The CPU
generates read and write signals, RD and WR, during external data memory
accesses. External program memory and external data memory can be
combined by an applying the RD and PSEN signal to the inputs of AND gate
and using the output of the fate as the read strobe to the external program/data
memory.
3.7.1 PROGRAM MEMORY:
The map of the lower part of the program memory, after reset, the CPU
begins execution from location OOOOh. Each interrupt is assigned a fixed
location in program memory. The interrupt causes the CPU to jump to that
location, where it executes the service routine. External Interrupt 0 for example,
is assigned to location 0003h. If external Interrupt 0 is used, its service routine
must begin at location 0003h. If the Interrupt 1 is not used its service location is
available as general-purpose program memory.
The interrupt service locations are spaced at 8 byte intervals 0003h for
External interrupt 0, OOOBh for Timer 0, 0013h for External interrupt l,001Bh
for Timer 1, and so on. If an Interrupt service routine is short enough (as is
often the case in control applications) it can reside entirely within that 8-byte
interval. Longer service routines can use a jump instruction to skip over
subsequent interrupt locations. If other interrupts are in use. The lowest
addresses of program memory can be either in the on-chip Flash or in an

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external memory. To make this selection, strap the External Access (EA) pin to
either Vcc or GND. For example, in the AT89C51 with 4K bytes of on-chip
Flash, if the EA pin is strapped to Vcc, program fetches to addresses OOOOh
through OFFFh are directed to internal Flash. Program fetches to addresses
lOOOh through FFFFh are directed to external memory.
3.7.2 DATA MEMORY:
The Internal Data memory is dived into three blocks namely,
• The lower 128 Bytes of Internal RAM.
• The Upper 128 Bytes of Internal RAM.
• Special Function Register

Internal Data memory Addresses are always 1 byte wide, which.implies

an address space of only 256 bytes. However, the addressing modes for internal
RAM can in fact accommodate 384 bytes. Direct addresses higher than 7Fh
access one memory space, and indirect addresses higher than 7Fh access a
different Memory Space.
The lowest 32 bytes are grouped into 4 banks of 8 registers. Program
instructions call out these registers as RO through R7. Two bits in the Program
Status Word (PSW) Select, which register bank, are in use. This architecture
allows more efficient use of code space, since register instructions are shorter
than instructions that use direct addressing. The next 16-bytes above the
register banks form a block of bit addressable memory space. The micro
controller instruction set includes a wide selection of single - bit instructions
and this instruction can directly address the 128 bytes in this area. These bit
addresses are OOh through 7Fh. either directs or indirect addressing can access
all of the bytes in lower 128 bytes. Indirect addressing can only access the
upper 128. The upper 128 bytes of RAM are only in the devices with 256 bytes
of RAM.

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 The Special Function Register includes Ports latches, timers, peripheral
controls etc., direct addressing can only access these register. In general, all
Atmel micro controllers have the same SFRs at the same addresses in SFR
space as the
AT89C51 and other compatible micro controllers. However, upgrades to
the AT89C51 have additional SFRs. Sixteen addresses in SFR space are both
byte and bit Addressable. The bit Addressable SFRs are those whose address
ends in 000B. The bit addresses in this area are 8 Oh through FFh.

3.8 ADDRESSING MODES:

DIRECT ADDRESSING:
In direct addressing, the operand specified by an 8-bit address field is in
the instruction. Only internal data RAM and SFR's can be directly addressed.

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INDIRECT ADDRESSING:
In Indirect addressing, the instruction specifies a register that contains the
address of the operand. Both internal and external RAM can indirectly address.

The address register for 8-bit addresses can be either the Stack Pointer or
RO or R1 of the selected register Bank. The address register for 16-bit
addresses can be only the 16-bit data pointer register, DPTR.

INDEXED ADDRESSING:
Program memory can only be accessed via indexed addressing this
addressing mode is intended for reading look-up tables in program memory. A
16 bit base register (Either DPTR or the Program Counter) points to the base of
the table, and the accumulator is set up with the table entry number. Adding the
Accumulator data to the base pointer forms the address of the table entry in
program memory.

Another type of indexed addressing is used in the" case jump "

instructions. In this case the destination address of a jump instruction is
computed as the sum of the base pointer and the Accumulator data.

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REGISTER INSTRUCTION:
The register banks, which contains registers RO through R7, can be
accessed by instructions whose opcodes carry a 3-bit register specification.
Instructions that access the registers this way make efficient use of code, since
this mode eliminates an address byte. When the instruction is executed, one of
four banks is selected at execution time by the row bank select bits in PSW.

REGISTER - SPECIFIC INSTRUCTION:

Some Instructions are specific to a certain register. For example some
instruction always operates on the Accumulator, so no address byte is needed to
point OT. In these cases, the opcode itself points to the correct register.
Instructions that register to Accumulator as A assemble as Accumulator -
specific Opcodes.

IMMEDIATE CONSTANTS:
The value of a constant can follow the opcode in program memory For
example. MOV A, #100 loads the Accumulator with the decimal number 100.
The same number could be specified in hex digit as 64h.

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3.9 PROGRAM STATUS WORD:

3.3..Program status word register in atmel flash micro controller

25
PSWO:
Parity of Accumulator Set By Hardware To 1 if it contains an Odd
number of Is, Otherwise it is reset to 0.

PSW1:
User Definable Flag

PSW2:
Overflow Flag Set By Arithmetic Operations

PSW3:
Register Bank Select

PSW4:
Register Bank Select

PSW5:
General Purpose Flag.

PSW6:
Auxiliary Carry Flag Receives Carry Out from Bit 1 of Addition
Operands

PSW7:
Carry Flag Receives Carry Out From Bit 1 of ALU Operands.
The Program Status Word contains Status bits that reflect the current
state of the CPU. The PSW shown if Fig resides in SFR space. The PSW
contains the Carry Bit, The auxiliary Carry (For BCD Operations) the two -
register bank select bits, the Overflow flag, a Parity bit and two user
Definable status Flags.
The Carry Bit, in addition to serving as a Carry bit in arithmetic
operations also serves the as the "Accumulator" for a number of Boolean

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Operations .The bits RSO and RSI select one of the four register banks. A
number of instructions register to these RAM locations as RO through R7.The
status of the RSO and RSI bits at execution time determines which of the four
banks is selected.
The Parity bit reflect the Number of Is in the Accumulator .P=l if the
Accumulator contains an even number of 1 s, and P=0 if the Accumulator
contains an even number of Is. Thus, the number of Is in the Accumulator plus
P is always even. Two bits in the PSW are uncommitted and can be used as
general-purpose status flags.

3.10 INTERRUPTS
The AT89C51 provides 5 interrupt sources: Two External interrupts,
two- timer interrupts and a serial port interrupts. The External Interrupts INTO
and INT1 can each either level activated or transition - activated, depending on
bits ITO and IT1 in Register TCON. The Flags that actually generate these
interrupts are the IEO and IE1 bits in TCON. When the service routine is
vectored to hardware clears the flag that generated an external interrupt only if
the interrupt WA transition - activated. If the interrupt was level - activated,
then the external requesting source (rather than the on-chip hardware) controls
the requested flag. TfO and Tfl generate the Timer 0 and Timer 1 Interrupts,
which are set by a rollover in their respective Timer/Counter Register (except
for Timer 0 in Mode 3).
When a timer interrupt is generated, the on-chip hardware clears the flag
that generated it when the service routine is vectored to. The logical OR of RI
and TI generate the Serial Port Interrupt. Neither of these flag is cleared by
hardware when the service routine is vectored to. In fact, the service routine

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normally must determine whether RI or TI generated the interrupt and the bit
must be cleared in software.
In the Serial Port Interrupt is generated by the logical OR of RI and TI.
Neither of these flag is cleared by hardware when the service routine is
vectored to. In fact, the service routine normally must determine whether RI to
TI generated the interrupt and the bit must be cleared in software.

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3.10.1 IE: INTERRUPT ENABLE REGISTER
EA ET2 ES ET1 EX1 ETO EXO
-
Enable bit = 1 enabled the interrupt
Enable bit = 0 disables it.

3.4 Iinterrupt enable register

Symbol Position Function

EA IE. Global enable /disable all
interrupts.
If EA= 0, no interrupt will be
Acknowledge. If EA= 1,
each interrupt source is
individually enabled to
disabled by setting or
clearing its enable Bit
- IE.6 Undefined/ reserved
ET2 IE.5 Timer 2 Interrupt enable Bit.
ES IE.4 Serial Port Interrupt enable
Bit.
ET1 IE.3 Timer 1 Interrupt enable Bit.
EX1 IE.2 External Interrupt enable Bit.
ETO IE.l Timer 0 Interrupt enable Bit.
EXO IE.O External Interrupt 0 enable
Bit.

3.2: Interrupt enable register

3.11 PIN DIAGRAM:

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 3.5: Pin diagram of micro controller

3.11.1 PIN DESCRIPTION

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VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each
pin can sink eight TTL inputs. When 1 s are written to port 0 pins, the pins can
be used as high impedance inputs. Port 0 may also be configured to be the
multiplexed low order address/data bus during accesses to external program
and data memory. In this mode PO has internal pull-ups. Port 0 also receives
the code bytes during Flash programming, and outputs the code bytes during
program verification. External pull-ups are required during program
verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1
output buffers can sink/source four TTL inputs. When Is are written to Port 1
pins they are pulled high by the internal pull-ups and can be used as inputs. As
inputs, Port 1 pins that are externally being pulled low will source current (IIL)
because of the internal pull-ups. Port 1 also receives the low-order address
bytes during Flash programming and verification.

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Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2
output buffers can sink/source four TTL inputs. When Is are written to Port 2
pins they are pulled high by the internal pull-ups and can be used as inputs. As
inputs, Port 2 pins that are externally being pulled low will source current (11L)
because of the internal pull-ups. Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data
memory that uses 16-bit addresses (MOVX @ DPTR). In this application it
uses strong internal pull-ups when emitting Is. During accesses to external data
memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of
the P2 Special Function Register. Port 2 also receives the high-order address
bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3
output buffers can sink/source four TTL inputs. When Is are written to Port 3
pins they are pulled high by the internal pull-ups and can be used as inputs. As
inputs, Port 3 pins that are externally being pulled low will source current (IIL)
because of the pull-ups. Port 3 also serves the functions of various special
features of the AT89C51 as listed below:

Port Pin Alternate Functions

P3.0 RXD(serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)

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 P3.3 INT1 (external interrupt 1)
P3.4 TO (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write
strobe)
P3.7 RD (external data memory read
strobe)
3.3: Port 3 - micro controller

Port 3 also receives some control signals for Flash programming and
verification.

RST

Reset input. A high on this pin for two machine cycles while the
oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte of the
address during accesses to external memory. This pin is also the program pulse
input (PROG) during Flash programming. In normal operation ALE is emitted
at a constant rate of 1/6 the oscillator frequency, and may be used for external
timing or clocking purposes. Note, however, that one ALE pulse is skipped
during each access to external Data Memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location

8EH. With the bit set, ALE is active only during a MOVX or MOVC

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instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable
bit has no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external program memory.

When the AT89C51 is executing code from external program memory, PSEN
is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external data memory.

EA/VPP

External Access Enable, EA must be strapped to GND in order to enable

the device to fetch code from external program memory locations starting at
0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will
be internally latched on reset. EA should be strapped to VCC for internal
program executions.

This pin also receives the 12-volt programming enable voltage (VPP)
during Flash programming, for parts that require 12-volt VPP.
XTAL1

Input to the inverting oscillator amplifier and input to the internal clock
operating circuit.
XTAL2

Output from the inverting oscillator amplifier, should be noted that when
idle is terminated by a hard ware reset, the device normally resumes program

34
execution, from where it left off, up to two machine cycles before the internal
reset algorithm takes control. On-chip hardware inhibits access to internal
RAM in this event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle should not be one that
writes to a port pin or to external memory.

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