IC PACKAGINGS

Dr. R. Ramaprabha (Sec A)

 ICs are at the core of a modern digital system

Many systems fit entirely on a single IC (SOC)
a single (15-mm)chip can hold several million gates
a simple 32-bit CPU can be realised in an area of 1mm

inexpensive plastic packages: <200 pins

packages with >1000 pins available (e.g. Xilinx FF1704: 1704-ball flip-chip BGA)

An electronic package is defined as that portion of an electronic structure that serves to

protect an electronic/electrical element from its environment and the environment from
the electronic/electrical element.

In addition to providing encapsulation for environmental protection, a package must also

allow for complete testing of the packaged device and a high-yield method of assembly
to the next level of integration.

Functions that a package must provide:

1) A structure to physically support the chip
2) A physical housing to protect the chip from the environment
3) An adequate means of removing heat generated by the chips or system
4) Electrical connections to allow signal and power access to and from the chip
5) A wiring structure to provide interconnection between the chips of an electronic system

1) Large reduction in signal count between on-chip wires and

package pins.

2) Typical IC wiring tracks on each of four metal layer signals can leave the chip (for
cheaper packages: 40..200)

3) Chips are often pad-limited. Peripheral-bonded chips. Chip area increases as the
square of the number of pads

SMT(surface-mount-technology)
SMT packages have leads that are soldered directly to corresponding exposed metal
lands on the surface of the circuit board

Elimination of holes
Ease of manufacturing (high-speed P&P)
Components on both sides of the PCB
Smaller dimensions
Improved package parasitic components
Increased circuit-board wiring density

SMT packages offer many benefits and are generally preferred.

PTH (pin-through-hole)
Pins are inserted into through-holes in the circuit board and
soldered in place from the opposite side of the board
Sockets available
Manual P&P possible

Plastic, ceramic, laminates (fiberglass, epoxy resin), metal

The most commonly used IC packaging material is PLASTIC
die-bonding and wire-bonding the chip to a metal lead frame
encapsulation in injection-molded plastic
inexpensive but high thermal resistance
Warning:
Plastic molds are hygroscopic
Absorb moisture
Storage in low-humidity environment. Observation of factory floor-life
can lead to hydrostatic pressure during reflow process.
Stored moisture can vapourise during rapid heating

Consequences can be:

1) Delamination within the package, and package cracking.
2) Early device failure.

Ceramic packaging
Consists of several layers of conductors separated by layer of ceramic
& Chip placed in a cavity & bonded to the conductors
Metal lid soldered on to the package
sealed against the environment
high permittivity of alumina(er=10)
Note: High permittivity leads to higher propagation delay!
expensive

PLASTIC DUAL INLINE

PACKAGE(PDIP)

SC-70
SMALL
OUTLINE IC
(SO14)

PDIP14

THIN SHRINK SMALL

OUTLINE
(TSSOP14)

PLASTIC LEAD
CHIP CARRIER
(PLCC 28)

THIN QUAD FLAT

PACKAGE (TQFP 32)

Shown: BGA54
Available pin count >1700
Advanced IC package for high-density
low-profile applications
Chip-scale package (CSP)
Dimensions: 8.0mm x 5.5mm x 1.4mm
Pin-to-pin: 0.8mm
Low lead inductance

Flip Chip BGA Package

Signal and power distribution are accomplished through leads and wire bonds, etc.
Heat dissipation is accomplished through leads and chip support
Support and protection are accomplished through the Wiring Board/substrate, or
external package, and Resin, or plastic encapsulant.

Single electronic package

containing more than one IC
which are connected through a
substrate.

3D Stacking Three-Dimensional Stacking:

# Chips are stacked together.

# One of the first commercial efforts to stack chips within a single package mated flash
memory with static random-access memory (SRAM).
# The industry desire to reduce product size, weight, and cost while providing extra
performance (shorter interconnects that lower capacitance and inductance,reducing
crosstalk, and lower power consumption) and increasing functionality, has driven 3D
packaging of both chips and packages.

Everyday there is scope for improvement. May be we will soon be in a

situation to make even a deadly weapon only with chips.
Chips no doubt is a boon for us. There will be a time in history in which IC
will rule the world.

>>>
Looking forward..