Topic-II

8086 Microprocessor & its

Architecture
T1. Barry B Brey, The Intel Microprocessors .Pearson, Eight Ed. 2009. Chapter 2
R1. Douglas V Hall, Microprocessor and Interfacing, TMH, Second Edition. Chapter 2

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EVOLUTION OF MICROPROCESSOR

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16 bit Microprocessor

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32 bit Microprocessor

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Variations of 8086 - 8088

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Characteristics of the X86 family

CISC
Instructions broken up into micro operations
Complex instruction decoder

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Little Endian format

Binary data are stored as a byte (8 bits), word (16 bits),
or double word (32 bits) in a computer system.
These data may be unsigned or signed.
Signed negative data are always stored in the two's
complement form.
Data that are wider than 8 bits are always stored using
the little endian format.
The assembler directives DB or BYTE define bytes,
DW or WORD define words, DD or DWORD define
doublewords, and DQ or QWORD define quadwords.
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Little Endian & Big Endian

A word (16-bits) is formed with two bytes of data.
The least significant byte always stored in the lowestnumbered memory location.
Most significant byte is stored in the highest.
This method of storing a number is called the little
endian format.
Alternate method is called the big endian format.
Numbers are stored with the lowest location containing
the most significant data.
Not used with Intel microprocessors.
The big endian format is used with the Motorola family
of microprocessors.
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8086 Microprocessor

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Bus Interface Unit (BIU)

handles all transfers of data and addresses on the buses for
the execution unit

Execution Unit (EU)

Actual function is performed here
- instructs BIU from where to fetch an instruction
- decodes it,
- executes it
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EU Operation
1. Fetch an instruction from instruction

queue
2. According to the instruction, EU control
logic generates control signals.
(This process is also referred to as instruction
decoding)

AH
BH
CH
DH

AL
BL
CL
DL
SP
BP
SI
DI

3. Depending on the control signal,

EU performs one of the following

operations:
An arithmetic operation

ALU

A logic operation
Storing a data into a register
Moving a data from a register

Flag register

General purpose
register

ALU Data bus

(16 bits)

EU
control

instruction
1011000101001010

Changing flag register

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8086 Microprocessor

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Block diagram of 8086

Address bus (20 bits)

Execution Unit
(EU)

AH

AL

BH

BL

CH

CL

DH

DL

General purpose
register

SP

Segment
register

BP
SI
DI

CS

Data bus
(16 bits)

DS
SS

ALU Data bus

(16 bits)

ES
IP
Bus
control

ALU

Instruction Queue

External bus

EU
control
Flag register

Bus Interface Unit (BIU)

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X86 -ISA
Register Organisation

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8086 Register organization

General purpose Registers.

- AX, BX, CX, DX

Segment Registers.
- CS, DS, SS, ES

Pointer and Index Registers.

- IP, BP, SP
-SI, DI

Flag Registers
-FLAGS

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Function wise 8086 Register

organization

Multipurpose Registers.
- AX, BX, CX, DX, BP, DI, SI

Special Purpose Registers.

- IP, SP, FLAGS

Segment Registers.
- CS, DS, SS, ES

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8086 Register organization

IP : INSTRUCTION POINTER

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General Purpose Registers

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General Purpose Registers

BX : offset storage for

forming physical address
CX : default counter in case
of string and loop
instructions

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Pointer and Index Registers

IP : INSTRUCTION POINTER

Pointer and
Index Group

SP

Stack Pointer

BP

Base Pointer

SI

Source Index

DI

Destination Index

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Pointer and Index Registers

Pointer (IP, BP, SP) : contain offset within a particular
segment for forming physical address.
IP contain offset within Code segment.
BP and SP contain offset with Stack segment.
Index (SI, DI) : used as general purpose as well as contain
offset with Data and Extra segment respectively.
Index registers are useful for string manipulation.

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Flag Register

FLAGS
- Status Flag
- Control Flag

FLAG Register

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16 bit Flag Register in 8086

Flag register contains information reflecting the current status of a

microprocessor. It also contains information which controls the

operation of the microprocessor.
15

Control

IF:
DF:
TF:

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OF DF IF TF SF ZF AF PF CF

Status Flags

Flags

Interrupt enable flag

Direction flag
Trap flag

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CF:
PF:
AF:
ZF:
SF:
OF:

Carry flag
Parity flag
Auxiliary carry flag
Zero flag
Sign flag
Overflow flag 3-23

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Flags
Conditional/ status Flags: They are set/reset by the processor to indicate
certain condition that arises during the execution of a program. (the lower
byte of 16 bit along with overflow flag.)
- Reflects the result of operation performed by CPU.

Control Flags: they are deliberately set/reset by the programmer to control

certain operations of the processor. (higher byte of excluding overflow)

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Status Flags
Carry - unsigned arithmetic out of range (set or C=1)
Parity - no. of 1 s is an even number (set or P=1)

Auxiliary Carry - carry from bit D3 to D4. (set or AC=1)

Zero - result is zero (set or Z=1)
Sign - result is negative for signed computation. (set or S=1)

Overflow - signed arithmetic out of range (set or O =1)

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Status Flags

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Control Flags
IF: Interrupt enable flag (If IF is set, IF=1 CPU will
serve the interrupts from external device)
DF: Direction flag used for string manipulation of
instructions. (If DF is set, DF=1, string will process
from highest towards lowest address) (opposite of little
endian format)

TF: Trap flag (If TF is set, TF =1, processors enter

into single step execution ) This flag normally is used
for debugging of program.
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Segment Registers

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Segment Registers:
Segment register stores upper 16 bits of its starting address.
(base address)
code segment registers - holds base address from where
instructions are coming (base address of memory location in code
segment)
stack segment registers - stores base address of stack while a
subprogram is executed. (base address of memory location in
stack segment)
data segment registers - holds base address of memory location
where data stored (base address of memory location in data
segment)
extra segment registers - holds base address of memory location
if extra data required (another data segment)
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Stack Segment
The CPU use the stack for temporarily
storing important data. For example the
content of register that will be require
at later stage.
The stack grows down i.e. the data is
pushed onto the stack memory
locations with decreasing address.
When the data is required by CPU in
later stage they will be popped off from
the stack.

Microprocessor System Design

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Physical address calculation

The total addressable memory size is 1Mega Byte memory.

The complete 1MB memory is divided into 16 logical segments
and each segment contains 64Kbytes of memory.
While addressing any location in the memory bank the physical
address is calculated from two parts ; the first is segment address
and the second is offset address.

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8086 Memory Address Space

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Physical address calculation

The segment register contains the 16 bit segment base address
related to different segment.
Any of the pointer or index registers or BX may contains the
offset of the location of the address.

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Physical address calculation

Advantage of this is : instead of maintaining 20 bit register for a
physical address the processor will maintain two 16 bit registers
which are within the word length capacity of machine.
All segments are like logical segments
They may or may not be physically separated .

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Physical address calculation

At any given time the 8086 works with only four 64 KB
segments within this 1MB range.
A 64 KB segment can be located anywhere within the 1 MB
space, but the address will always start at an address with zeros in
the lowest 4 bits.

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8086 Memory Address Space

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Physical address calculation

This constraint was put on the location of segments so that it is
only necessary to store and manipulate 16- bit data .
The part of the segment starting address that is stored in
segment registers is known as segment base address.

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Programmers model of 8086

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Segmentation
Physical memory address pointed by
segment (range: 0000H to F000H) and
offset (range: 0000H to FFFFH) pair is calculated as:

Physical address = (<segment> * 16) + <offset>

= Segment address will shift left bitwise 4 times

+ offset address
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Segmentation

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Default 16-bit segment and offset

address combinations
SEGMENT

OFFSET

CS

IP

SS

SP (or) BP

STACK ADDRESS

DS

BX, DI, SI,

an 8-bit number,
16 bit number
DI
for string Instructions

DATA ADDRESS

ES

SPECIAL
PURPOSE
INSTRUCTION
ADDRESS

STRING
DESTINATION
ADDRESS

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Segmentation in 8086
(Physical address calculation)

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Programmers Model

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Segmentation

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Physical Address

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Advantage of Segmentation

Allows the memory capacity to be 1MBytes although the

actual addresses to be handled are of 16-bit size.

Allow the placing of code , data and stack portions of the

same program in different parts (segments) of memory, for
data and code protection

Relocation: Permits a program and/or its data to be put into

different areas of memory each time the program is
executed.

Program - Specify only offset

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Arithmetic Logic Unit (ALU)

A

n bits

F
n bits

Carry
Y= 0 ?

A>B?

0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1

A+B
A -B
A -1
A and B
A or B
not A

Signal F control which function will be conducted by ALU.

Signal F is generated according to the current instruction.
Basic arithmetic operations: addition, subtraction,
Basic logic operations: and, or, xor, shifting,
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X86 -ISA
8086-80486 Programmers Model
BIU

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Memory Addressing

Real
- Access only 1MB of memory
- Only 20 Address lines required.

Protected
- support multitasking
- memory management protection enabled

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Programmers Model BIU

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Programmers Model- MPR

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80X86 Summary

BIU (Bus Interface Unit)

EU (Execution Unit)

provides hardware function for generation of the memory and

I/O addresses for the transfer of data between itself and the
outside world.

receives program instructions code and data from the BIU,

executes these instructions and store the results in the general
purpose registers.
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