chapter

P ROCESSOR /C ACHE AND S YSTEM

S UPPORT
Host Bus (Northbridge)
Pentium II CPU/Cache
The computer supports only Intel Pentium II processors housed in the MP2 (minicartridge) form factor. A general feature list is as follows:

Full SMI (System Management Interrupt)

Fully static (support Stop Grant and Stop Clock states)
66/100 MHz bus interface to the system
32 bit Address Bus
64 bit Data Bus
512 KB on-board write-back cache (Mobile Deschutes processors)
256 KB on-chip write-back cache (Dixon processors)
Capability of executing two instructions per clock via two pipelined integer units
Multimedia extension (MMX) register set

The computer uses the notebook versions of the Pentium II processor in a 420-pin minicartridge (MP2) package. The notebook versions all offer Intels Voltage Reduction
Technology (VRT). VRT is used to reduce the voltage to the core of the processor,
which reduces power consumption and heat. The processor modules have three power
planes: a core power plane at a pre-selected voltage based on the CPU type, a cache
power plane at 3.3 V, and an I/O power plane that is always at 1.8 V.

Processor/Cache and System Support 3-1

The MP2 has an integrated L2 cache controller, containing either 512 KB of dedicated
cache memory (Mobile Deschutes) or 256 KB of on-chip cache memory (Dixon) which
supports a direct-mapped, write-through scheme using pipelined burst SRAM.
The processors supported by the computer are listed in the following table:

Table 3-1
Supported Processors
Processor

CORE VCC

I/O VCC

EXT CLK

POWER

MP2/266
MP2/300
MP2/333
MP2/366

1.8 V (+/- 135 mV)

1.6 V (+/- 135 mV)
1.6 V (+/- 135 mV)
1.6 V (+/- 135 mV)

1.8V (+/- 90 mV)

1.8 V (+/- 90 mV)
1.8 V (+/- 90 mV)
1.8 V (+/- 90 mV)

66 MHz
66 MHz
66 MHz
66 MHz

9.5 Watts
8.9 Watts
8.6 Watts
9.5 Watts

82443BX
The Intel 440BX PCI-based chipset is optimized for portable systems with stringent
form factor and power consumption requirements. It is made of two components named
the 82443BX and PIIX4E. The 82443BX makes up the Northbridge (control between
the PCI bus and the CPU and AGP buses). The PIIX4E is referred to as the
Southbridge (control between the PCI bus and the ISA bus). This section deals with
the 82443BX.
The 82443BX integrates the CPU, AGP, PCI, and DRAM bus interfaces. This includes
the DRAM controller, AGP bus arbiter, PCI bus arbiter, power management, and the
host (CPU) interface.
The 82443BXs data buffer steers and buffers data between the four interfaces: 64-bit
CPU, 64-bit DRAM, 32-bit AGP, and 32-bit PCI. The data flow can be CPU-to-PCI,
CPU-to-AGP, CPU-to-DRAM, AGP-to-DRAM, or PCI-to-DRAM.

3-2 Processor/Cache and System Support

Power Planes
The 82443BX utilizes two power planes, plus reference signals for use in
communication to the Pentium II CPU (GTLREFA,B; VTTA,B) and PCI (REFVCC5)
buses. Both planes remain on in Standby (S1) and Suspend-to-RAM (S3) states. The
82443BX has leakage control so that no back powering of other system functions
occurs in Suspend. Table 3-2 lists the 82344X power planes.

Table 3-2
82443X Power Planes
Plane

VCC OPTIONS

Selection

Description

VCC
VCCAGP
GTLREFA,B
VTTA,B
REFVCC5

3.3V
3.3V
0.55VTT
CPU selected
3.3V

PMVCC3
PMVCC3
0.55(CPUCOREVCC)
CPUCOREVCC
PMVCC3

Main power
AGP bus power
GTL buffer (switching) voltage
GTL threshold (clamp) voltage
PCI 5V tolerant level (not used)

Reset Interface
The 82443BX reset function is an integral part of the Suspend/Resume functions. The
82443BX supports the normal reset function in a desktop platform, as well as the
various power-up reset and resume reset functions in the mobile platform.
The PIIX4E integrates the system reset logic for the system. The PIIX4E generates
CPURST, PCIRST#, and RSTDRV during power up (PWROK) and when a hard reset
is initiated through the RC register, as well as during certain power management
resume operations.
The 440BX chipset has two separate reset inputs: RCIN# and PWROK; and five reset
outputs: PCIRST#, CPURST#, SUS_STAT#, and INIT#.
RCIN#: In the computer, this signal is used to generate a reset from the H8.
PWROK: An RC delay from the enabling of SYSVCC3. During the period when
RCRST# is de-asserted and PWROK is not yet asserted, RSTDRV and CPURST# are
asserted. When PWROK becomes asserted, RSTDRV and CPURST de-assert causing a
system reset.

Processor/Cache and System Support 3-3

Table 3-3
440BX Reset Outputs
Signal

Assert w/
PCIRST#

System Devices or
Buses Affected

Source

Description

PCIRST#

PIIX4E

CPURST#
RSTDRV

Always
Always

PCI bus, 82443BX, NB,

PIIX4E
CPU
ISA bus / X-Bus
devices

SUSSTAT#

N/A

INIT#

No

Used in power-up sequence,

resume from S2R or S2D.
CPU reset signal.
ISA bus reset. Directly derived
from PCIRST#. Resides in PIIX4E
main voltage well.
SUSSTAT# signals a Suspend
mode entry/exit. This signal
originates from the PIIX4E
Suspend voltage well.
CPU soft reset generated by
PIIX4E.

82443BX
PIIX4E

PIIX4E Only

CPU

PIIX4E

CPURST# is generated by the 82443BX in the following case:

CPURST# is always asserted if PCIRST# is asserted.
CPURST# is asserted during resume sequence from Standby (CRst_En= 1).

The 82443BX de-asserts CPURST# 1 ms after detecting the rising edge of PCIRST#.
The CPURST# is synchronous to the host bus clock.
PCIRST# must be asserted when the system resumes from low power mode of which
power is removed, including resume from Suspend-to-RAM or Suspend-to-Disk and
power up sequence. In these cases, CPURST# is activated with the assumption that
CPU power is removed as well and in order to enforce correct resume sequence.
When resuming from Standby, the PCIRST# and CPURST# are typically not used to
speed up the resume sequence. The option to reset the CPU, in this case, is available by
using the CRst_En configuration bit option.
When the user performs a soft reset, the PIIX4E drives SUSTAT# to the 82443BX.
This forces the 82443BX to switch to a Suspend refresh state. When the BIOS attempts
to execute cycles to DRAM, the 82443BX cannot accept these cycles because it
believes that it is in a Suspend state. After coming out of reset, software must set the
Normal refresh enable bit (bit4, Power Management Control register at Offset 7Ah) in
the 82443BX before doing an access to memory.

3-4 Processor/Cache and System Support

Power-On Configuration
The 440BX chipset uses power-on registers to define system configuration variables
that must be set by hardware options. All signals used to select power-on options are
connected to either internal pull-down or pull-up resistors of minimum 50K/maximum
150 K ohms, which select a default mode on the signal during reset.
To enable different modes, external pull-ups or pull-downs (the opposite of the internal
resistor) of approximately 10 K ohm can be connected to particular signals. These pullup or pull-down resistors are connected to the PMVCC3 power supply. During normal
operation of the 82443BX, including while it is in Suspend mode, the paths from GND
or PMVCC3 to internal strapping resistors are disabled to effectively disable the
resistors. In these cases, the MAB# lines are driven by the 82443BX to a valid voltage
level.
Table 3-4 lists the Power On options that are loaded into the 82443BX during cold
reset. The 82443BX is required to float all the signals connected to straps during cold
reset and keep them floated for a minimum of four host clocks after the end of cold
reset sequence.

Table 3-4
82443BX Power On Options During Cold Reset
Line

Settin
g

MAB13#
MAB12#
0
MAB11#
1
MAB10
0
MAB9#
0
MAB8#
MAB7#
0
MAB6#
1
**
default selection

Description
Reserved
Host Frequency Select
In-Order Queue Depth Enable
Quick Start Select
AGP Disable
Reserved
Memory Module Configuration
Host Bus Buffer Mode Select

Notes

**

0 = 60/66 MHz, 1 = 100 MHz

**
0 = non-pipelined, 1 = pipelined (8-deep)
**
0 = normal mode, 1 = Quick Start mode
**
0 = AGP enabled, 1 = AGP disabled
**

0 = normal (BX), 1 = 430TX-compatible

**
0 = desktop GTL+, 1 = mobile GTL+

When resuming from Suspend, even while PCIRST# is active, the MAB# lines remain
driven by the 82443BX and the strapping latches maintain the value stored during the
cold reset.

Clock Interface
The 82443BX requires two clock inputs which are CPUCLK (66 MHz) and
PCICLK_443BX (33 MHz). The CPUCLK signal is buffered and driven to three output
pins: DCLKOUT, DCLKWR, and DCLKRD.
During certain conditions the CPUCLK signals may be stopped and restarted. The
CPUCLK can be stopped in the Sleep and Deep-Sleep modes and restarted when a
primary activity is detected. The CPUCLK signal is driven in the On and Standby
states.
The PCICLK is always CPUCLK / 2.

Processor/Cache and System Support 3-5

CPU Interface
The 82443BX Northbridge supports Pentium II processors including the Mobile
Deschutes and Dixon families.
CPU address pipelining is supported. x-1-1-1 CPU writes can be supported up to 100
MHz. Write buffers exist for CPU-to-DRAM, CPU-to-AGP, and CPU-to-PCI cycles.
Read re-ordering is supported for these buffers.

DRAM Controller
The DRAM controller supported by the 82443BX allows up to four 64-bit SDRAM
banks for 512 MB (1 GB for Registered DIMMs). The DRAM controller supports
Extended Data Output (EDO) DRAM and Synchronous DRAM (SDRAM).
For specifics on the computers main memory, refer to the System Memory chapter.

Secondary Cache (L2)

The Pentium II processor supports a 512 KB second level cache via a backside bus
(BSB) interface or a 256 KB on-chip cache. The processor module handles all control
for the L2 cache. The computer uses this built-in cache memory of the MP-2 module.
No external cache control logic or tag RAM memory is required.

PCI Bus
The PCI bus is a 32-bit multiplexed address/data bus that is used for high-speed
components. The PCI bus operates at half or one third of the CPU external clock rate.
All models use a 66 MHz external clock, therefore, the PCI bus is clocked at 33 MHz.
Bursting is supported from PCI bus masters into main memory.

AGP Bus
The 82443BX supports a dedicated 66 MHz Accelerated Graphics Port (AGP) video
bus. Like the PCI bus, the AGP bus is a 32-bit multiplexed address/data bus, but it
operates at 66 MHz full or 2/3-CPU bus speeds, with bursting support into main
memory. The AGP bus can only have two devices on it: the PCI-to-AGP bridge and the
video controller.
Devices on the AGP bus can run in two modes:
1X speed 66 MHz, one data window per clock pulse
2X speed 66 MHz, data windows on both rising and falling clock edge, 133 MHz
throughput

The computer supports both modes of operation and is compatible with the AGP
Specification, Rev. 1.0.

3-6 Processor/Cache and System Support

Operation in 2X mode can reach peak transfer bandwidths in excess of 500 MB/sec. (In
comparison, PCI graphics controllers are limited to a peak bandwidth of 132 MB/s,
which they must share with other PCI devices.) In addition, the video system supports
AGPs pipelined sideband protocol, which improves the sustained bandwidth of data
transfers, further enhancing video performance.
From a system-architecture point of view, the AGP bus looks exactly like a secondary
PCI bus, and the AGP interface in the 82443BX appears to include a standard PCI-toPCI bridge. The main behind-the-scene differences are: the graphics controller is in
sole possession of this bus, so bus arbitration is minimized; and the AGP bus has a
direct aperture into system DRAM, allowing quick access to large blocks of memory
for 3D texture maps.

ISA Bus (Southbridge)

PIIX4E (82371EB)
The PIIX4E serves as the Southbridge providing a bridge between the PCI and ISA
buses, and the logic to support master and slave cycles on both PCI and ISA buses. It
also serves as the master power management controller for the 440BX chipset and
offers a mechanism to generate up to 53 general purpose I/Os.

Power Planes
The PIIX4E has a flexible power plane structure to support a wide variety of system
configurations. Four independent power planes are used plus a reference signal for
communication to the ISA and PCI buses:

Table 3-5
PIIX4 Power Planes
VCC
VCCRTC
VCCSUS
VCCUSB
VREF
**

VCC OPTIONS

Selection

Description

3.3V
3.3V
3.3V
3.3V
5V or 3.3V

SYSVCC3
DCDC3 **
DCDC3
SYSVCC3
SYSVCC3

Core voltage supply

RTC/CMOS logic power
Suspend Well logic supply
USB logic supply
External logic voltage reference

battery-backed version of selected voltage

Processor/Cache and System Support 3-7

Clock Interface
Four clock signals are inputs to the PIIX4E: PCICLK_PIIX, USBCLK, 32KHZ, and 14
MHZ_PIIX4.
PCICLK_PIIX is used to create all PCI control signals. The PIIX4E also supplies the
SYSCLK output for ISA devices, derived from PCICLK_PIIX.
USBCLK is used to derive all of the signals for the USB host adapter.
32 KHZ is used to control the on-board RTC.
14MHZ_PIIX4 is used to control the 8254-compatible timer in the PIIX4E.

Reset Interface
PCIRST# is used as the master reset signal for the PIIX4E.

System Management Mode (SMM)

The PIIX4E provides a flexible SMM interface for both software and hardware. It can
generate an SMI from many sources including the following:
Power management events
External pins
Timer time-outs
Software triggered events

The SMM base address is defined as 000D0000H-000EFFFFH. The physical memory

space used for SMM memory is at 000A0000H-000BFFFFH in DRAM.
SMRAM accesses are always marked as write-through to the L1 cache. SMRAM
cannot be accessible by PCI or AGP masters.
The only external pin that generates an SMI is SCPSMI#.
SCPSMI#: This signal, generated from the SCP (H8), is used for all wake-up sources
from Suspend (Ring, Alarm, Suspend/Resume button, Lid switch, etc.). It is also used
for any event that indicates through the SCP that an SMI is needed.

3-8 Processor/Cache and System Support

Power Management Controller

The PIIX4E has a number of power management functions designed to maximize
system battery life:

Enhanced clock control

Local/global monitoring support and PMI generation for 14 individual on-board and
system devices
Advanced primary and secondary activity monitors
Low-power states to provide battery conservation -- Power-On Suspend, Suspendto-DRAM, and Suspend-to-Disk. (These states and how they are applied to are
discussed elsewhere in this document.)
Hardware-based thermal management permits software-independent entrance to
low-power states
Full support for the Advanced Configuration and Power Interface (ACPI)
Specification
Dedicated pins to monitor external events: -- notebook lid, Suspend/Resume button,
battery low indicators, etc.
Accepts power management inputs from the SCP via the SCPSMI# input

PCI to ISA Cycle Translation

The PIIX4E has three physical address spaces: Memory, Input/Output, and
configuration address spaces. A subtractive decoding scheme is implemented in
PIIX4E at power up, and is used for ISA bus targets, although positive decoding is
performed for interrupt acknowledge and PCI configuration. If a second ISA bus is
added via the docking interface the PIIX4E can be placed in a positive decode mode
only. There can only be one subtractive decode device in a system.

ISA Bus Interface

Although the computer is a PCI based system, areas of ISA bus support are still
required in the notebook and peripherals. In order to provide ISA bus support in the
PCI system, a PCI-to-ISA bridge must be used to translate between the ISA and PCI
buses. The PIIX4E provides this function.
The PIIX4E can be configured for a full ISA bus or a subset of the ISA bus called the
Extended IO (EIO) bus. The use of the EIO bus allows unused signals to be configured
as general purpose inputs and outputs. The PIIX4E provides byte-swap logic, I/O
recovery support, wait-state generation, and SYSCLK generation. Chip selects are
provided for the Keyboard Controller/SCP, BIOS, Real Time Clock, and a second
microcontroller, as well as two programmable chip selects.
The PIIX4E can be configured as both a subtractive decode PCI-to-ISA bridge and as a
positive decode bridge for PCI functions, such as the IDE controller and USB bus.

Processor/Cache and System Support 3-9

General Purpose Inputs

The PIIX4E provides up to 22 general purpose input (GPI) signals. These GPIs can be
used to directly monitor system logic and external inputs. The read-only registers that
store the state of these inputs are located in the PIIX4E. Please see the 82371AB
(PIIX4) design guide and 82371EB (PIIX4E) addendum for further information.
Some of these pins are multiplexed with other PIIX4E functions. Depending on the
PIIX4E features used, some of the GPIs may not be available to the system. Three GPIs
are used for their alternative function, leaving 19 GPIs available to the system.
The GPI usage is listed in Table 3-6.

Table 3-6
General Purpose Inputs
GPI

Signal Name

Description

High

Low

GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPI7
GPI8
GPI9
GPI10
GPI11
GPI12
GPI13
GPI14
GPI15
GPI16
GPI17
GPI18
GPI19
GPI20
GPI21

IOCHK#
PME#
GPI2
GPI3
GPI4
GPI5
GPI6
SERIRQ
H8_SCI
BATLOW#
H8_WAKE
SMBALERT#
RING#
CRISIS
SECURITY
GPI15
GPI16
GPI17
GPI18
PCBREV0
PCBREV1
PCBREV2

Reserved by PIIX4E
PCI Power Management Enable input
Not used
Not used
Not used
Not used
Not used
Reserved by PIIX4E
H8 ACPI wakeup source
Battery low level indicator
H8 Resume source
Reserved by PIIX4E
Wake-on-Ring input
Crisis Recovery indicator
Clears password data
Not used
Not used
Not used
Not used
PCB revision indication
PCB revision indication
PCB revision indication

Normal
Wakeup
Normal
Normal
Normal
1
1
1

Battery low
Normal
Modem ring
Recovery mode
Clear password
0
0
0

3-10 Processor/Cache and System Support

General Purpose Outputs

The PIIX4E provides up to 31 general purpose output (GPO) signals. These GPOs can
be used to directly monitor and control system logic. The read/write registers that store
and change the state of these outputs are located in the PIIX4E. Please see the
82371AB (PIIX4) design guide and 82371EB (PIIX4E) addendum for further
information.
Some of the GPOs are multiplexed to provide other PIIX4E functions. Depending on
the features used in the PIIX4E, some GPOs may not be available to the system. Nine
GPOs are used for their alternative function, leaving 22 GPOs available to the system.

Table 3-7
General Purpose Outputs
GPO

Signal Name

Description

High

Low

GPO0
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
GPO8
GPO9
GPO10
GPO11
GPO12
GPO13

GPO0
LA17
LA18
LA19/AUD_PWR
LA20/DIMM1_EN
LA21/DBAY_PWR
LA22
LA23
VGA_STNDBY#
IDEVCCON#
RESETIDE#
12VON_OFF#
BAYIDEEN
DISKETTE
DRIVEVCCEN#
DISKETTE
DRIVE_DENSEL
SYSVCCON
PMVCCON
CPUSTP#
PCISTP#
H8_NMI
SUS_STAT1#
SUS_STAT2#
GPO22
GPO23
FORCERST#
FAN_ON
KBCCS#
USBEN#
CB_SUSP#
BOOTVPPON#
FLASHVPPON#

Not used
Reserved by PIIX4E
Reserved by PIIX4E
Audio power enable
DIMM1 select
Dock Bay power enable
Reserved by PIIX4E
Reserved by PIIX4E
Video controller power-down indicator
IDE power enable
IDE reset
12V power enable
Bay IDE power enable
Bay DISKETTE DRIVE power enable
DISKETTE DRIVE density select

Audio power on
Enabled
Dock Bay on
Normal
IDE power off
Normal
12V on
Bay power on
DISKETTE DRIVE
power off
Mode 3

Audio power off

Disabled
Dock Bay off
Low power
IDE power on
Reset
12V off
Bay power off
DISKETTE DRIVE
power on
Normal

SYSVCC3 enable
PMVCC3 enable
Reserved by PIIX4E
Reserved by PIIX4E
NMI input
Reserved by PIIX4E
Reserved by PIIX4E
Not used
Not used
Force system reset
Cooling fan enable
Reserved by PIIX4E
USB power enable
CardBus Suspend power
Boot Block VPP enable
Flash VPP enable

SYSVCC3 on
PMVCC3 on
Normal
Enabled
USB power off
CB power off
Normal
Programming

SYSVCC3 off
PMVCC3 off
Reset
Disabled
USB power on
CB power on
Programming
Normal

GPO14
GPO15
GPO16
GPO17
GPO18
GPO19
GPO22
GPO23
GPO22
GPO23
GPO24
GPO25
GPO26
GPO27
GPO28
GPO29
GPO30

Processor/Cache and System Support 3-11

System Interrupt (IRQ) Map

The interrupt usage of a PCI/PnP system can vary considerably and is based on the
commands given by the OS during hardware detection and configuration. The
following default interrupts are set on the system. Some interrupts, while immovable,
can be disabled, freeing up the resource. Table 3-8 lists the system interrupts.

Table 3-8
System Interrupts
IRQ

Use

Move

Disable

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

System timer
Keyboard
Cascade
IrDA (default disabled)
Serial Port
Audio
Diskette controller
Printer (Parallel) Port
Real-Time Clock
ACPI
UMI
CardBus/USB
PS/2 Mouse
Numeric Processor
Primary IDE controller
Secondary IDE controller

No
No
No
Yes
Yes
Yes
No
Yes
No
No
Yes
No
No
No
No
No

No
No
No
Yes
Yes
Yes
No
Yes
No
Yes
Yes
Yes
No
No
No
Yes

Real Time Clock (RTC)

The RTC functions are provided in a special area of the PIIX4E. This area contains low
power CMOS circuitry that keeps the current time and date and a low power CMOS
storage area for system settings. A 32.768kHz crystal is used to clock and update the
time and date. The RTC has system wakeup capability for resume on alarm, including
Wake on Day-of-Month capability (ACPI and OnNow requirement). This alarm can be
programmed via SETUP to wake up the system from Standby and Suspend-to-RAM
states.
The PIIX4E has 256 bytes of battery-backed CMOS memory. The first 128 bytes are
the standard CMOS locations, of which the first 14 are used for clock/calendar control.
The second 128 bytes can be used for extended CMOS functions.

3-12 Processor/Cache and System Support

Read Only Memory (ROM)

The System Power Management, Video BIOS, as well as the setup program reside in
Read only Memory (ROM). The ROM is implemented using one 4 Mbit (512 Kx8 bit)
Intel 28F004BV boot block FLASH EPROM device. The flash consists of a 16 KB
boot block section, two 8 K parameter sections, and 480K of the main section. The 16
KB boot block section stores the initial POST routines. The two 8 K parameter sections
are not used. The main 480 K holds the remainder of the code. Normal BIOS upgrades
would only update the 480 K main section.
Implementing the BIOS ROM using FLASH technology allows the ROM to be
reprogrammed dynamically by a FLASH update program. The FLASH update utility is
supplied by Phoenix Technologies (suppliers of the system BIOS). The utility checks
that AC power is applied to the unit and no memory management drivers are loaded
before reprogramming of the BIOS is allowed. If a failure occurs during the
reprogramming (AC power is lost and the main battery is dead), the computer becomes
inoperable and the FLASH ROM needs to be crisis recovered.
5 V (DCDC5) is needed for erasing and programming the ROM. There are two
hardware signals that are used to program the ROM: FLASHVPPON and
BOOTVPPON. FLASHVPPON enables 5 volts to the ROM VPP pin and allows the
480K main section and the two 8K parameter sections to be programmed but cannot
allow programming of the boot section. BOOTVPPON unlocks the boot block for
erasure and programming. The two signals mentioned in this section (FLASHVPPON
and BOOTVPPON) are generated by the PIIX4E and are defined in the PIIX4E section
of this specification.
NOTE: FLASHVPPON must be enabled prior to setting BOOTVPPON (and held on
during the entire boot block programming cycle) in order to properly erase and program
the boot block.
Please refer to the Maintenance and Service Guide for instructions on how to re-flash
the system BIOS.

System Control Processor (SCP) Subsystem

The SCP device is the Hitachi H8 (HD647343) in a 100-pin PQFP package. This
device performs many critical system functions and is referred to as the System Control
Processor (SCP). It is often referred to as the H8 in this specification.
The H8 is a single-chip embedded controller with an H8/300 CPU core, a 16-bit freerunning timer, two 8-bit timers, two PWM timers, a serial communication interface, an
A/D converter, a keyboard controller, host CPU interface, power management features,
and I/O ports. The HD647343 has 32Kbytes internal EEPROM and 1Kbytes internal
RAM. It can be reprogrammed in the system if required.

Processor/Cache and System Support 3-13

The SCP resides on the ISA bus, and its external crystal runs at 10 MHz. The SCP
resides on the DCDC3 power plane, which always receives power as long as the main
battery or the back-up battery has power. The H8 has internal power management states
which the SCP transitions to during periods of system inactivity. In the lowest power
savings state during system Suspend or Off, the SCP disables its external crystal and
can only be woken up by a transition on its interrupt pins.
SCP duties include the following:

Supports two external PS/2 ports (normally for mouse and keyboard control)
PS/2 interface to the touchpad pointing device
Internal keyboard scanning
Charge rate over-ride capability for Li-Ion
Switch management for Suspend/Resume/On/Off, Lid switches
Interfaces to the smart battery packs to read battery fuel gauge information
AT compatible 8042 keyboard emulation
Extended SCP (XSCP) command interface

The reset pin of the H8 is connected to the DCDC3 plane through an RC filter. A reset
switch is located in the unit which, when pressed, asserts H8RESET# to reset the H8.

SCP I/O Port Definitions/Functions

I/O PORT 1
BIT
Bits 0-7

FUNCTION
Internal keyboard scanning of rows 0-7.

I/O PORT 2
BIT
Bits 0 - 3
Bit 4
Bit 5
Bit 6

Bit 7

FUNCTION
Internal keyboard scanning of columns 0-3.
VOLUP: Sends data to the Maestro 2E audio controller to increase
master mixer volume.
VOLDOWN: Sends data to the Maestro 2E audio controller to increase
master mixer volume.
CHGLED: Lights LED when battery is being charged. Also connects
to the docking connector to be a shutdown indicator for a docked
charge cradle.
CHGEN: This is used to enable the LT1511 charging for both fast
charge and trickle charge.

I/O PORT 3
BIT
Bits 0 - 7

FUNCTION
ISA host data bus interface, tied to SD<0:7>.

3-14 Processor/Cache and System Support

I/O PORT 4
BIT
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

FUNCTION
H8VPPON: Output to enable 12 volts to the H8 VPP pin for H8 flashing.
H8_SPKR: Allows the SCP to beep the internal speaker.
SCPSMI#: SMI output from the SCP to the PIIX4E. This is the only wake-up
source from Suspend. It is used to generate SMIs from many sources.
Not used.
IRQ1: Keyboard Interrupt for internal or PS/2 keyboards. Connects to the PIIX4E
IRQ1.
IRQ12: Mouse Interrupt for touchpad and PS/2 mouse. Connects to the PIIX4E
IRQ12.
CHGRATE: This is a PWM output that can be used to limit the charge rate to the
battery currently being charged.
BRIGHTNESS: This is a PWM output to control the brightness of the inverter. It
connects to the inverter through the 50-pin LCD connector.

I/O PORT 5
BIT
Bit 0
Bit 1
Bit 2
Bits 3-7

FUNCTION
KBDID: Input from keyboard to indicate which countrys keyboard is attached.
AGPPCIRST#: Enables the PCIRST# signal to the video controller.
SYS_RESET#: Initiates a reset of all areas of the system except the H8.
Not used.

I/O PORT 6
BIT
Bit 0
Bit 1
Bit 2
Bit 3

Bit 4
Bit 5

Bit 6
Bit 7

FUNCTION
SMBALERT#: Smart Bus interrupt signal. This is used by the Smart Bus as a way
to generate SMIs.
2
IICINT#: I C interrupt signal. This is used by the docking peripherals as a way to
generate SMIs or request some other function.
ACIN#: Active low to indicate that AC power is available.
POWERSW#: RC-filtered input from the power switch. This switch is used from
Suspend/Resume. If the power switch is depressed and held for four seconds,
the system goes directly to the Off state.
LIDOPEN#: Input from the Lid switch. If the Lid is closed, the system suspends.
If the Lid opens after suspending due to a lid closure, the system resumes.
SYSVCCON#: Input that is asserted when the main system power, SYSVCC, is
enabled by the PIIX4E. This signal corresponds to the power management value
of SUSB in the PIIX4E.
POWERRAILLOW#: Input that is asserted when the VPOWERRAIL power plane falls
below a critical level.
Not used.

Processor/Cache and System Support 3-15

I/O PORT 7 (analog inputs/outputs)

BIT
Bit 0
Bit 1

Bit 2

Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

FUNCTION
H8BATLOW: Analog input indicating the voltage on the battery.
DOCKTYPE: Analog input indicating the type of dock (Convenience Base or
Mobile Expansion Unit) attached to the system. NOTE: This function is not
used at this time.
CPUTEMP: Analog input indicating the CPU temperature. This is used for
thermal management. The processor speed is slowed if a pre-determined
temperature is exceeded. If the temperature exceeds a critical point, the
system is suspended.
VREF: Analog input fixed at 1.182V.
BAY1TYPE: Analog input used to indicate what type of module is inserted
into the notebook module bay.
PANELTYPE: Analog input to indicate the specific panel attached, allowing
the video BIOS to make adjustments for best panel viewing.
Not used.
BAY2TYPE: Analog input used to indicate what type of module is inserted
into a docking stations module bay.

I/O PORT 8
BIT
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6

FUNCTION
SA2: ISA address line.
A20GATE: Implements the PC-AT keyboard Gated A20 function. Used in
conjunction with Port 9 Bit 6.
SCPCS#: SCP Chip select.
IOR#: ISA signal.
IOW#: ISA signal.
XSCPCS#: Extended SCP Chip select.
IICCLOCK: I2C clock signal.

I/O PORT 9
BIT
Bits 0-5
Bit 6
Bit 7

FUNCTION
PS/2 signals for touchpad and external PS/2 ports.
A20GATE: Implements the PC-AT keyboard Gated A20 function. Used in
conjunction with Port 8 Bit 1.
2
IICDATA: I C Data signal.

3-16 Processor/Cache and System Support

I/O PORT A
BIT
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7

FUNCTION
BATDETECT1#: Input from the system battery to signal the battery
attachment.
H8_WAKE: Output to PIIX4E signaling a return from a Suspend state.
DOCK_GNT1#: Output to enable and latch the attached middle dock.
DOCK_GNT2#: Output to enable and latch the attached bottom dock.
DOCKED1#: Input indicating that a middle dock is attached.
DOCKED2#: Input indicating that a bottom dock is attached.
UNDOCK_REQ1#: Input indicating that a middle dock undock is being
requested.
UNDOCK_REQ2#: Input indicating that a bottom dock undock is being
requested.

I/O PORT B
BIT
Bits 0-3
Bit 3

Bit 4
Bit 5
Bit 6
Bit 7

FUNCTION
Internal Keyboard Column outputs.
BAYOCCUPIED#: Transitions from high-to-low to
indicate that a module has been inserted. Remains low
as long as the module is inserted. Used to generate an
SMI.
DQ1: Notebook battery serial interface.
KBDRST#: System reset signal, connected to the
PIIX4Es RCIN# input to force a system reset.
DQ2: Dock battery serial interface.
ONBOARDPS2EN: Output to switch between on-board
PS/2 ports and docking stations PS/2 ports.

Processor/Cache and System Support 3-17

Clocks
Master Clock Generator
The ICS9148 is a clock synthesizer designed for Pentium II CPU based notebook
applications. The ICS9148 requires a 14.318 MHz crystal, which provides multiple
clock outputs up to 100 MHz. It provides CPU and CPU/2 outputs at 66 MHz and 33
MHz, respectively, and hardwired outputs of 48 MHz, 24 MHz, and 14.318 MHz. It
supports CPU and PCI stop-clock operations.
The CPU clock is set to 66 MHz. This clock is connected to the 82443BXs HCLKIN
pin, which is the source for the processor/host bus. The 82443BX also uses 66 MHz to
generate the AGP bus and SDRAM clocks.
The PCI clock is set to CPU/2 (33 MHz) and is used by the PIIX4E to generate the PCI
and ISA buses.
The 48 MHz clock is used by the PIIX4E to generate the USB bus signals. The 14.318
MHz output is used by the PIIX4E and Super I/O controller.
The 24 MHz clock is not used.
For further details, please refer to the ICS9148 design specification.

Other Clocks
Real-Time Clock
The PIIX4E uses a crystal-controlled 32.768 kHz clock to generate the timing signals
for its internal Real Time Clock (RTC). The use of a dedicated crystal oscillator
guarantees that the RTC runs smoothly during instances where the system is fully
powered Off, while drawing extremely low current.

Video Clocks
The 3D RAGE LT Pro uses a 29.498928 MHz crystal to drive an internal clock
synthesizer consisting of six independent phase locked loops (PLLs) capable of
synthesizing any frequency up to 230 MHz. These six PLLs generate:

The clocks for the primary CRTC, display controller, and palette DAC
The clock for the drawing coprocessor
The 66/133 MHz internal clock for AGP bus operations
The clock for the memory controller
The clock for the secondary CRTC, display controller, and palette DAC
The clock for the internal TV encoder

Audio Clocks
The Maestro 2E uses a 49.152 MHz crystal to generate its internal timing signals for
audio data sampling and conversion rates.

3-18 Processor/Cache and System Support