[01]

F (A, B, C, D) = m(2, 7, 8, 13) + d(0, 5, 10)

(a)
AB

00

11
10

00

11
10

00

CD

11

(b) Find the optimized sumofproducts (SOP) expression

for F.

01

10

F (ABCD) = BD+BCD+ABD

01

01

01

00

CD

11

10

F (ABCD) = BD+BCD+ABD
(c) Find the optimized productofsums (POS) expression
for F.

AB

00

11
10

01

01

00

CD

11

10

F (ABCD) = ABD+ABD+AC+BD
(d)
[Q2]

(a) F1(A,B,C)= m(0, 1, 2, 4, 6, 7)

00

01

11

10

AB
C
0

F1(A,B,C)= C+AB+AB

F2(A,B,C)= m(0, 1, 3, 5, 7)

00

01

11

10

AB
C
0

F2(A,B,C)= C+AB

F3(A,B,C)= m(0, 1, 2, 3, 6, 7)
00

01

11

10

AB
C
0

F3(A,B,C)= A+B

F4(A,B,C)= m(0, 2)
00

01

11

10

AB
C
0

F4(A,B,C)= AC

(b) Draw truth tables for the above expressions.

F1(A,B,C)= C+AB+AB

AB

AB

C+AB
+AB

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0

0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0

AB

1
1
0
0
0
0
0
0

A+B

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
1
0
0
0
0

1
1
1
1
0
0
1
1

AC

0
0
0
0

0
0
1
1

0
1
0
1

1
1
1
1

1
0
1
0

1
0
1
0

1
1
0
0
0
0
0
0

F2(A,B,C)= C+AB
C+AB
1
1
0
1
0
1
0
1

F3(A,B,C)= A+B

F4(A,B,C)= AC

1
1
1
0
1
0
1
1

1
1
1
1

(c) i. ROM

0
0
1
1

0
1
0
1

0
0
0
0

1
0
1
0

0
0
0
0

ii. PLA
F1(A,B,C)=C+AB+AB
P1 P2 P3
F2(A,B,C)= C+AB
P4
F3(A,B,C)= A+B
P5 P6
F4(A,B,C)= AC
P7

iii. PAL

(d)

ROM

PLA

Devices with fixed AND

array (which is a decoder)
and programmable OR
array.

The AND array (decoder)

generates all 2n possible
minterm products of its n
inputs (often referred to
as n-to-2n decoder).
n input lines, m output
lines.

Compared to a ROM and a

PAL, a PLA is the most
flexible having a
programmable set of
ANDs combined with a
programmable set of
ORs.
A PLA can have large N
and M permitting
implementation of
equations that are
impractical for a ROM
(because of the number of
inputs, N, required

Bit combination of input

variables address.

A PLA has all of its

product terms

PAL

The PAL is the

opposite of the
ROM, having a
programmable set
of ANDs combined
with fixed ORs.

ROM guaranteed to
implement any M
functions of N
inputs. PAL may have too
few inputs to the OR gates

connectable to all
outputs, overcoming the
problem of the limited
inputs to the PAL ORs
Some PLAs have outputs
that can be
complemented, adding
POS functions
Bit combination of output
lines word (each word
contains m bits).

[Q3]
(a)

Often, the product term

count limits the
application of a PLA. .

For given internal

complexity, a PAL can
have larger N and M.
Some PALs have outputs
that can be
complemented, adding
POS functions
No multilevel circuit
implementations in ROM
(without external
connections from output
to input). PAL has
outputs from OR terms as
internal inputs to all AND
terms, making
implementation of multilevel circuits easier.

Setup time (tsu ): The minimum amount of time the data signal should be held steady before the
clock event so that the data is reliably sampled by the clock. This applies to synchronous input signals
to the flip-flop.
Hold time (th): The minimum amount of time the data signal should be held
steady after the clock
event so that the data are reliably sampled. This applies to synchronous input
signals to the flip-flop.
Propagation delay (tp): the time a flip-flop takes to change its output after the clock
edge

(b)
(c)

[Q4]

(a)
X

1 0 1 0 0 1 1 0 1 1 0 0 1 1

0 0 0 0 0 1 0 1 0 0 1 0 1 0 .

(b)

Draw a state table for the pattern detector.

Present
State
S0
S1
S2
S3
S4
S5
S6

(c)

Next State /Output

X=0
S1/0
S1/0
S4/0
S4/0
S6/0
S4/1
S1/0

X=1
S2/0
S3/0
S2/0
S5/0
S3/0
S2/0
S3/1

Draw a transition table for the pattern detector.

2P-1 < 7
P=3
Present State

Next State /Output

X=0
X=1
Y2 Y1 Y0
Y2 Y1 Y0 /Z

Y2 Y1
Y0
0 0
0
0 0
1
0 1
0
0 1
1
1 0 0

S0

0
1/0
0
1/0
1
0/0
1
0/0
1
0/0
1 0 1
1
0/1
1 1 0
0
1/0

S1
S2
S3
S4
S5
S6

0 1 0/0

0 1 1/0

0 1 0/0

1 0 1/0

0 1 1/0

0 1 0/0

0 1 1/1

(d) Implement the pattern detector using D Flip Flop and other digital gates.
Y0Y1

00
01
11
10

Y2X

01
11
10

01

Y0Y
00

00

00

10

D0=Y1Y2X + Y1Y2X + Y0X

01

0Y2X 0

11

11

10

D1=Y1X + Y1Y2 + Y0Y2X

Y0Y
1

00
01
11
10

00

Y2X

01

11

10

D2=Y1Y2X + Y1Y2X + Y0Y1X + Y0Y1Y2 + Y0Y2X

Y0Y
1

00
01
11
10

Y2X

00

01

11

10

Z=Y1Y2X + Y0Y1Y2X