Final Exam: Graduate Course { VLSI Testing

Auburn Univ., ELEC 7250, Spring 2004

May 10, 2004
Instructions (please read before you proceed):

1. Please read all problems before starting your answers. Problems can be answered in any order.
2. Attempt all six problems and attempt all parts within each problem.
3. Answers can be written on question sheets or separate sheets or a combination.
Each sheet should have a page number and problem number. On the rst sheet
write your name and the total number of sheets you are submitting.
4. Before handing in your answers, please check them thoroughly. If necessary,
extra 10 minutes can be allowed for checking.

Problem 1: Fault Modeling (16 Points)

For the circuit of Figure 1, determine fault equivalences among the ve faults shown.
C

L
E

sa1

sa0
H

Z
sa1

sa0

sa1

G
B

Figure 1: Circuit for fault modeling problem.

Final Exam Problems: VLSI Testing ELEC 7250 { May 10, 2004

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Problem 2: Testability Measures (16 Points)

For the circuit of Figure 2 compute SCOAP combinational controllability and observability measures for all lines (8 points).
I

G
H
L
E

Figure 2: Circuit for testability measures problem.

(i) Assuming that the testability of a stuck-at fault can be represented as the sum
of appropriate controllability and observability, nd the set of most di cult
to test faults (4 points).
(ii) Proving a fault to be redundant is a di cult task for an ATPG program. This
circuit has three redundant faults, I s-a-1, J s-a-1, and F s-a-1. Are all of
these faults in your set of most di cult to test faults? If not, explain why not
(4 points).

Final Exam Problems: VLSI Testing ELEC 7250 { May 10, 2004

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Problem 3: Logic Simulation (17 Points)

The following conversation is recorded at a meeting to discuss the verication problems of the circuit shown in Figure 3:
A

B
C
E

Z
F

FF
CK

Figure 3: Circuit for Problem 3.

Designer: Why does our logic simulator not initialize my circuit?
CAD Engineer: That is due to a limitation of the three-state logic simulator.
Designer: Irrespective of the initial state, the ip-op should initialize to 1 state
when 1 is applied at the input A and the circuit is clocked. I am not going to change
the circuit. You better x your simulator.
CAD Manager (not realizing what is being promised): My engineer will nd a
solution before the end of the day.
You are the CAD engineer who must take the challenge:

(i) Devise a modication of the three-state logic simulator that will correctly initialize the circuit of Figure 3 containing a single ip-op (9 points).
(ii) How will you extend the new procedure for circuits with many ip-ops (4
points)? Discuss any limitations (4 points).

Final Exam Problems: VLSI Testing ELEC 7250 { May 10, 2004

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Problem 4: Podem (17 points)

Use the Podem algorithm to derive a test for the fault G stuck-at-0 in the Schneider's
example circuit from Roth's 1967 paper, which is shown in Figure 4 (8 points).
F
A

(2,4)7
SCOAP Testability Measures
(CC0, CC1) CO

(1,1)10

(1,1)10

(1,1)10
B
(1,1)10
C

(1,1)10
(2,3)9

(2,3)10 K
(2,3)10

(2,4)7

Z
(2,3)10

sa0

(1,1)10

(2,4)7

(5,9)0

(2,3)9
M

(2,4)7

(1,1)10

Figure 4: Schneider's circuits for Podem problem.

Neatly write all steps, specifying objectives, operations (backtrace, forward implications, X-path check, etc.) Give the state of the implication stack at each step.
(9 points).

Final Exam Problems: VLSI Testing ELEC 7250 { May 10, 2004

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Problem 5: Delay Test (17 points)

(i) Specify a single input change (SIC) test for the critical path " a ; z (shown in
bold lines) in the circuit of Figure 5(i). Is this a robust test? (8 points)
(ii) The circuit of Figure 5(i) is redesigned in Figure 5(ii) to reduce the delay.
Will the SIC test obtained above still test the longest delay path shown in
bold lines? If not, what is the minimum modication required in the test? (9
points)
a
b
c
d
e
f
g
h
i

z
(i) Original circuit.
a
b
c
d
e
f
g
h
i
z

(ii) Redesigned circuit.

Figure 5: Circuits for delay test problem.

Final Exam Problems: VLSI Testing ELEC 7250 { May 10, 2004

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Problem 6: DFT (17 Points)

The circuit in Figure 6 is a sequence detector. A sequence 11111 in the input bitstream at A locks the output Z to 1. The output can be unlocked by applying
R = 1.
Z
A

FF
FF

FF

FF

FF

CK
R

Figure 6: Circuit for DFT Problem 6.

For scan design, only one pin is available and the only circuit element that can
be used is a two-to-one multiplexer.
(i) Redesign the circuit using minimum extra hardware to conform to the scan
design rule, \clock must not be gated by a combinational signal." Neatly
sketch the redesigned circuit (8 points).
(ii) Sketch a schematic of the full-scan circuit using minimum extra overhead.
Show the complete wiring of the SCANIN , SCANOUT and test control
(TC ) signals (9 points).

Final Exam Problems: VLSI Testing ELEC 7250 { May 10, 2004

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