Functions Simplification

Lara Manuel, Aguilar Armin, Chan Ricardo,

Ros Aaron, Prado Ivn.

Line 1 (of Affiliation): dept. name of organization

Line 2: name of organization, acronyms acceptable
Line 3: City, Country
Line 4: e-mail address if desired

UNIVERSIDAD AUTNOMA DE YUCATN

Mrida, Yucatn

Authors Name/s per 2nd Affiliation (Author)

Abstract From the Boole algebra theorem, simplifications to
algebraic expressions will be realized and with the truth tables of
a logical function, Karnaugh maps will be realized. Through
simulation and implementation in a FPGA, these functions
(original and simplified) will be verified to be equal.

I.

INTRODUCTION

Boole algebra is all class or set of elements that can take

two perfectly differentiated values, which are designed as 0
and 1.
Simplification of Boolean expressions has always been
important, since smaller logical expressions use fewer
resources and are easier to implement.

Karnaugh map
The Karnaugh map provides an alternative way of circuit
simplification. Instead of using simplification techniques with
Boole algebra, logic values can be transferred from a Boolean
function o from a truth table to a Karnaugh map. The grouping
of zeros and ones in the map helps to visualize the logic
relations between the variables and leads to simplified Boolean
function.
Karnaugh maps are used to simplify logical problems with
2, 3 and 4 variables.In figure 1 an example of a Karnaugh map
can be observed.

Boole algebra has the following properties:

Addition and multiplication are conmutative:
+ = +
=
In Boolean algebra, there exists two neutral elements, 0
and 1, which fulfill the property of identity:
0+ =
1 =
Each operation is distributive respect to each other:
( + ) = +
+ ( ) =
( + ) ( + )
For each element of algebra there exists an element
denominated:
+ = 1

=0

This postulate defines a new fundamental operation, which

is the inversion o complementation of a variable.

Figure 1: OR logic gate with its corresponding Karnaugh map

and truth table.
II.

SIMULATION

In this experiment one simulation was realized and is shown

in Fig.2.
The experiment was modeled by changing the value of the
two inputs at different time intervals and finally, leaving both
inputs as a logic 1.
It is important to state that in Fig.2, thed input value only
affects the circuito3 and circuit3_Simp signals.

Fig.2. Simulation of three non-simplified circuits,

each with its corresponding simplified version, in

From Fig.2, it could be observed an equivalence between

the signals of each non-simplified circuits and there
corresponding simplified circuits (each non-simplified and
simplified circuit pair is shown by similar color signals), thus
proving that a logic circuit may be expressed as another
simplified logic expression with the exact same logical output.
III.

IMPLEMENTED DESIGN

In order to correctly implement the design of each of the

given Boolean Functions the program included both the
original and the simplified functions; this was done with the
objective of comparing the behavior of the functions and also
to prove that said behavior is the same in both cases.
The pseudo code used in the implementation is as follows:
+
+ ) + (1)

(
< =

+ (
< =
) (2)

+
+

(3)
< =
+

+
+

(4)
< =

The syntax presented in (1) and (3) are the original

expressions presented in the manual whereas (2) and (4) are
the simplified expressions. After implementing this program
the various Boolean expressions were tested and the results can
be seen in the latter section of this document and in the
simulation as well.
The visualization of these results was made possible by the
FPGA Basys 2 using both input and output pins as were
necessary to be able to visualize everything that was
implemented in the program used.
IV.

IMPLEMENTATION CONSTRAINTS FILE

This file is used for allocating each FPGA pin depending on

the FPGA characteristics like the family, device and package
with the variable input/output created in the VHDL module,
the syntax is described in 3, the variable name is the assigned
on the module.
NET VARIABLE_NAME LOC= FPGA_PIN; (3)
V.

LOADING THE PROGRAM

Once with the design implementation and the constraints, in

Xilinx option we used the synthesizer, after implement design
and finally generate a programming file BIT. Thus, with the
FPGA connected to computer and with the software Digilent
Adept was load the bit file before created.

of these with the use of Boolean properties (rules) and

Karnaugh maps. It was also possible to implement the logic
functions thanks to the use of only 4 LUTS also called truth
tables, this array of configuration can prove the behavior of the
whatever digital circuit but this are limited for the high number
of bits and the extensive complex of logic gates combination.
As a result, were obtained three implemented functions with
their simplification, which gives six implemented logic
functions. The signal outputs for the three cases had the same
behavior, which proved the correctness of each simplification.
All this analysis was possible thanks to the signal outputs
observed in the simulation and in the implementation on the
FPGA.
There are 960 available slices in the architecture of the
FPGA Basys 2 [4]; these slices could also be seen as the basic
building block components in the FPGA, which contains a
number of LUTs, flip-flops and carry-logic elements.
Specifically only 1% of the occupied slices were used, cero
flips-flops and six inputs outputs buses (IOBS) of 83 available,
which gives 7% of the total available. This information shows
the amazing power and advantage of the FPGA, because it
could be implemented at a high level, getting efficiency and
control design, also the software gives the statistics of the
sources, translation report, map report, synthesis report and
control design, also the statistics of the sources used in the
module VHDL.
CONCLUSION
This practice show us how a complex Boolean function could
be reduced to terms more simple, using the axioms and
theorems algebra Boole and the implementations of the
Karnaugh maps however is necessary to emphasize that there
are many possibilities to construct one function or an specific
output, but if the simplification process is successful doesnt
matter because we could express the same output with less
terms and logical operators all depend of the arrangement used
and the application of the DeMorgan theorems. This bring us
several advantage in the time of synthetize, implementation,
design, and the sources used in the FPGA let us be more
efficient and create functions more complex with the
necessary sources design. The process of simplification not
always ensure the reduction of the terms and sources, in special
cases could be a function more complex compare to the
original based in the number of logic gates, Flip flops, IOBs
used etc.
REFERENCESE
[1]
[2]

VI.

RESULTS

In the practice implementation, were used the basics logic

gates for built the logic functions given and the simplifications

[3]
[4]

R.Jaeger,T. Blalock. (2011). Microelectric Circuit Desgn,

New York, U.S.A: McGraw Hill.
D. Money, Digital Design and Computer Architecture
chapter 1, pp. 2530, July 2012.
D. Money, Digital Design and Computer Architecture
chapter 1, pp. 2530, July 2012.
Basys 2TM FPGA Board Reference Manual (2011). 1300
Pullman, WA 99163, USA.

4th Edition.
2nd edition,
2nd edition,
Henley Ct,