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Performance Analysis of Inverter Using Domino Logic
Performance Analysis of Inverter Using Domino Logic
Next is the evaluation phase or cycle, during which either ,node A' are discharged through NMOS
transistor T2 or they remain high, according to the realized function. Thus the outputs A of the buffer either
reaches high or remain low, respectively .As shown in fig .2 ,in Domino logic
logic the transition of nodes A is always
from low to high and is rippled through the logic from primary inputs to the primary outputs.Gates evaluate
sequentially but precharge in parallel.Thus evaluation is more critical than precharge. Each domino gate triggers
trigg
next one,like a string of dominos toppling over.Since there are cascaded logic blocks,the evaluation of a stage
causes the next stage to evaluate and proceed so on.There is no restriction on number of logic stages be cascaded,
provided that they can be evaluated within the evaluate phase of the clock. Thus the Domino logic design
precharged by clock presents applications with high performance in terms of reduced area requirements and as well
as reduced power dissipation.
ISSN: 2347-2200/V2-N1/PP35
N1/PP35-43/IJSE-ITS: Race-2014
37
Performance Analysis of Inverter using Domino Logic
implementation by CMOS and DOMINO technologies on 90nm and 65nm scale foundary and try to distinguish that
how the DOMINO logic circuits designs are low power and high speed circuits,and require less area than CMOS
designs, we perform all the experimental designing and simulation using DSCH and microwind CAD tools.
The Inverter of CMOS logic consist of one pmos transistor and one nmos transistor. when the input A is
(0), the NMOS transistor is OFF and PMOS transistor is ON. Thus the output is pulled up to (1) because it is
connected to VDD but not to GND. Conversely, when A is 1, the NMOS transistor is ON,the PMOS is OFF and
the output is pulled down to 0. This is summarized in the truth table.
Table 1:- Inverter truth table
INPUT A
OUTPUT NOT A
On simulation through DSCH we get Fig .3 showing the Schematic diagram of CMOS Inverter ,and Fig .4 showing
Waveform for CMOS Inverter,similarly Fig .5 showing Schematic diagram of Domino Inverter and Fig .6 showing
Waveform for Domino Inverter.
B
0
1
0
1
A.B
0
0
0
1
The AND gate can be defined as an electronic circuit that gives a high output 1, only if all its inputs are high. AND
operation is represented by a (.)dot like A.B . Here in Fig .7 and Fig .8 ,we present the Schematic and Waveform of
CMOS AND Gate respectively,while Fig .9 and Fig .10 presents the Schematic and Waveform of DOMINO AND
GATE respectively.
39
Performance Analysis of Inverter using Domino Logic
The layout and simulation have been performed on Microwind and DSCH for CMOS AND & Domino AND Gate.
First the schematics & Waveforms are drawn using DSCH,Proceeding with a Verilog file is generation in DSCH
which is then compiled in Microwind tool to generate the layout and to estimate layout area. Simulations are done
using BSIM4 MODEL.BSIM ie, Berkeley Shortchannel IGFET Model [5]referstofamily of MOSEFT transistor
models for integrated circuit design.
Fig 11. Flow Graph for Layout Area and other parameter estimation.
41
Performance Analysis of Inverter using Domino Logic
On 65nm
On 65nm
43
Performance Analysis of Inverter using Domino Logic
Table 3. power and layout comparison of CMOS AND Gate and Domino AND Gate
Parameter
Cmos AND
Domino AND
90nm
65nm
90nm
65nm
Area(m )
75.1
36.8
37.3
18.3
Power(mw)
.997
.136
.795
.106
V. CONCLUSION
In this work an attempt has been made to simulate And gate. Domino circuits have offered an improved
performance results. On comparing the power consumption and layout area of cmos and & domino and method .
The domino and is more effective in reducing power consumption as well as layout area.The result is simulated
with microwind software and DSCH ,and compare at different technology of 90nm and 65nm. Thus we conclude
that the power and area performance of Domino Logic is far better than CMOS logic.The number of gates of n type
also provides faster response in Domino logic.
REFERENCES
1]Knepper. "SC571 VLSI Design Principles," Chapter 5: Dynamic Logic Circuits
2] Abdel-Hafeez and Ranjan. Single Rail Domino Logic For Four-Phase Clocking Scheme.
3]Rakhi R. Agrawal and S.A.Ladhake,Systematic Design of High-Speed and Low-Power Domino LogicInternational Journal
of Advanced Research in Computer Science and Software Engineering, Volume 2 ,pp 218-224 ,March.2012
4] R.K. Brayton, R. L. Rudell, and A. L. Sangiovanni-Vincentelli,-MIS: A Multiple-Leve Logic Optimization System, in IEEE
Trans.on Computer Aided Design, pp.1062-1081,Vol. 6, No. 6, 1987.
[5] Sheu, Scharfetter, Ko, and Jeng (August 1987). "BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors". IEEE
Journal of Solid State Circuits. SC-22: 558566.
[6]Vojin G. Oklobdzija and Robert K. Montoye, Design-Performance Trade-Offs in CMOS-Domino Logic, In IEEE Journal of
Solid-State Circuits, Volume sc-21, No. 2