GPS GSM Document

CHAPTER 1
INTRODUCTION
In this project there are mainly three units. Those are GSM modem,
GPS modem and micro controller unit. We can configure GSM modem by
standard GSM AT command set for sending and receiving SMS and getting
modem status. GPS modem for getting the data of longitude, latitude of location
on earth. These data sending to predefined GSM number through the GSM
modem. All these functions are controlled by the microcontroller. Alphanumeric
LCD display also added in this project for user friendly interface. GSM modem is
configured by standard GSM AT - command set.
A vehicle tracking system combines the installation of an electronic device in a
vehicle, or fleet of vehicles, with purpose-designed computer software at least at
one operational base to enable the owner or a third party to track the vehicle's
location, collecting data in the process from the field and deliver it to the base of
operation. Modern vehicle tracking systems commonly use GPS technology for
locating the vehicle, but other types of automatic vehicle location technology can
also be used. Vehicle information can be viewed on GSM mobile or electronic
maps via the Internet or specialized software. Urban public transit authorities are
an increasingly common user of vehicle tracking systems, particularly in large
cities.
Vehicle tracking systems are commonly used by fleet operators for fleet
management functions such as fleet tracking, routing, dispatch, on-board
information
and
security.
Along
with
commercial
fleet
operators,
urban transit agencies use the technology for a number of purposes, including
monitoring schedule adherence of buses in service, triggering changes of
buses' destination sign displays at the end of the line (or other set location along
a bus route), and triggering pre-recorded announcements for passengers.
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CHAPTER 2
History of GSM
During the early 1980s, analog cellular telephone systems were experiencing
rapid growth in Europe, particularly in Scandinavia and the United Kingdom, but
also in France and Germany. Each country developed its own system, which was
incompatible with everyone else's in equipment and operation. This was an
undesirable situation, because not only was the mobile equipment limited to
operation within national boundaries, which in a unified Europe were increasingly
unimportant, but there was also a very limited market for each type of equipment,
so economies of scale and the subsequent savings could not be realized. The
Europeans realized this early on, and in 1982 the Conference of European Posts
and Telegraphs (CEPT) formed a study group called the Group Special Mobile
(GSM) to study and develop a pan-European public land mobile system. This is a
pioneer mode of communication which is sited in almost all countries around the
world Owing to its widespread availability; an appropriate knowledge of this
valuable channel of communication can equip us with a powerful tool for
controlling desired device or process parameter from distant location, through
electromagnetic waves. With a little effort logic can be setup to even receive a
feedback on the status of the device or the process being controlled.
CHAPTER 2
History of GPS
The Global
Positioning
System (GPS)
is
space-based satellite
navigation system that provides location and time information in all weather,
anywhere on or near the Earth, where there is an unobstructed line of sight to
four or more GPS satellites. It is maintained by the United States government
and is freely accessible by anyone with a GPS receiver. The system imposes
some technical limitations which are only removed for authorized users.
The GPS program provides critical capabilities to military, civil and commercial
users around the world. In addition, GPS is the backbone for modernizing the
global air traffic system.
The GPS project was developed in 1973 to overcome the limitations of previous
navigation systems, integrating ideas from several predecessors, including a
number of classified engineering design studies from the 1960s. GPS was
created and realized by the U.S. Department of Defense and was originally run
with 24 satellites. It became fully operational in 1994.
Advances in technology and new demands on the existing system have now led
to efforts to modernize the GPS system and implement the next generation of
GPS
III
satellites
and
Next
Generation
Operational
Control
System
(OCX). Announcements from the Vice President and the White House in 1998
initiated these changes. In 2000, U.S. Congress authorized the modernization
effort, referred to as GPS III.
In addition to GPS, other systems are in use or under development. The Russian
Global Navigation Satellite System (GLONASS) was in use by only the Russian
military, until it was made fully available to civilians in 2007. There are also the
planned
European
Union Galileo positioning system, Chinese Compass
navigation system, and Indian Regional Navigational Satellite System.
Basic concept of GPS

A GPS receiver calculates its position by precisely timing the signals sent by
GPS satellites high above the Earth. Each satellite continually transmits
messages that include the time the message was transmitted, precise orbital
information the general system health and rough orbits of all GPS satellites.
The receiver uses the messages it receives to determine the transit time of each
message and computes the distance to each satellite. These distances along
with the satellites' locations are used with the possible aid of trilateration,
depending on which algorithm is used, to compute the position of the receiver.
This position is then displayed, perhaps with a moving map display or latitude
and longitude; elevation information may be included. Many GPS units show
derived information such as direction and speed, calculated from position
changes.
A GPS tracking unit is a device that uses the Global Positioning System to
determine the precise location of a vehicle, person, or other asset to which it is
attached and to record the position of the asset at regular intervals. The recorded
location data can be stored within the tracking unit, or it may be transmitted to a
central
location
data
base,
or
internet-connected
computer,
using
a cellular (GPRS or SMS), radio, or satellite modem embedded in the unit. This
allows the asset's location to be displayed against a map backdrop either in real
time or when analyzing the track later, using GPS tracking software.
CHAPTER 3
Design Method
Considering the variety and the complexity of the functions to be performed and
the fact that a rather complex controlling structure needs to coordinate the overall
activity of the system, a microcontroller-based system is ideally suited for this
application. In addition to coordinating the functions of the system, the controller
itself may be used to simplify the implementation of some of the desired functions
or tasks (like counting, comparison of data, interrupts handling etc.). The use of a
microcontroller has the advantage that it has a CPU (a microprocessor) in
addition to a fixed amount of RAM,ROM,I/O ports & timer are all embedded
together on one chip, thus decreasing the size and cost of the system. Future
design changes are quickly and easily implemented, primarily by changing the
program. Thus reducing the material costs. Also, software is more flexible than
hardware.
The Top-Down policy approach has been followed in the design of this system.
This approach is basically a step-wise refinement. First, the general structure is
created. The problem is broken into smaller segments and each one is dealt with
individually. This process is repeated until the problem segment in hand is
manageable.
The basic functions to be performed by this system could be distinctively divided
in the following manner:
1) Reading GPS Data
2) Display the data on LCD
3) Sending Location data to mobile through the GSM modem
We are using ATMEGA16 microcontroller. This controller communication with
both GPS and GSM modems through the serial port. But microcontroller had only
one serial port. So we are using analog switch for switching the serial port to
GSM and GPS modems. LCD display using for instant data display. RTC IC
using for Real time back up.
5
For serial communication we are using Max 232 line driver line IC to convert TTL
levels into RS232 and vice versa.
Max232 was populated for debugging
purpose. Key board connecter provided for future applications
CHAPTER 4
BLOCK DIAGRAM
CHAPTER 5
7
POWER SUPPLY
The circuit to be a self-contained unit and thus requires a power supply to
provide low voltage DC for its electronics from the AC power line. a standard
linear topology was chosen. The components used in the circuit will be standard,
conventional parts that will use a supply voltage of 5V. These specifications
dictate the use of a low-cost, ubiquitous linear regulator -- the National
Semiconductor, LM7812, and LM7805. The LM7805 requires an input voltage of
at least 7.5V in order to guarantee regulation, so the unregulated power supply
should supply at least this voltage under worst-case current consumption,
assumed to be about 200mA. Because a full-wave bridge rectifier will be used for
efficiency, we can assume that about 1.4V will be lost across the bridge (0.7V per
conducting diode). We therefore need a peak voltage of at least 9V from the
power transformer. Because the RMS voltage of a sinusoidal AC signal is 0.707
times the peak, a power transformer with a 6.3V RMS secondary is required.
Transformer 230V/12V, 100mA is meeting the above requirement hence
selected.
We provide the battery backup for this application. So we added battery charging
circuit here. Battery voltage is feedback to the controller for controlling the
charging. Controller read the battery voltage at one ADC pin, and then based on
the ADC level, we ON/OFF the charging circuit.
Most of the devices in electronic equipments require essentially a constant
DC. voltage for their operation. Therefore, almost all electronic equipments
include a circuit that converts AC voltage of mains supply into DC voltage which
is independent of changes in AC. line voltage. This part of the equipment is
called power supply.
Power supply units generally operate from AC. mains power line and consist of
following sections:
Transformer
8
A full wave rectifier

A smoothing filter
A voltage regulator circuit or IC regulator
Circuit description:
The transformer provides voltage transformation and produces AC voltage
required for producing the desired DC voltages across its secondary windings. It
also provides electrical isolation between the power supply input i.e., AC mains
and output. The rectifier circuit changes the AC voltages appearing at
transformer secondary to DC. Commonly used rectifier circuits include half-wave
rectifier, conventional full-wave rectifier requiring a tapped secondary or a bridge
rectifier.
The rectified voltage will always have some AC content known as power supply
ripple. The filter circuit levels the ripple of the rectified voltage. The filtering action
of
the capacitor connected across the output of the rectifier comes from the fact that
it offers a low reactance to AC components. The ripple in nature is inversely
proportional to capacitance. Thus, the capacitor connected across the output of
the rectifier, which provides the filtering action, must be large enough to avoid the
ripple.
The regulated circuit is a type of feedback circuit that ensures the output DC
voltage does not change from its normal value due to changes in line voltage or
load current. It is the nature of regulator circuit that distinguishes the linear power
supply from a switching supply. In a linear power supply, the active device (linear
regulator) that provides regulation, usually bipolar transistor is operated
anywhere between cut-off and saturation i.e., in active region whereas in
switching mode power supply, switching regulator is operated either in cut-off or

in saturation. 7812 or 7805 are linear, fixed voltage series regulators, which
provide regulated 12V and 5V DC respectively. In case of a series regulator a
change in the output voltage due to a change in input voltage or load current
results in a change in the voltage drop across the regulator transistor so as to
maintain a constant output voltage across the load. 12V and 5V regulated DC
power supplies are obtained across 10 micro farad capacitors.
Figure below shows a complete power supply using a transformer (step
down, center tapped 12-0), a full wave rectifier with two P-N junction diodes
(IN4007), capacitive (2200uF, 470uF, 100uF) filter sections and voltage regulator
IC (7805).
The AC voltage to be rectified is applied to the primary coil of the
transformer T1. The secondary of the transformer is connected to two P-N
junction diodes for full wave rectification. It is then followed by a shunt capacitive
filter which filters the unidirectional pulsating voltage of the rectifier output. It is
then regulated by a voltage regulator IC. voltage regulator IC 7809 is used to get
the constant output of +9v DC. And 7805 is used to get the constant output of
+5v DC.These regulator IC maintains the constant output voltage at a desired
value irrespective of the variations in AC. line voltage.
LM7809CT
LM7805CT
Vreg
pin 1
input
IN
OUT
pin 1
input
pin 3
output
pin 2
GND
Vreg
IN
OUT
pin 3
output
pin 2
GND
Pin description of LM7805 &LM7809
Monolithic IC voltage regulator:
10
A voltage regulator is a circuit that supplies a constant voltage regardless

of changes in load currents. Although voltage regulators can be designed using
op-amps, it is quicker and easier to use IC voltage regulators. Furthermore, IC
voltage regulators are versatile and relatively inexpensive and are available with
features such as programmable output, current/voltage boosting, internal shortcircuit current limiting, thermal shutdown and floating operation for high voltage
applications
Here we are using 7800 series voltage regulators. The 7800 series
consists of 3-terminal positive voltage regulators with seven voltage options.
These ICs are designed as fixed voltage regulators and with adequate heat
sinking can deliver output currents in excess of 1A. Although these devices do
not require external components, such components can be used to obtain
adjustable voltages and currents. For proper operation a common ground
between input and output voltages is required. In addition, the difference
between input and output voltages (VI VO) called drop out voltage, must be
typically 1.5V even during the low point as the input ripple voltage. Furthermore,
the capacitor Ci is required if the regulator is located an appreciable distance
from a power supply filter. Even though Co is not needed, it may be used to
improve the transient response of the regulator.
Typical performance parameters for voltage regulators are line regulation,
load regulation, temperature stability and ripple rejection. Line regulation is
defined as the change in output voltage for a change in the input voltage and is
usually expressed in milli volts or as a percentage of Vo. Temperature stability or
average temperature coefficient of output voltage (TC Vo) is the change in output
voltage per unit change in temperature and is expressed in either milli volts/C or
parts per million (PPM/C). Ripple rejection is the measure of a regulators ability
to reject ripple voltage. It is usually expressed in decibels. The smaller the values
of line regulation, load regulation and temperature stability the better the
regulation
11
FIXED VOLTAGE REGULATORS:General Description:

The LM78XX series of three terminal regulators is available with several fixed
output voltages making them useful in a wide range of applications. One of these
is local on card regulation, eliminating the distribution problems associated with
single point regulation. The voltages available allow these regulators to be used
in logic systems, instrumentation, HiFi, and other solid state electronic
equipment. Although it was designed primarily as fixed voltage regulators these
devices can be used with external components to obtain adjustable voltages and
currents.
The LM78XX series is available in an aluminum TO-3 package which will allow
over 1.0A load current if adequate heat sinking is provided. Current limiting is
included to limit the peak output current to a safe value. Safe area protection for
the output transistor is provided to limit internal power dissipation.
If internal power dissipation becomes too high for the heat sinking provided, the
thermal shutdown circuit takes over preventing the IC from overheating.
Considerable effort was expanded to make the LM78XX series of regulators easy
to use and minimize the number of external components. It is not necessary to
bypass the output, although this does improve transient response. Input
bypassing is needed only if the regulator is located far from the filter capacitor of
the power supply.
CHAPTER 6
MICRO CONTROLLER
12
Looking back into the history of microcomputers, one would at first come across
the development of microprocessor i.e. the processing element, and later on the
peripheral devices. The three basic elements-the CPU, I/O devices and memoryhave developed in distinct directions. While the CPU has been the proprietary
item, the memory devices fall into general-purpose category and the I/O devices
may be grouped somewhere in-between.
We are using atmega16 in this application.
6.1 Features of Atmega16
High-performance, Low-power AVR 8-bit Microcontroller
Advanced RISC Architecture
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
16K Bytes of In-System Self-programmable Flash program memory
512 Bytes EEPROM
1K Byte Internal SRAM
Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
Data retention: 20 years at 85C/100 years at 25C
In-System Programming by On-chip Boot Program
Programming Lock for Software Security
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
One 16-bit Timer/Counter with Separate Rescale, Compare and Capture mode
Real Time Counter with Separate Oscillator
Four PWM Channels
8-channel, 10-bit ADC,8 Single-ended Channels
Byte-oriented Two-wire Serial Interface
Programmable Serial USART
13
Master/Slave SPI Serial Interface

Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down,
Standby and Extended Standby
6.2 Pin diagram
It was total 40 pin microcontroller. In this two for VCC and two for ground. One
pin for reset and other 32 pins are i/o pins. Each port had individual additional
14
features. portA had ADC module, PORTD had USART and external interrupt
functions.
6.4 ATMEGA16 internal block diagram
6.5 Pin Descriptions
15
VCC -------------------------------------------Digital supply voltage

GND --------------------------------------------Ground.
Port A (PA7 --PA0) Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not
used. Port pins can provide internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink
and source capability. When pins PA0 to PA7 are used as inputs and are
externally pulled low, they will source current if the internal pull-up resistors are
activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up
resistors (selected for each bit). The Port B output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port B pins
that are externally pulled low will source current if the pull-up resistors are
activated. The Port B pins are tri-stated when a reset condition becomes active,
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up
resistors (selected for each bit). The Port C output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port C pins
activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running. If the JTAG interface is enabled, the pull-up
resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a
reset occurs.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up
resistors (selected for each bit). The Port D output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port D pins
activated. The Port D pins are tri-stated when a reset condition becomes active,
RESET Reset Input. A low level on this pin for longer than the minimum pulse
length will generate a reset, even if the clock is not running. Shorter pulses are
not guaranteed to generate a reset.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock
operating circuit.
XTAL2 Output from the inverting Oscillator amplifier.
16
AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It should
be externally connected to VCC, even if the ADC is not used. If the ADC is used,
it should be connected to VCC through a low-pass filter.
AREF AREF is the analog reference pin for the A/D Converter.
6.6 AVR MCU Architecture
This section discusses the AVR core architecture in general. The main function of
the CPU core is to ensure correct program execution. The CPU must therefore
be able to access memories, perform calculations, control peripherals, and
handle interrupts.
Architectural Overview
Figure .6.6 Block Diagram of the AVR MCU Architecture
In order to maximize performance and parallelism, the AVR uses Harvard
architecture with separate memories and buses for program and data.
Instructions in the Program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from
17
the Program memory. This concept enables instructions to be executed in every

clock cycle. The Program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working
registers with a single clock cycle access time. This allows single-cycle Arithmetic
Logic Unit (ALU) operation. In a typical ALU operation, two operands are output
from the Register File, the operation is executed, and the result is stored back in
the Register File in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register
pointers for Data Space addressing enabling efficient address calculations.
One of the these address pointers can also be used as an address pointer for
look up tables in Flash Program memory. These added function registers are the
16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between
a constant and a register. Single register operations can also be executed in the
ALU. After an arithmetic operation, the Status Register is updated to reflect
information about the result of the operation.
The Program flow is provided by conditional and unconditional jump and call
instructions, able to directly address the whole address space. Most AVR
instructions have a single 16-bit word format. Every Program memory address
contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program
section and the Application program section. Both sections have dedicated Lock
Bits for write and read/write protection. The SPM instruction that writes into the
Application Flash memory section must reside in the Boot program section.
During interrupts and subroutine calls, the return address Program Counter (PC)
is stored on the Stack. The Stack is effectively allocated in the general data
SRAM, and consequently the Stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initialize the SP in the reset
routine (before subroutines or interrupts are executed). The Stack Pointer SP is
read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory
maps.
A flexible interrupt module has its control registers in the I/O space with an
additional global interrupt enable bit in the Status Register. All interrupts have a
separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority
18
in accordance with their Interrupt Vector position. The lower the Interrupt Vector
address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as
Control Registers, SPI, and other I/O functions. The I/O Memory can be
accessed directly, or as the Data Space locations following those of the Register
File, 0x20 - 0x5F.
6.7 Internal Registers
Arithmetic Logic Unit ALU
The high-performance AVR ALU operates in direct connection with all the 32
general purpose working registers. Within a single clock cycle, arithmetic
operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main
categories arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned
multiplication and fractional format. See the Instruction Set section for a
detailed description.
Status Register
The Status Register contains information about the result of the most recently
executed arithmetic instruction. This information can be used for altering program
flow in order to perform conditional operations. Note that the Status Register is
updated after all ALU operations, as specified in the Instruction Set Reference.
This will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine
and restored when returning from an interrupt. This must be handled by software.
The AVR Status Register SREG is defined as:
Bit 7 - I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers.
If the Global Interrupt Enable Register is cleared, none of the interrupts are
enabled independent of the individual interrupt enable settings. The I-bit is
cleared by hardware after an interrupt has occurred, and is set by the RETI
instruction to enable subsequent interrupts. The I-bit can also be set and cleared
19
by the application with the SEI and CLI instructions, as described in the
Instruction Set Reference.
Bit 6 - T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as
source or destination for the operated bit. A bit from a register in the Register File
can be copied into T by the BST instruction, and a bit in T can be copied into a bit
in a register in the Register File by the BLD instruction.
Bit 5 - H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half
Carry is useful in BCD arithmetic. See the Instruction Set Description for
detailed information.
Bit 4 - S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Twos
Complement Overflow Flag V. See the Instruction Set Description for detailed
information.
Bit 3 - V: Twos Complement Overflow Flag
The Twos Complement Overflow Flag V supports twos complement arithmetics.
See the Instruction Set Description for detailed information.
Bit 2 - N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic
operation. See the Instruction Set Description for detailed information.
Bit 1 - Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See
the Instruction Set Description for detailed information.
Bit 0 - C: Carry Flag
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the
Instruction Set Description for detailed information.
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In
order to achieve the required performance and flexibility, the following
input/output schemes are supported by the Register File:
One 8-bit output operand and one 8-bit result input.
Two 8-bit output operands and one 8-bit result input.
Two 8-bit output operands and one 16-bit result input.
One 16-bit output operand and one 16-bit result input.
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Figure 6.7 shows the structure of the 32 general purpose working registers in the
CPU.
Most of the instructions operating on the Register File have direct access to all
registers, and most of them are single cycle instructions.
As shown in Figure 5.7, each register is also assigned a Data memory address,
mapping them directly into the first 32 locations of the user Data Space. Although
not being physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer
Registers can be set to index any register in the file.
6.8 Oscillator
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier
which can be configured for use as an On-chip Oscillator, as shown in Figure 11.
Either a quartz crystal or a ceramic resonator may be used. The CKOPT Fuse
selects between two different Oscillator amplifier modes. When CKOPT is
programmed, the Oscillator output will oscillate a full rail-to-rail swing on the
output. This mode is suitable when operating in a very noisy environment or
when the output from XTAL2 drives a second clock buffer. This mode has a wide
frequency range. When CKOPT is unprogrammed, the Oscillator has a smaller
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output swing. This reduces power consumption considerably. This mode has a
limited frequency range and it cannot be used to drive other clock buffers.
For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed
and 16 MHz with CKOPT programmed. C1 and C2 should always be equal for
both crystals and resonators. The optimal value of the capacitors depends on the
crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. Some initial guidelines for choosing
capacitors for use with crystals are given in Table 4. For ceramic resonators, the
capacitor values given by the manufacturer should be used.
Figure 6.8a Crystal Oscillator Connections

The Oscillator can operate in three different modes, each optimized for a specific
frequency range. The operating mode is selected by the fuses CKSEL3..1 bits as
shown in Table Table 5.8b.
Table 6.8b. Crystal Oscillator Operating Modes
Note: 1.This option should not be used with crystals, only with ceramic
resonators.
External Clock
22
To drive the device from an external clock source, XTAL1 should be driven as
shown in Figure 13. To run the device on an external clock, the CKSEL Fuses
must be programmed to 0000. By programming the CKOPT Fuse, the user can
enable an internal 36 pF capacitor between XTAL1 and GND, and XTAL2 and
GND.
Figure 6.8c External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT
Fuses as shown in Table 5.8d .
Table 6.8d Start-up Times for the External Clock Selection
When applying an external clock, it is required to avoid sudden changes in the

applied clock frequency to ensure stable operation of the MCU. A variation in
frequency of more than 2% from one clock cycle to the next can lead to
unpredictable behavior. It is required to ensure that the MCU is kept in Reset
during such changes in the clock frequency.
Timer/Counter Oscillator
For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and
TOSC2), the crystal is connected directly between the pins. By programming the
CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2,
thereby removing the need for external capacitors. The Oscillator is optimized for
23
use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1
is not recommended.
Note: The Timer/Counter Oscillator uses the same type of crystal oscillator as
Low-Frequency Oscillator and the internal capacitors have the same nominal
value of 36 p F.
6.9 Power Saving Modes
Idle Mode
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU
enter Idle mode, stopping the CPU but allowing SPI, USART, Analog
Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts CLKCPU
and CLKFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well
as internal ones like the Timer Overflow and USART Transmit Complete
interrupts. If wake-up from the Analog Comparator interrupt is not required, the
Analog Comparator can be powered down by setting the ACD bit in the Analog
Comparator Control and Status Register ACSR. This will reduce power
consumption in Idle mode. If the ADC is enabled, a conversion starts
automatically when this mode is entered.
ADC Noise Reduction Mode
When the SM2.0 bits are written to 001, the SLEEP instruction makes the MCU
enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the
external interrupts, the Two-wire Serial Interface address watch, Timer/Counter2
and the Watchdog to continue operating (if enabled). This sleep mode basically
halts CLK/O, CLKCPU, and CLKFLASH, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution
measurements. If the ADC is enabled, a conversion starts automatically when
this mode is entered. Apart form the ADC Conversion Complete interrupt, only an
External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial
Interface address match interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM
ready interrupt, or an external level interrupt on INT0 or INT1, can wake up the
MCU from ADC Noise Reduction mode.
Power-down Mode
When the SM2.0 bits are written to 010, the SLEEP instruction makes the MCU
enter Power-down mode. In this mode, the External Oscillator is stopped, while
the external interrupts, the Two-wire Serial Interface address watch, and the
Watchdog continue operating (if enabled). Only an External Reset, a Watchdog
Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt,
24
or an external level interrupt on INT0 or INT1, can wake up the MCU. This sleep
mode basically halts all generated clocks, allowing operation of asynchronous
modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down
mode, the changed level must be held for some time to wake up the MCU. Refer
to External Interrupts on page 66 for details.
When waking up from Power-down mode, there is a delay from the wake-up
condition occurs until the wake-up becomes effective. This allows the clock to
restart and become stable after having been stopped. The wake-up period is
defined by the same CKSEL Fuses that define the Reset Time-out period, as
described in Clock Sources.
Power-save Mode
When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU
enter Power-save mode. This mode is identical to Power-down, with one
exception:
If Timer/Counter2 is clocked asynchronously, i.e. the AS2 bit in ASSR is set,
Timer/Counter2 will run during sleep. The device can wake up from either Timer
Overflow or Output Compare event from Timer/Counter2 if the corresponding
Timer/Counter2 interrupt enable bits are set in TIMSK, and the global interrupt
enable bit in SREG is set.
If the asynchronous timer is NOT clocked asynchronously, Power-down mode is
recommended instead of Power-save mode because the contents of the
registers in the asynchronous timer should be considered undefined after wakeup in Power-save mode if AS2 is 0.
This sleep mode basically halts all clocks except CLKASY, allowing operation
only of asynchronous modules, including Timer/Counter 2 if clocked
asynchronously.
Standby Mode
When the SM2..0 bits are 110 and an external crystal/resonator clock option is
selected, the SLEEP instruction makes the MCU enter Standby mode. This mode
is identical to Power-down with the exception that the Oscillator is kept running.
From Standby mode, the device wakes up in 6 clock cycles.
Brown-out Detector
If the Brown-out Detector is not needed in the application, this module should be
turned off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be
enabled in all sleep modes, and hence, always consume power. In the deeper
sleep modes, this will contribute significantly to the total current consumption.
25
Refer to Brown-out Detection on page 40 for details on how to configure the

Brown-out Detector.
Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out
Detector, the Analog Comparator or the ADC. If these modules are disabled as
described in the sections above, the internal voltage reference will be disabled
and it will not be consuming power. When turned on again, the user must allow
the reference to start up before the output is used. If the reference is kept on in
sleep mode, the output can be used immediately. Refer to Internal Voltage
Reference on page 42 for details on the start-up time.
Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be
turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes,
and hence, always consume power. In the deeper sleep modes, this will
contribute significantly to the total current consumption. Refer to Watchdog
Timer on page 43 for details on how to configure the Watchdog Timer.
When entering a sleep mode, all port pins should be configured to use minimum
power. The most important thing is then to ensure that no pins drive resistive
loads. In sleep modes where the both the I/O clock (clkI/O) and the ADC clock
(clkADC) are stopped, the input buffers of the device will be disabled. This
ensures that no power is consumed by the input logic when not needed. In some
cases, the input logic is needed for detecting wake-up conditions, and it will then
be enabled. Refer to the section Digital Input Enable and Sleep Modes on page
55 for details on which pins are enabled. If the input buffer is enabled and the
input signal is left floating or have an analog signal level close to VCC/2, the
input buffer will use excessive power.
6.10 Reset Sources
The ATmega16 has four sources of Reset:
Power-on Reset. The MCU is reset when the supply voltage is below the Poweron Reset threshold (VPOT).
External Reset. The MCU is reset when a low level is present on the RESET pin
for longer than the minimum pulse length.
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires
and the Watchdog is enabled.
Brown-out Reset. The MCU is reset when the supply voltage VCC is below the
Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at
1 MHz. This is the typical value at VCC = 5V. See characterization data for typical
26
values at other VCC levels. By controlling the Watchdog Timer prescaler, the
Watchdog Reset interval can be adjusted as shown in Table 17 on page 44. The
WDR Watchdog Reset instruction resets the Watchdog Timer.
The Watchdog Timer is also reset when it is disabled and when a Chip Reset
occurs. Eight different clock cycle periods can be selected to determine the reset
period. If the reset period expires without another Watchdog Reset, the
ATmega16 resets and executes from the Reset Vector. For timing details on the
Watchdog Reset.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence
must be followed when the Watchdog is disabled. Refer to the description of the
Watchdog Timer Control Register for details.
Figure 6.10 Watchdog Timer

Watchdog Timer Control Register WDTCR
Bits 7..5 - Res: Reserved Bits
These bits are reserved bits in the ATmega16 and will always read as zero.
Bit 4 - WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the
Watchdog will not be disabled. Once written to one, hardware will clear this bit
after four clock cycles. Refer to the description of the WDE bit for a Watchdog
disable procedure. In Safety Level 1 and 2, this bit must also be set when
changing the prescaler bits.
27
6.11 Interrupts
This section describes the specifics of the interrupt handling performed by the
ATmega16. For a general explanation of the AVR interrupt handling,
Table 6.11 Reset and Interrupt Vectors

Interrupt Vectors in ATmega16
When the IVSEL bit in GICR is set, Interrupt Vectors will be moved to the start of
the boot Flash section. The address of each Interrupt Vector will then be the
address in this table added to the start address of the boot Flash section.
Table shows reset and Interrupt Vectors placement for the various combinations
of BOOTRST and IVSEL settings. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be
placed at these locations. This is also the case if the Reset Vector is in the
Application section while the Interrupt Vectors are in the boot section or vice
versa.
28
6.12 I/O Ports

All AVR ports have true Read-Modify-Write functionality when used as general
digital I/O ports. This means that the direction of one port pin can be changed
without unintentionally changing the direction of any other pin with the SBI and
CBI instructions. The same applies when changing drive value (if configured as
output) or enabling/disabling of pull-up resistors (if configured as input). Each
output buffer has symmetrical drive characteristics with both high sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port
pins have individually selectable pull-up resistors with a supply-voltage invariant
resistance. All I/O pins have protection diodes to both VCC and Ground as
indicated in Figure 5.12. Refer to Electrical Characteristics on page 242 for a
complete list of parameters.
Figure 6.12 I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower
case x represents the numbering letter for the port, and a lower case n
represents the bit number. However, when using the register or bit defines in a
program, the precise form must be used (i.e., PORTB3 for bit 3 in Port B, here
documented generally as PORTxn).
Three I/O memory address locations are allocated for each port, one each for the
Data Register PORTx, Data Direction Register DDRx, and the Port Input Pins
PINx. The Port Input Pins I/O location is read only, while the Data Register and
the Data Direction Register are read/write. In addition, the Pull-up Disable PUD
bit in SFIOR disables the pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in Ports as General Digital
I/O . Most port pins are multiplexed with alternate functions for the peripheral
features on the device. How each alternate function interferes with the port pin is
described in Alternate Port Functions on page 56. Refer to the individual
module sections for a full description of the alternate functions.
29
Note that enabling the alternate function of some of the port pins does not affect
the use of the other pins in the port as general digital I/O.
Special Function IO Register:
Bit 2 - PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if
the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn,
PORTxn} = 0b01). See Configuring the Pin on page 52 for more details about
this feature
Table 6.21a Port B Pins Alternate Functions

Alternate Functions of Port B
The alternate pin configuration is as follows:
XTAL2/TOSC2 - Port B, Bit 7
30
XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or
Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be
used as an I/O pin.
TOSC2: Timer Oscillator pin 2. Used only if internal calibrated RC Oscillator is
selected as chip clock source, and the asynchronous timer is enabled by the
correct setting in ASSR. When the AS2 bit in ASSR is set (one) to enable
asynchronous clocking of Timer/Counter2, pin PB7 is disconnected from the port,
and becomes the inverting output of the Oscillator amplifier. In this mode, a
crystal Oscillator is connected to this pin, and the pin cannot be used as an I/O
pin.
If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0.
XTAL1/TOSC1 - Port B, Bit 6
XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal
calibrated RC Oscillator. When used as a clock pin, the pin can not be used as
an I/O pin.
TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is
selected as chip clock source, and the asynchronous timer is enabled by the
correct setting in ASSR. When the AS2 bit in ASSR is set (one) to enable
asynchronous clocking of Timer/Counter2, pin PB6 is disconnected from the port,
and becomes the input of the inverting Oscillator amplifier. In this mode, a crystal
Oscillator is connected to this pin, and the pin can not be used as an I/O pin.
If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.
SCK - Port B, Bit 5
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI
is enabled as a Slave, this pin is configured as an input regardless of the setting
of DDB5. When the SPI is enabled as a Master, the data direction of this pin is
controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up
can still be controlled by the PORTB5 bit.
MISO - Port B, Bit 4
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a Master, this pin is configured as an input regardless of the setting of
DDB4. When the SPI is enabled as a Slave, the data direction of this pin is
MOSI/OC2 - Port B, Bit 3
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI
is enabled as a Slave, this pin is configured as an input regardless of the setting
of DDB3. When the SPI is enabled as a Master, the data direction of this pin is
31
OC2, Output Compare Match Output: The PB3 pin can serve as an external
output for the Timer/Counter2 Compare Match. The PB3 pin has to be configured
as an output (DDB3 set (one)) to serve this function. The OC2 pin is also the
output pin for the PWM mode timer function.
SS/OC1B - Port B, Bit 2
SS: Slave Select input. When the SPI is enabled as a Slave, this pin is
configured as an input regardless of the setting of DDB2. As a Slave, the SPI is
activated when this pin is driven low. When the SPI is enabled as a Master, the
data direction of this pin is controlled by DDB2. When the pin is forced by the SPI
to be an input, the pull-up can still be controlled by the PORTB2 bit.
OC1B, Output Compare Match output: The PB2 pin can serve as an external
output for the Timer/Counter1 Compare Match B. The PB2 pin has to be
configured as an output (DDB2 set (one)) to serve this function. The OC1B pin is
also the output pin for the PWM mode timer function.
OC1A - Port B, Bit 1
OC1A, Output Compare Match output: The PB1 pin can serve as an external
output for the Timer/Counter1 Compare Match A. The PB1 pin has to be
configured as an output (DDB1 set (one)) to serve this function. The OC1A pin is
also the output pin for the PWM mode timer function.
ICP1 - Port B, Bit 0
ICP1 - Input Capture Pin: The PB0 pin can act as an Input Capture Pin for
Timer/Counter1.
Table 5.12b Port C Pins Alternate Functions

The alternate pin configuration is as follows:
SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while
MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
32
RESET - Port C, Bit 6

RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions
as a normal I/O pin, and the part will have to rely on Power-on Reset and Brownout Reset as its reset sources. When the RSTDISBL Fuse is unprogrammed, the
reset circuitry is connected to the pin, and the pin can not be used as an I/O pin.
If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0.
SCL/ADC5 - Port C, Bit 5
SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one)
to enable the Two-wire Serial Interface, pin PC5 is disconnected from the port
and becomes the Serial Clock I/O pin for the Two-wire Serial Interface. In this
mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on
the input signal, and the pin is driven by an open drain driver with slew-rate
limitation.
SDA/ADC4 - Port C, Bit 4
SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one)
to enable the Two-wire Serial Interface, pin PC4 is disconnected from the port
and becomes the Serial Data I/O pin for the Two-wire Serial Interface. In this
mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on
the input signal, and the pin is driven by an open drain driver with slew-rate
limitation.
PC4 can also be used as ADC input Channel 4. Note that ADC input channel 4
uses digital power.
ADC3 - Port C, Bit 3
uses analog power.
uses analog power.
uses analog power.
ADCO - Port C, Bit 0
uses analog power.
Overriding Signals for Alternate Functions in PC6..PC4
33
Overriding Signals for Alternate Functions in PC3. PC0(1)
Note 1: When enabled, the Two-wire Serial Interface enables slew-rate controls
on the output pins PC4 and PC5. This is not shown in the figure. In addition,
spike filters are connected between the AIO outputs shown in the port figure and
the digital logic of the TWI module.
34
Port D Pins Alternate Functions

AINO - Port D, Bit 6
AIN0, Analog Comparator Positive Input. Configure the port pin as input with the
internal pull-up switched off to avoid the digital port function from interfering with
the function of the Analog Comparator.
T1 - Port D, Bit 5 T1, Timer/Counter1 counter source.
XCK/TO - Port D, Bit 4
XCK, USART external clock. T0, Timer/Counter0
counter source.
INT1 - Port D, Bit 3
INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt
source.
INTO - Port D, Bit 2
INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt
source.
TXD - Port D, Bit 1
TXD, Transmit Data (Data output pin for the USART). When the USART
Transmitter is enabled, this pin is configured as an output regardless of the value
of
RXD - Port D, Bit 0
RXD, Receive Data (Data input pin for the USART). When the USART Receiver
is enabled this pin is configured as an input regardless of the value of DDD0.
When the USART forces this pin to be an input, the pull-up can still be controlled
by the PORTD0 bit.
Register Description for I/O Ports
The Port B Data Register PORTB
35
The Port B Data Direction Register DDRB
The Port B Input Pins Address PINB
The Port C Data Register PORTC
The Port C Data Direction Register DDRC
The Port C Input Pins Address PINC
The Port D Data Register PORTD
The Port D Data Direction Register DDRD
36
The Port D Input Pins Address PIND
5.13 External Interrupts

The external interrupts are triggered by the INT0, and INT1 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0.1 pins are configured as
outputs. This feature provides a way of generating a software interrupt. The
external interrupts can be triggered by a falling or rising edge or a low level. This
is set up as indicated in the specification for the MCU Control Register
MCUCR. When the external interrupt is enabled and is configured as level
triggered, the interrupt will trigger as long as the pin is held low. Note that
recognition of falling or rising edge interrupts on INT0 and INT1 requires the
presence of an I/O clock, described in Clock Systems and their Distribution on
page 25. Low level interrupts on INT0/INT1 are detected asynchronously. This
implies that these interrupts can be used for waking the part also from sleep
modes other than idle mode. The I/O clock is halted in all sleep modes except
idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down
mode, the changed level must be held for some time to wake up the MCU. This
makes the MCU less sensitive to noise. The changed level is sampled twice by
the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 s
(nominal) at 5.0V and 25C. The frequency of the Watchdog Oscillator is voltage
dependent as shown in Electrical Characteristics on page 242. The MCU will
wake up if the input has the required level during this sampling or if it is held until
the end of the start-up time. The start-up time is defined by the SUT Fuses as
described in System Clock and Clock Options. If the level is sampled twice by
the Watchdog Oscillator clock but disappears before the end of the start-up time,
the MCU will still wake up, but no interrupt will be generated. The required level
must be held long enough for the MCU to complete the wake up to trigger
General Interrupt Flag Register GIFR
37
Bit 7 - INTF1: External Interrupt Flag 1

When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set
(one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will
jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one
to it. This flag is always cleared when INT1 is configured as a level interrupt.
Bit 6 - INTF0: External Interrupt Flag 0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU will
jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one
to it. This flag is always cleared when INT0 is configured as a level interrupt.
5.14 Timer/Counter:
The Timer/Counter is a synchronous design and the timer clock (clkT0) is
therefore shown as a clock enable signal in the following figures. The figures
include information on when Interrupt Flags are set. Figure 28 contains timing
data for basic Timer/Counter operation. The figure shows the count sequence
close to the MAX value.
Timer/Counter Timing Diagram, No Prescaling
Figure 5.14 shows the same timing data, but with the prescaler enabled.
Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
38
8-bit Timer/Counter Register Description

Timer/Counter Control Register TCCR0
The three clock select bits select the clock source to be used by the
Timer/Counter.
Table 5.14 Clock Select Bit Description

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin
will clock the counter even if the pin is configured as an output. This feature
allows software control of the counting.
Timer/Counter Register TCNT0
39
The Timer/Counter Register gives direct access, both for read and write
operations, to the Timer/Counter unit 8-bit counter.
Timer/Counter Interrupt Mask Register TIMSK
Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set
(one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding
interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0
bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 0 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0.
TOV0 is cleared by hardware when executing the corresponding interrupt
Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and
TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
Bit 0 - TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0.
TOV0 is cleared by hardware when executing the corresponding interrupt
Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and
TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
16-bit Timer/Counter1
40
The 16-bit Timer/Counter unit allows accurate program execution timing (event
management), wave generation, and signal timing measurement. The main
features are:
True 16-bit Design (i.e., allows 16-bit PWM)
Two Independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceller
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
Most register and bit references in this section are written in general form. A
lower case n replaces the Timer/Counter number, and a lower case x replaces
the Output Compare unit channel. However, when using the register or bit
defines in a program, the precise form must be used i.e., TCNT1 for accessing
Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 32. For
the actual placement of I/O pins, refer to Pin Configurations on page 2. CPU
accessible I/O Registers, including I/O bits and I/O pins, are shown in bold.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin
will clock the counter even if the pin is configured as an output. This feature
allows software control of the counting.
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1)
give direct access, both for read and for write operations, to the Timer/Counter
unit 16-bit counter. To ensure that both the high and Low bytes are read and
written simultaneously when the CPU accesses these registers, the access is
performed using an 8-bit temporary High byte Register (TEMP). This temporary
register is shared by all the other 16-bit registers. See Accessing 16-bit
Registers on page 79. Modifying the counter (TCNT1) while the counter is
running introduces a risk of missing a Compare Match between TCNT1 and one
of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the Compare Match on the
following timer clock for all compare units. The Output Compare Registers
contain a 16-bit value that is continuously compared with the counter value
(TCNT1). A match can be used to generate an Output Compare Interrupt, or to
generate a waveform output on the OC1x pin. The Output Compare Registers
41
are 16-bit in size. To ensure that both the high and Low bytes are written
simultaneously when the CPU writes to these registers, the access is performed
using an 8-bit temporary High byte Register (TEMP). This temporary register is
shared by all the other 16-bit registers.
Input Capture Register 1 ICR1H and ICR1L
The Input Capture is updated with the counter (TCNT1) value each time an event
occurs on the ICP1 pin (or optionally on the Analog Comparator Output for
Timer/Counter1). The Input Capture can be used for defining the counter TOP
value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low
bytes are read simultaneously when the CPU accesses these registers, the
access is performed using an 8-bit temporary High byte Register (TEMP). This
temporary register is shared by all the other 16-bit registers. Accessing 16-bit
Registers .
Timer/Counter Interrupt Mask Register TIMSK (1)
Note: 1. This register contains interrupt control bits for several Timer/Counters,
but only Timer1 bits are described in this section. The remaining bits are
described in their respective timer sections.
Bit 5 - TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set
(interrupts globally enabled), the Timer/Counter1 Input Capture Interrupt is
42
enabled. The corresponding Interrupt Vector (see Interrupts on page 46) is

executed when the ICF1 Flag, located in TIFR, is set.
Bit 4 - OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

(interrupts globally enabled), the Timer/Counter1 Output Compare a match
interrupt is enabled. The corresponding Interrupt Vector is executed when the
OCF1A Flag, located in TIFR, is set.
Bit 3 - OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
(interrupts globally enabled), the Timer/Counter1 Output Compare B match
interrupt is enabled. The corresponding Interrupt Vector is executed when the
OCF1B Flag, located in TIFR, is set.
Bit 2 - TOIE1: Timer/Counter1, Overflow Interrupt Enable
(interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled.
The corresponding Interrupt Vector is executed when the TOV1 Flag, located in
TIFR, is set.
Timer/Counter Interrupt Flag Register TIFR(1)
Note: 1. This register contains flag bits for several Timer/Counters, but only
Timer1 bits are described in this section. The remaining bits are described in their
respective timer sections.
Bit 5 - ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input
Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value,
the ICF1 Flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is
executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit
location.
Bit 4 - OCF1A: Timer/Counter1, Output Compare A Match Flag
43
This flag is set in the timer clock cycle after the counter (TCNT1) value matches
the Output Compare Register A (OCR1 A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt
Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to
its bit location.
Bit 3 - OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches
the Output Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B
Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt
Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to
its bit location.
Bit 2 - TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In normal and
CTC modes, the TOV1 Flag is set when the timer overflows. Refer to Table 39 on
page 99 for the TOV1 Flag behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt
Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to
its bit location.
8-bit Timer/Counter Register Description
Timer/Counter Control Register - TCCR2
Bit 7 - FOC2: Force Output Compare

The FOC2 bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to
zero when TCCR2 is written when operating in PWM mode. When writing a
logical one to the FOC2 bit, an immediate Compare Match is forced on the
waveform generation unit. The OC2 output is changed according to its COM21:0
bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the
value present in the COM21:0 bits that determines the effect of the forced
compare.
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC
mode using OCR2 as TOP.
The FOC2 bit is always read as zero.
Bit 6, 3 - WGM21:0: Waveform Generation Mode
44
These bits control the counting sequence of the counter, the source for the
maximum (TOP) counter value, and what type of waveform generation to be
used. Modes of operation supported by the Timer/Counter unit are: Normal
mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse
Width Modulation (PWM) modes. See Table 42 and "Modes of Operation" on
page 110.
Table Waveform Generation Mode Bit Description
Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the
WGM21:0 definitions. However, the functionality and location of these bits are
compatible with previous versions of the timer.
Bit 5:4 - COM21:0: Compare Match Output Mode
These bits control the Output Compare Pin (OC2) behavior. If one or both of the
COM21:0 bits are set, the OC2 output overrides the normal port functionality of
the I/O pin it is connected to. However, note that the Data Direction Register
(DDR) bit corresponding to OC2 pin must be set in order to enable the output
driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on
the WGM21:0 bit setting. Table 43 shows the COM21:0 bit functionality when the
WGM21:0 bits are set to a normal or CTC mode (non-PWM).
6.15 USART
The Universal Synchronous and Asynchronous serial Receiver and Transmitter
(USART) is a highly-flexible serial communication device. The main features are:
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data Overrun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX
Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
45
CHAPTER 7
LCD DIAPLAY
16x2 alphanumeric LCD display is used here for monitoring the channel
temperature and power status of testing device. This LCD display is initialized
and controlled by the micro controller.
7.1. LCD CONNECTIONS:2x16 DOT MATRIX LCD DISPLAY
VSS VDD
RS R/W
E D0
CONTROL PINS
D1 D2 D3 D4 D5 D6
D7
DATA PINS
CONTRAST
WE ARE USING ONLY FOUR BIT DATA MODE AND CONTROL PINS ONLY .
In four bit mode we needed only D4 to D7.
RS COMMAND when its one. Otherwise data mode
R/W this pin is one means its write mode, otherwise read mode. For busy
checking
E this pin using for enable the LCD module. E = 1, indicates LCD module is
activated.
Liquid Crystal Displays are created by sandwiching a thin (10-12 micro mm) layer
of a liquid crystal fluid between two glass plates. A transparent, electrically
conductive film or back plane is put up on the rear glass sheet. The transparent
sections of the conductive film in the shape of the desired characters are coated
on the front glass plate. When a voltage is applied between a segment and the
back plane, an electric field is created in the region under the segment. This
electric field changes the transmission of light through the region under the
segment film.
7.2 Liquid Crystal Display Description: In this project, JHD 162A Liquid Crystal Display (16x2), which is shown in Figure
7.2 a is interfaced with the CPU.
46
The features of 16x2A LCD is as follows: 16 Characters x 2 Lines

5x7DotswithCursor
Built in Controller
+5v Power Supply
1/16 Duty Circle.
The pin description of the JHD 162A LCD without backlight is as shown in Table
7.2b. If the LCD is having Backlight, then it will have two more pins with pin
numbers 15 & 16 connected to VCC and GND respectively.
Pin
Symbol Level I/O Function
number
1
Vss
Power supply (GND)
Vcc
Power supply (+5V)
Vee
Contrast adjust
RS
0/1
0
=
Instruction
1 = Data input
R/W
0/1
0 = Write to LCD module

1 = Read from LCD module
1, 1->0 I
DB0
0/1
I/O Data bus line 0 (LSB)
DB1
0/1
I/O Data bus line 1
DB2
0/1
I/O Data bus line 2
10
DB3
0/1
I/O Data bus line 3
11
DB4
0/1
I/O Data bus line 4
12
DB5
0/1
I/O Data bus line 5
13
DB6
0/1
I/O Data bus line 6
14
DB7
0/1
I/O Data bus line 7 (MSB)
input
snable signal
Table 7.2b
An LCD allows an application to output a very specific message (or prompt) to
the user, making the application much more user friendly and impressive. LCD's
are invaluable for displaying status messages and information during application
debug. ASCII-input LCDs even though they have these advantages, they have a
reputation of being difficult to hook up and get to work. Most alphanumeric LCD's
47
use a common controller chip and a common connector interface. Both of these
actions have resulted in alphanumeric LCDs that range in size from 8 characters
to 80 (arranged as 16x2, 40x2 or 20x4) and are interchangeable, without
requiring hardware or software changes.
The ASCII code to be displayed is 8 bits long and is sent to the LCD either 4 or 8
bits at time. If the 4-bit mode is used, two nibbles of data (sent high 4 bits then
low 4 bits with an E clock pulse with each nibble) are sent to make up a full 8-bit
transfer. The "E" clock is used to initiate the data transfer within the LCD. In the
LCD there is a cursor,
This specifies where the next data character is to be written. This cursor can be
moved or be made invisible to blink. The blinking function is very rarely used
because it is pretty obnoxious.
Sending parallel data either as 4 or 8 bits are the two primary modes of
operation. While there are secondary considerations and modes deciding how to
send the data to the LCD is more critical decision to be made for an LCD
interface application. 4-bit mode is best used when the speed required in an
application and at least 10 I/O pins are available. 4-bit mode requires minimum 6
bits. To wire a Microcontroller to an LCD 4-bit mode, just the top 4-bits (DB4-7)
are written as shown in the Figure 8.2c below:
Figure 7.2c Data Transfer using a 4-Bit Interface

Using a shift register so that a minimum of three I/O pins is required can further
reduce this. 8-bit mode could be used with a shift register, but a ninth bit (which
will be used as R/S) will be required.
48
The display contains two internal byte-wide registers, one for command (RS=0)
and the second for the characters to be displayed (RS=1). The R/S bit is used to
select whether data or an instruction is being transferred between the
Microcontroller and the LCD. If the bit is set, the byte at the current LCD cursor
position can be read or written. When the bit is reset, either an instruction is
being sent to the LCD or the execution status of the last instruction is read back
(whether it has completed or not).
The display contains two internal byte-wide registers, one for command (RS=0)
and the second for characters to be displayed (RS=1). It also contains a user
programmed RAM area (the character RAM) that can be programmed to
generate a desired character that can be formed using a dot matrix.
To distinguish between these two data areas, the hex command byte 80 will be
used to signify that the display RAM address 00h is chosen.
Port 1 is used to furnish the commands or data byte and ports 3.2 to 3.4 furnish
register select and read/write levels. The display takes varying amounts of time
to accomplish the functions. LCD bit 7 is monitored for a long high (bus) to
ensure the display is not over written. A slightly more complicated LCD display (4
lines* 40 characters) is currently being used in medical diagnostic systems to run
a very familiar program.
7.3 Getting The LCD To Display Text: After successfully initializing the LCD and turn it the display ON, one can begin to
display messages on the LCD by sending the correct instructions to it. Getting
the LCD to display text is a two-step process. First, the LCD's cursor must be
moved to the LCD address where the character is to be displayed. This is done
with the "DDRAM Address Set" command. Second, the actual character must be
written to the cursor in order to store it in the DDRAM at the cursor's location.
This is performed with the "CGRAM/DDRAM Data Write" command.
7.4 LCD Busy Flag Polling: The LCD will not accept new commands while it is busy with some internal
operation. This condition must be tested before sending a new command to the
LCD. The "Busy Flag/Address Read" instruction should be used for this purpose.
The BF bit in this instruction is the busy flag. When this bit is 1, LCD controller is
busy. When BF is 0, LCD is ready for the next command. In addition to busy flag
polling, this instruction is used to determine where the address of the LCD cursor
is. Examples for Busy Flag testing using both 4-bit and 8-bit interfaces are shown
in figures 8.4a and 8.4b respectively.
49
Figure 7.4a Example of busy flag testing using a 4-bit interface.
Figure
7.4b
Example
of
busy
flag
testing
using
an
8-bit
interface.
7.5 Defining LCD Custom Characters: One of the nice features of the LCD is that it allows for the creation and use of up
to eight unique, user-defined characters. Character Generator RAM (CGRAM)
has been added to the LCD for this purpose. Before a custom character can be
used it must be created. Each character that can be displayed by the LCD is
composed of a 5 x 8 grid of pixels or dots. Each of these dots can be turned
either ON or OFF when a character is being displayed. Therefore, in order for the
LCD controller to display a character, it must have a definition of which of the
character dots need to be turned ON.
50
7.6 flow chart for LCD initialsation
51
INITILAZATION OF DISPLAY
(4 bit data interfacing)
POWER ON
Wait f or 15 ms or more
after Vcc risres to 4.5V
RS
R/W DB7 DB6 DB5 DB4
0
0
0
0
1
1
------------------------------------------------Function Set DL=1,8 bit interface data.
DL must set at H during this inilization
Wait for 4.1 m s
RS
R/W DB7 DB6 DB5 DB4
0
0
0
0
1
1
------------------------------------------------Function Set :DL=1,8 bit interface data.
Wait for 100 m icro sec
or m ore
RS
R/W DB7 DB6 DB5 DB4
0
0
0
0
1
1
------------------------------------------------Function Set :DL=1,8 bit interface data.
Chech for not busy
RS
R/W DB7 DB6 DB5 DB4
0
0
0
0
1
0
------------------------------------------------Function Set :DL=0,4 bit interface data
RS
R/W DB7 DB6 DB5 DB4
0
0
0
0
1
0
0
0
N
F
X
X
--------------------------------------------Function Set : DL=0.4bit interface data.
N=no.of l ine,F= character font
Chech for not busy
RS
R/W DB7 DB6 DB5 DB4
0
0
0
0
0
0
0
0
1
0
0
0
--------------------------------------------Display off
RS
R/W DB7 DB6 DB5 DB4
0
0
0
0
0
0
0
0
0
0
0
1
--------------------------------------------Display on
RS
R/W DB7 DB6 DB5 DB4
0
0
0
0
0
0
0
0
0
1
I/D
S
--------------------------------------------Entry mode set
End of initialization
52
7.7 INSTRUCTIONS OF LCD DISPLAY:Code

Instructio
Description
n
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Clear
display
Cursor
home
Entry
0
mode set
I/D
Display
On/Off
control
Cursor/di 0
splay
shift
S/C R/L *
53
Executi
on
time**
Clears
display 1.64mS
and
returns
cursor to the
home
position
(address 0).
Returns cursor 1.64mS
to home position
(address 0). Also
returns display
being shifted to
the
original
position.
DDRAM
contents
remains
unchanged.
Sets
cursor 40uS
move direction
(I/D), specifies to
shift the display
(S).
These
operations are
performed
during
data
read/write.
Sets On/Off of 40uS
all display (D),
cursor
On/Off
(C) and blink of
cursor position
character (B).
Sets
cursor- 40uS
move or displayshift (S/C), shift
direction (R/L).
DDRAM
contents
remains
Executi
Instructio Code
Description
on
n
time**
unchanged.
Function 0 0
0
0
1
DL N
F
*
*
Sets
interface 40uS
set
data length (DL),
number
of
display line (N)
and
character
font(F).
Set
0 0
0
1
CGRAM address
Sets
the 40uS
CGRAM
CGRAM
address
address.
CGRAM data is
sent
and
received
after
this setting.
Set
0 0
1
DDRAM address
Sets
the 40uS
DDRAM
DDRAM
address
address.
DDRAM data is
sent
and
received
after
this setting.
Read
0 1
BF CGRAM / DDRAM address
Reads Busy-flag 0uS
busy-flag
(BF) indicating
and
internal
address
operation
is
counter
being performed
and
reads
CGRAM
or
DDRAM address
counter contents
(depending on
previous
instruction).
Write to 1 0
write data
Writes data to 40uS
CGRAM
CGRAM
or
or
DDRAM.
DDRAM
Read
1 1
read data
Reads data from 40uS
from
CGRAM
or
CGRAM
DDRAM.
54
Instructio Code
Description
n
or
DDRAM
CHAPTER 8
55
Executi
on
time**
RS232 COMMUNICATION
8.1 INTRODUCTION:
The Serial Port is harder to interface than the Parallel Port. In most cases, any
device you connect to the serial port will need the serial transmission converted
back to parallel so that it can be used. This can be done using a UART. On the
software side of things, there are many more registers that you have to attend to
than on a Standard Parallel Port. (SPP)
1. Serial Cables can be longer than Parallel cables. The serial port transmits a '1'
as -3 to -
25 volts and a '0' as +3 to +25 volts where as a parallel port
transmits a '0' as 0v and
'1' as 5v. Therefore the serial port can have a
maximum swing of 50V compared to the
parallel port which has a maximum
swing of 5 Volts. Therefore cable loss is not going
to be as much of a problem
for serial cables as they are for parallel.

2. You don't need as many wires are parallel transmission. If your device needs
to be
mounted a far distance away from the computer then 3 core cable (Null
Modem Configuration) is going to be a lot cheaper that running 19 or 25 core

cable. However you must take into account the cost of the interfacing at each
end.
3. Microcontroller's have also proven to be quite popular recently. Many of these
have in
built SCI (Serial Communications Interfaces) which can be used to talk
to the outside
world. Serial Communication reduces the pin count of these
MCU's. Only two pins are
commonly used, Transmit Data (TXD) and Receive
Data (RXD) compared with at
least 8 pins if you use a 8 bit Parallel method
(You may also require a Strobe).

8.2 Hardware Properties:
Devices which use serial cables for their communication are split into two
categories. These are DCE (Data Communications Equipment) and DTE (Data
Terminal Equipment.) Data Communications Equipment are devices such as your
modem, TA adapter, plotter etc while Data Terminal Equipment is your Computer
or Terminal.
56
The electrical specifications of the serial port are contained in the EIA
(Electronics Industry Association) RS232C standard.
Figure8.2: Typical operating circuit

1. A "Space" (logic 0) will be between +3 and +25 Volts.
2. A "Mark" (Logic 1) will be between -3 and -25 Volts.
3. The region between +3 and -3 volts is undefined.
4. An open circuit voltage should never exceed 25 volts. (In Reference to GND)
5. A short circuit current should not exceed 500mA. The driver should be able to
handle this without damage.
Above is no where near a complete list of the EIA standard. Line Capacitance,
Maximum Baud Rates etc are also included. For more information please consult
the EIA RS232-C standard. It is interesting to note however, that the RS232C
standard specifies a maximum baud rate of 20,000 BPS!, which is rather slow by
today's standards. A new standard, RS-232D has been recently released.
8.3 PIN CONFIGURATION
57
Fig 8.3 pin configuration of Max232

8.4 Serial Pin out (D-9 Connector)
Serial Port D-Type 9 pin connector which is male on the back of the PC, thus you
will require a female connector on your device. Below is a table of pin
connections for the 9 pin D-Type connector.
Figure 8.4: D Type 9 Pin Connector

8.5 Null Modems
58
A Null Modem is used to connect two DTE's together. This is commonly used as
a cheap way to network games or to transfer files between computers using
Zmodem Protocol, Xmodem Protocol etc. This can also be used with many
Microprocessor Development Systems.
Figure8.5: Null Modem Wiring Diagram

Above is my preferred method of wiring a Null Modem. It only requires 3 wires
(TD, RD & SG) to be wired straight through thus is more cost effective to use with
long cable runs. The theory of operation is reasonably easy. The aim is to make
to computer think it is talking to a modem rather than another computer. Any data
transmitted from the first computer must be received by the second thus TD is
connected to RD. The second computer must have the same set-up thus RD is
connected to TD. Signal Ground (SG) must also be connected so both grounds
are common to each computer.
The Data Terminal Ready is looped back to Data Set Ready and Carrier Detect
on both computers. When the Data Terminal Ready is asserted active, then the
Data Set Ready and Carrier Detect immediately become active. At this point the
computer thinks the Virtual Modem to which it is connected is ready and has
detected the carrier of the other modem.
59
All left to worry about now is the Request to Send and Clear To Send. As both
computers communicate together at the same speed, flow control is not needed
thus these two lines are also linked together on each computer. When the
computer wishes to send data, it asserts the Request to Send high and as it's
hooked together with the Clear to Send, It immediately gets a reply that it is ok to
send and does so.
CHAPTER 9
REAL TIME CLOCK
60
9.1 DESCRIPTION
The DS1307 serial real-time clock (RTC) is a low-power, full binary-coded
decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are
transferred serially through an I2C, bidirectional bus. The clock/calendar provides
seconds, minutes, hours, day, date, month, and year information. The end of the
month date is automatically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates in either the 24-hour or
12-hour format with AM/PM indicator. The DS1307 has a built-in power-sense
circuit that detects power failures and automatically switches to the backup
supply. Timekeeping operation continues while the part operates from the backup
supply.
9.2 FEATURES
Minutes, Hours, Date of the Month, Month, Day of the week, and Year with LeapYear Compensation Valid Up to 2100
56-Byte, Battery-Backed, Nonvolatile (NV)
RAM for Data Storage
I2C Serial Interface
Programmable Square-Wave Output Signal
Automatic Power-Fail Detect and Switch circuitry.
Consumes Less than 500nA in Battery- Backup Mode with Oscillator Running
9.3 pin diagram of DS1307
VCC
R 16
1k2
R 10
10K
R 11
10K
C 12
100nf
C7
47uf
D8
LED
Y2
3 2 .7 6 8 K h z
1
2
3
4
U5
X1
X2
SQ
VBAT
GND
VCC
-O U T
SCL
SDA
8
7
6
5
9.4 operation of DS1307

The DS1307 is a
SCL
SDA
clock/calendar with
B T2
D S1307
3 V L i B a tte ry
battery-backed
61
56
low-power
bytes
SRAM.
of
The
clock/calendar provides seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is automatically adjusted for
months with fewer than 31 days, including corrections for leap year. The DS1307
operates as a slave device on the I2C bus. Access is obtained by implementing a
START condition and providing a device identification code followed by a register
address. Subsequent registers can be accessed sequentially until a STOP
condition is executed. When VCC falls below 1.25 x VBAT, the device terminates
an access in progress and resets the device address counter. Inputs to the
device will not be recognized at this time to prevent erroneous data from being
written to the device from an out-of-tolerance system. When VCC falls below
VBAT, the device switches into a low-current battery-backup mode. Upon powerup, the device switches from battery to VCC when VCC is greater than VBAT
+0.2V and recognizes inputs when VCC is greater than 1.25 x VBAT. The
schematic shows the main elements of the serial RTC.
CHAPTER 10
GSM MODEM MANUAL
62
GSM Modem Product, from Sparr Electronics limited (SEL), provides full
functional capability to Serial devices to send SMS and Data over GSM Network.
The product is available as Board Level or enclosed in Metal Box. The Board
Level product can be integrated in to Various Serial devices in providing them
SMS and Data capability and the unit housed in a Metal Enclosure can be kept
outside to provide serial port connection. The GSM Modem supports popular
"AT" command set so that users can develop applications quickly. The product
has SIM Card holder to which activated SIM card is inserted for normal use. The
power to this unit can be given from UPS to provide uninterrupted operation. This
product provides great feasibility for Devices in remote location to stay connected
which otherwise would not have been possible where telephone lines do not exist
10.2. Application areas
Mobile Transport vehicles.
LAN based SMS servers
Alarm notification of critical events including Servers
Network Monitoring and SMS reporting
Data Transfer applications from remote locations
Monitor and control of Serial services through GSM Network
Integration to custom software for Warehouse, Stock, Production, Dispatch
notification through SMS.
AMR- Automatic Meter Reading
And many more
10.3. Connection Diagram
Fig4.1 Connection Diagram

10.4. Block Diagram
10.4. Pinouts and details
63
Note :Short the pin numbers 2 and 3 of JP2 for TTL Serial Operations
Short the pin numbers 1 and 2 of JP2 for RS 232 Operations.
JP3 SERIAL TTL LEVEL SIGNALS
JP3 PIN NO
1
2
3
4
5
6
7
8
9
10
SIGNALS
RXD
CTS
DSR
DCD
RI
TXD
RTS
DTR
GROUND
4.6. Short Messages commands

Parameters definition
64
<da>
Destination Address, coded like GSM 03.40 TP-DA
<dcs>
Data Coding Scheme, coded like in document [5].
<dt>
Discharge Time in string format :yy/MM/dd,
<fo>
First Octet, coded like SMS-SUBMIT first octet in document [4],
default value is
17 for SMS-SUBMIT
<index>
Place of storage in memory.
<length>
Text mode (+CMGF=1): number of characters PDU mode
(+CMGF=0): length of the TP data unit in octets
<mem1>
Memory used to list, read and delete messages (+CMGL, +CMGR
and +CMGD).
<mem2>
Memory used to write and send messages (+CMGW, +CMSS).
<mid>
CBM Message Identifier.
<mr>
Message Reference.
<oa>
Originator Address.
<pid>
Protocol Identifier.
<pdu>
For SMS : GSM 04.11 SC address followed by GSM 03.40 TPDU in
hexadecimal format, coded as specified in doc [4] For CBS : GSM 03.41 TPDU in
hexadecimal
format
<ra>
Recipient Address.
<sca>
Service Center Address
<scts>
Service Center Time Stamp in string format :
yy/MM/dd,hh :mm :ss zz
(Year/Month/Day, Hour: Min: Seconds Time Zone)
<sn>
CBM Serial Number
<st>
Status of a SMS-STATUS-REPORT
<stat>
Status of message in memory.
<tooa>
Type-of-Address of <oa>.
<tora>
Type-of-Address of <ra>.
<tosca>
Type-of-Address of <sca>.
<total1>
Number of message locations in <mem1>.
<total2>
Number of messages locations in <mem2.
<used1>
Total number of messages locations in <mem1>.
<used2>
Total number of messages locations in <mem2.
<vp>
Validity Period of the short message, default value is 167
GSM ADVANTAGES
65
GSM providers are available almost in many countries

We can control the home appliances by sending a SMS to programmed home
automation kit with coded instructions by the authenticated programmer
simultaneously we will get a feedback and the status of the device. Since we
have an option of Roaming Service provided by the GSM service providers
hence we can get SMS at any place on the earth.
DISADVANTAGES
It requires a continuous electrical power supply for its proper working
We have to continuously recharge the GSM SIMCARD.
Maintenance cost is high i.e. service charges are more per SMS.
If the SIM gets damaged we need to reprogram with other number for security
purposes because the cost depends on the service provider.
CHAPTER 11
66
GPS MODEM
The GPS module L10 brings the high performance of the MTK positioning engine
to the industrial standard. The L10 supports 210 PRN channels. With 66 search
channels and 22 simultaneous tracking channels, it acquires and tracks satellites
in the shortest time even at indoor signal level. This versatile, stand-alone
receiver combines an extensive array of features with flexible connectivity
options. Their ease of integration results in fast time-to-market in a wide range of
automotive, consumer and industrial applications.
Compact GPS Module with Super Sensitivity Wireless makes smarter SMD Type
Advantages
210 PRN channels, with 66 search channels and 22
simultaneous tracking channels
-165dBm tracking sensitivity
Highest autonomous mode acquisition sensitivity, -148dBm
Low tracking power consumption, 38mA (passive antenna)
Full ESD protection on all pins
Embedded with one 4Mbits flash memory
Superior anti-jamming design for best integration with other wireless
application, such as WiFi, WiMax, CDMA and GSM
AGPS ready solution
Multi-path detection and correction for accurate navigation in harsh urban
canyon
Up to 10-Hz update rate
67
68
GPS DATA FORMAT:$GPRMC This message transfers recommended minimum specific GNSS data.
The $GPRMC message format is shown below.
Field
Format
Min chars
Max chars
Notes
Message ID
$GPRMC
RMC protocol
6
6
header.
Fix time to
UTC Time
hhmmss.sss 1,2,2.1
2,2,2.3
1ms accuracy.
A Data Valid.
Status
char
1
1
V Data invalid.
Degrees * 100
Latitude
Float
1,2.1
3,2.4
+ minutes.
N=north or
N/S Indicator
Char
1
1
S=south.
Degrees * 100
Longitude
Float
1,2.1
3,2.4
+ minutes.
E=east or
E/W indicator
Char
1
1
W=west.
Speed over
Speed over ground Float
1,1
5.3
ground in
knots.
Course over
Course over
Float
1.1
3.2
ground in
ground
degrees.
Date
ddmmyy
2,2,2
2,2,2
Current date.
Magnetic variation Blank
(0)
(0)
Not used.
E/W indicator
Blank
(0)
(0)
Not used.
Mode
Char
1
1
A Autonomous
Checksum
*xx
(0) 3
3
2 digits.
Message
ASCII 13,
<CR> <LF>
2
2
terminator
ASCII 10.
CHAPTER 12
69
SCHMETIC DIAGRAM
CHAPTER 13
70
PCB LAYOUT
71
CHAPTER 14
SOFTWARE
Embedded Device Technology is a transformational technology a technology
that is revolutionizing the way we function. Embedded Systems can be seen
everywhere from Wrist Watches, Washing Machines, Microwave Ovens and
Mobile Telephones to Automobiles, Aircrafts and Nuclear Power Plants.
Embedded Systems are the brains behind 90% of all electronic devices
worldwide. The explosion of Embedded System Technology is expected to
happen across product categories like office products, consumer products,
industrial automation products, automobiles, medical instrumentation, vending
machines, vehicles, communications infrastructure, etc.
An Embedded System is a combination of hardware and software designed to
control the additional hardware attached to the system. The software system is
completely encapsulated by the hardware that it controls. Embedded system
means the processor is embedded into that application or it is meant for that
specific application. Thus printer, keyboard, and video game player etc. are all
examples of devices performing specific application. In an Embedded System,
there is only one application software that is typically burned into ROM. An
Embedded System is time-constrained and often resource-constrained.
The brain of an Embedded System is the processor. It may be a general-purpose
microprocessor like Intel x86 family or a microcontroller like 8051 family. An
embedded product uses a microprocessor or microcontroller to do one specific
task only.
A microcontroller is a specific kind of microprocessor whose primary job is to
control the hardware it is attached to. A microcontroller has more pins dedicated
to carrying I/O signals as compared to microprocessor. A
72
Microcontroller has built-in memory and peripherals (single-chip computer).

Whereas a microprocessor has memory and supporting peripherals externally
connected.
COMPLIER
CodeVisionAVR
Features:1) Application that runs under Windows 2000, XP, Vista and Windows 7,
32bit and 64bit
2)
Easy to use Integrated Development Environment and ANSI C
compatible Compiler.
3) Editor with auto indentation, syntax highlighting for both C and AVR
assembler, function parameters and structure/union members
auto
complete.
4) Supported data types: bit, bool, char, int, short, long, float
5) Fast floating point library with hardware multiplier and enhanced core
instructions support for all the new AT mega chips
AVR specific extensions for: Accessing the EEPROM & FLASH memory areas
Bit level access to I/O registers
Interrupt support
Support for placing bit variables in the General Purpose I/O
Registers (GPIOR) available in the new chips (ATtiny2313,
ATmega48/88/168,
ATmega165/169/325/3250/329/3290/645/6450/649/6490,
ATmega1280/1281/2560/2561/640, ATmega406 and others)
Compiler optimizations:
Peephole optimizer
Advanced variables to register allocate, allows very efficient use
of the AVR architecture
Common Block Subroutine packing (what our competition calls
Code Compressor), replaces repetitive code sequences with
calls to subroutines. This optimizer is available as Standard in
CodeVisionAVR, at no additional costs, not like in our
competitors products.
Common sub-expression elimination
Loop optimization
Branch optimization
73
Subroutine call optimization

Cross-jumping optimization
Constant folding
Constant literal strings merging
Store-copy optimization
Dead code removing optimization
4 memory models: TINY (8 bit data pointers for chips with up to
256 bytes of RAM), SMALL (16 bit data pointers for chips with
more than 256 bytes of RAM), MEDIUM (for chips with 128k of
FLASH) and LARGE (for chips with 256k or more FLASH). The
MEDIUM and LARGE memory models allow full FLASH
addressing for chips like ATmega128, ATmega1280,
ATmega2560, etc, the compiler handling the RAMPZ register
totally transparently for the programmer. This feature is
available as Standard in CodeVisionAVR, at no additional costs,
not like in our competitors products.
User selectable optimization for code Size or Speed
Supplementary libraries for: Alphanumeric LCD modules, with possibility to allocate the LCD
signals to any pin of any I/O port
Graphic LCD modules with SSD1289, KS0108, SED1335,
S1D13700, SED1520, SED1530, SPLC501C, ST7565, T6963C
and PCD8544 (Nokia 3310, 5510) controllers, with possibility to
allocate the LCD signals to any pin of any I/O port
software bit-banged Philips IC Bus (master mode) with
possibility to allocate the signals to any pin of any I/O port
National Semiconductor LM75 Temperature Sensor
Maxim/Dallas Semiconductor DS1621 Thermometer/Thermostat
Philips PCF8563 and PCF8583 Real Time Clocks
Maxim/Dallas Semiconductor DS1302 and DS1307 Real Time
Clocks
Maxim/Dallas Semiconductor 1 Wire protocol
Maxim/Dallas Semiconductor DS1820/DS18B20/DS1822 1 Wire
Temperature Sensors
Maxim/Dallas Semiconductor DS2430/DS2433 1 Wire
EEPROMs
SPI
TWI (master and slave modes) for both AVR and XMEGA
devices
74
MMC/SD/SD HC FLASH Memory Card drivers and FAT12,

FAT16, FAT32 access libraries for both AVR and XMEGA
devices
Power management
Delays
BCD and Gray code conversion
Possibility to insert inline assembler code directly in the C source file

VERY EFFICIENT USE OF RAM: Constant character strings are stored only in
FLASH memory and aren't copied to RAM and accessed from there, like in other
compilers for the AVR
C Source level debugging, with COFF symbol file generation, allows variable
watching (including structures and unions) and the use of the Terminal I/O in
Atmels AVR Studio Debugger
Fully compatible with Atmels In-Circuit Emulators: AVR JTAG-ICE, AVR Dragon,
etc.
75
CHAPTER 15
CONCLUSION
We achieved final results of what our aim. We are able to receive data from GPS
module. And extract longitude, latitude and time from GPRMC format. Then we
are able show on LCD. And every minute we send this data to our mobile. All
these are success fully done.
For future development, we are looking for interfacing key pad. By using key pad,
we need to edit few parameters of unit. Like SMS sending number editing and
SMS intervals.
At the receiving side, we need to add another unit for receiving data and send it
to computer. It was useful to track visual on Google earth. System side
application also need for it.
And we are planning to add memory card or EEPROM for logging the data of
vehicle tracking.
76
BIBLIOGRAPHY
Books
1. Frank Vahid and Tony Givargis, Embedded System Design, 2002.
2. Kenneth J. Ayala, The 8051 Micro-Controller, Penram International
Publishing, 1996.
3. The 8051 Microcontroller and Embedded Systems, PEARSON Education
Muhammad Ali Mazidi, Janice Gillispie Mazidi
4. Atmel Micro-Controller Data Book, Atmel Corporation, 1997.
5. Keil Software Datasheets.
Websites
1. www.atmel.com
2. www.keil.com
3. www.google.com
77
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CHAPTER 1

Union Galileo positioning system, Chinese Compass

navigation system, and Indian Regional Navigational Satellite System.

Basic concept of GPS

Max232 was populated for debugging

purpose. Key board connecter provided for future applications

A full wave rectifier

switching mode power supply, switching regulator is operated either in cut-off or

Pin description of LM7805 &LM7809

Monolithic IC voltage regulator:

A voltage regulator is a circuit that supplies a constant voltage regardless

FIXED VOLTAGE REGULATORS:General Description:

Master/Slave SPI Serial Interface

6.5 Pin Descriptions

VCC -------------------------------------------Digital supply voltage

the Program memory. This concept enables instructions to be executed in every

Bit 7 - I: Global Interrupt Enable

Figure 6.8a Crystal Oscillator Connections

Figure 6.8c External Clock Drive Configuration

When applying an external clock, it is required to avoid sudden changes in the

Refer to Brown-out Detection on page 40 for details on how to configure the

Figure 6.10 Watchdog Timer

Table 6.11 Reset and Interrupt Vectors

6.12 I/O Ports

Figure 6.12 I/O Pin Equivalent Schematic

Bit 2 - PUD: Pull-up Disable

Table 6.21a Port B Pins Alternate Functions

Table 5.12b Port C Pins Alternate Functions

RESET - Port C, Bit 6

Overriding Signals for Alternate Functions in PC3. PC0(1)

Port D Pins Alternate Functions

The Port B Data Direction Register DDRB

The Port B Input Pins Address PINB

The Port C Data Register PORTC

The Port C Data Direction Register DDRC

The Port C Input Pins Address PINC

The Port D Data Register PORTD

The Port D Data Direction Register DDRD

The Port D Input Pins Address PIND

5.13 External Interrupts

Bit 7 - INTF1: External Interrupt Flag 1

8-bit Timer/Counter Register Description

Table 5.14 Clock Select Bit Description

Timer/Counter Interrupt Mask Register TIMSK

Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable

enabled. The corresponding Interrupt Vector (see Interrupts on page 46) is

Bit 4 - OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

Bit 7 - FOC2: Force Output Compare

The features of 16x2A LCD is as follows: 16 Characters x 2 Lines

Power supply (GND)

Power supply (+5V)

0 = Write to LCD module

I/O Data bus line 0 (LSB)

I/O Data bus line 1

I/O Data bus line 2

I/O Data bus line 3

I/O Data bus line 4