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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Analysis and Comparison in the Energy-Delay-Area
Domain of Nanometer CMOS Flip-Flops:
Part I—Methodology and Design Strategies
Massimo Alioto, Senior Member, IEEE, Elio Consoli, and Gaetano Palumbo, Fellow, IEEE
Abstract—In this paper (split into Parts I and II), an extensive
comparison of existing flip-flop (FF) classes and topologies is car-
ried out. In contrast to previous works, analysis explicitly accounts
for effects that arise in nanometer technologies and affect the en-
ergy-delay-area tradeoff (e.g., leakage and the impact of layout and
interconnects). Compared to previous papers on FFs comparison,
the analysis involves a significantly wider range of FF classes and
topologies. In particular, in this Part I, the comparison strategy,
which includes the simulation setup, the energy-delay estimation
methodology, and an overview of an optimum design strategy, to-
gether with the introduction of the analyzed FF classes and topolo-
gies, are reported.
Index Terms—Clocking, energy-delay tradeoff, energy effi-
ciency, flip-flops (FFs), high speed, interconnects, leakage, Logical
Effort, low power, nanometer technologies, VLSI.
I. INTRODUCTION
T HE appropriate choice of flip-flop (FF) topologies is of
fundamental importance in the design of VLSI integrated
circuits and, in particular, of both high-speed and low-energy
microprocessors [1]. Indeed, FFs affect the clock frequency,
since their delay occupies a significant fraction of the clock
cycle, especially in fast micro-architectures with low logic depth
[2]. Moreover, together with the circuits devoted to the clock
generation and distribution, FFs are part of the clock network,
which is responsible for 30%–50% of the whole chip energy
budget [3], [4].
Various classes of FFs have been proposed to achieve a de-
sired energy-delay tradeoff and depending on the fea-
tures of the application (high speed, low energy, low standby
energy, etc.). Understanding the suitability of FFs for a given
application is difficult and so is their selection, since it involves
a large number of existing topologies and depends on transis-
tors sizing. In particular, an appropriate sizing methodology is
necessary to get reliable results usable in practical designs.
Manuscript received September 10, 2009; revised December 21, 2009.
M. Alioto is with the Dipartimento di Ingegneria dell’Informazione (DII),
Università di Siena, 53100 Siena, Italy and also with the Berkeley Wireless
Research Center—Electrical Engineering and Computer Science Department,
University of California, Berkeley, CA 94704-1302 USA (e-mail: malioto@dii.
unisi.it; alioto@eecs.berkeley.edu)
E. Consoli and G. Palumbo are with the Dipartimento di Ingegneria Elettrica,
Elettronica e dei Sistemi (DIEES), Università di Catania, I-95125 Catania, Italy
(e-mail: econsoli@diees.unict.it; gpalumbo@diees.unict.it).
Digital Object Identifier 10.1109/TVLSI.2010.2041376
1063-8210/$26.00 © 2010 IEEE
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1
So far various analyses have been carried out, each focusing
on aspects pertinent with FFs comparison [1], [2], [4]–[11].
Among these works, [4]–[6] are the most thorough in terms of
adopted figures of merit and evaluated parameters. However,
previous comparisons exhibit (some of) the following lacks.
• They involve a limited number of topologies and/or do not
cover the entire spectrum of applications and con-
straints that are observed in real designs (therefore, no uni-
form comparison is available for the wide range of existing
FF classes).
• The area-delay and leakage-delay tradeoffs are usually not
considered at all.
• Circuit designers are typically accustomed to think in terms
of minimum energy-delay products or . Instead, a
fair comparison should take into account the FFs behavior
over the whole space [6], [12]–[14].
• The FF input capacitance is typically assumed fixed
or at most swept as a parameter in a narrow range, whose
extent is selected in a naïve manner. Hence, it is not clear
if the adopted ranges cover the regions of the
involved in real applications. Moreover, this naïve choice
does not permit to associate each value of
space
to a well-
defined point in the space.
• Till now, the most significant FF analyses in the litera-
ture have not adopted sub-100-nm technologies, thereby
neglecting:
• the leakage influence in active and in standby modes;
• the impact of layout parasitics associated with intercon-
nects, which degrade both speed and energy.
In this paper (split into Parts I and II), a novel analysis and
comparison strategy is proposed, which suitably accounts for all
the previously mentioned aspects to achieve fair and meaningful
results. Such strategy is applied to compare a large number of FF
classes (4) and topologies (19) in a 65-nm CMOS technology.
In particular, we show the following.
1) The comparison is carried out by including local wires par-
asitics within the transistors sizes optimization. To limit the
number of real layouts, wires parasitics are extracted from
some reference layouts and are estimated for different tran-
sistors sizes from the analysis of stick diagrams.
2) Leakage is separately evaluated and its impact is analyzed
in both active and standby mode.
3) The space is explored by considering the points
where products are minimized ( and are widely
varied to cover this space). Accordingly, every design is
associated with a point in the space that has a clear
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 1. Test bench circuit used to characterize a generic FF.
meaning, which links results to the hardware intensity con-
cept in [15]. This allows for gaining a deeper insight into
the tradeoff.
4) is a design variable allowing for further exploring the
potentials of each topology in the minimization of different
figures of merit, differently from [6], where separate en-
ergy-efficient curves (EECs) were extracted under very few
(three) different parametrical values.
5) In addition to the thorough investigation of the
tradeoff, the interdependence of several other circuit pa-
rameters is analyzed, including leakage, silicon area and
clock load. To this aim, appropriate figures of merit to rank
the considered FF classes and topologies are introduced.
This paper is divided into two parts: Part I presents the com-
parison methodology, the design strategies and the FF topolo-
gies to be analyzed, whereas the results are reported and com-
mented in detail in Part II [42].
Part I is structured as follows. In Section II the simulation
and analysis setup is shown. The space analysis and the
related topics are in Section III. The design-optimization strate-
gies for FFs are discussed in Section IV. Section V presents the
selected FF classes and topologies. Finally, Section VI reports a
brief conclusion. This paper also includes an Appendix related
with the accurate evaluation of the transient energy dissipation.
II. SIMULATION SETUP, ENERGY-DELAY ESTIMATION AND
ANALYSIS OF LAYOUT ISSUES
A. Test Bench: Driving Circuits and Output Load
Fig. 1 shows the setup used to test a generic FF, which is
similar to that proposed in [1], [2] but with some differences.
The clock signal fed to the FF comes from a two-stage buffer,
sized to attain a typical slope [1], [2] at the clock input
node of the FF ( is the slope of the output waveform of
an inverter loaded by inverters of the same size [16]). Hence,
the size of the clock-driving inverter close to the FF is
set to get an electrical effort equal to 3 [16]. When evaluating
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the FF input capacitance seen from the clock terminal, both the
transistors and local (i.e., internal to the FF) interconnects ca-
pacitances are taken into account.
As concerns the FF data input signal, we follow a different
approach with respect to [1], [2], where another constant slope
policy was adopted for simplicity. Indeed, in real pipelines, the
speed of the logic block driving the FF data input is obviously
comparable to the FF speed. Accordingly, the size of the data-
driving inverter close to the FF, , is set so that the slope of
the FF data input signal ( in Fig. 1) is equal to the slope at the
output of the FF first stage that is driven by . The latter slope
is estimated by resorting to the Logical Effort (LE) model [16].
Indeed, during the exploration of the design space, the sizes of
all FF transistors are known and LE model can be applied (also
including the layout parasitics).
In the case of circuits that are driven by complementary clock
(e.g., master-slave FFs) or data (e.g., differential FFs) signals,
both polarities are generated through buffers that are considered
as external to the FF, in order to avoid a penalty with respect
to other circuits [8]. Moreover, we assume that the comparison
of inverting and non-inverting FFs does not require further ar-
rangements and that neither of them is presumptively better than
the other ones [8].
Finally, the output load is swept to test the FF response under
light, moderate and heavy loading conditions [8]. Typical rea-
sonable loads are , being the input capac-
itance of a symmetrical minimum inverter (i.e., with
). Greater loads are not considered since, ac-
cording to LE, they usually require the insertion of a buffer at
the FF output, which alters the intrinsic energy-delay FF fea-
tures [8]. Observe that the first loading inverter in Fig. 1 that
loads the FF output is in turn loaded by another inverter, which
is 4 times wider to avoid an unrealistically strong Miller effect
in the gate-drain capacitances at the FF output.
B. Definition of Speed and Timing Parameters
The timing parameters characterizing a FF are well-known
and are accurately described in [2]. They are as follows:
1) the minimum data-to-output delay , which is ob-
tained by selecting the optimum data-to-clock delay;
2) the setup time , which is the optimum data-to-clock
delay that leads to ;
3) the minimum clock-to-output delay , occurring
when the data input transition occurs well before the clock
transition;
4) the hold time , which is the clock-to-data delay that
leads to a 5% increment of clock-to-output delay with
respect to .
In the analysis of the FF behavior within the space,
the speed is quantified through the minimum achievable
data-to-output delay, i.e., , according to [6]. In-
deed, represents the FF timing contribution to the cycle
time when the FF is placed into a critical path [5]. Moreover,
every delay is evaluated by considering the greatest among
all the possible data-to-output paths [namely two
for the single-edge-triggered (SET) FFs and four paths for the
dual-edge-triggered (DET) FFs]. On the other hand, FFs lying
in fast paths do not affect system speed. Anyhow, data races
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ALIOTO et al.: ANALYSIS AND COMPARISON IN THE ENERGY-DELAY-AREA DOMAIN OF NANOMETER CMOS FLIP-FLOPS
must be avoided and the race immunity
is the parameter that defines the FF sensitivity to races [2].
As regards and , FFs can be subdivided into the
following two main categories:
1) FFs where have positive (negative) values,
such as the master-slave FFs. They always have
and hence are not prone to data race problems, although
they do not allow time-borrowing because of their positive
[2], [5].
2) FFs where have negative (positive) values,
such as the Pulsed FFs. They are featured by an inherent
tradeoff related to the duration of their transparency
window. Indeed, by enlarging the width of the clock pulse,
their soft-clock-edge and time-borrowing properties are
improved thanks to an increasingly negative [5], but
their race immunity diminishes because increases
[2].
In the first case, and are inherently related to the
value. Hence, the only independent figure of merit con-
cerning FF timing is . In the second case, and
can be arranged regardless of the value. How-
ever, this tradeoff depends only on the specific requirements at
the micro-architectural level and can be freely regulated through
the pulse width. Hence, also in this case, the only real figure of
merit concerning FF timing is . Finally, the average FF energy dissipation in one clock cycle
C. Estimation of Energy Dissipation
The FF energy dissipation is made up of transient (i.e., dy-
namic and short-circuit) and static (i.e., leakage) contributions
[3].
Transient energy depends on the data input switching activity
[9], which is set to the typical values 0.10, 0.25, and 0.5. The
evaluation of transient dissipation has been discussed in detail
in [2]. However, we feel that some modifications are required
to more properly evaluate this contribution. Details about our
estimation methodology are reported in the Appendix, where the
average transient energy in a clock cycle is evaluated as
a function of . keepers (e.g., see the FF in [21]);
In deep submicrometer technologies, the impact of leakage
has to be considered not only in standby mode but also in active
mode, as it is a sizeable fraction of the chip consumption [18],
[19]. For this reason, it is separately evaluated from the transient
contribution, as discussed in the following. An average leakage
current, , is estimated by averaging out the 8 possible
values for the total FF leakage current according to the different
steady states of the FF terminals. The generic current is defined
where the subscripts and stand for the clock, data
and output static values (0 or 1). In order to correctly account
for the gate leakage, we also do the following:
• add the leakage contribution at the data and clock inputs
when they are at the high logical level (because this current
is drawn by the FF under analysis);
• subtract leakage currents that flow from the output when it
is logically high (because they are drawn by the load).
Thus, the average static dissipation in a clock cycle is
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3
(1)
from which it is apparent that the value of the clock period
has to be explicitly set to consistently add and compare
the leakage and the transient energy. Equivalently, the impact
of leakage in active mode depends on the choices made at the
micro-architectural level, which set for a given technology.
Actually, to express the impact of micro-architecture regardless
of the adopted technology, it is more convenient to refer to the
logic depth instead of the absolute clock cycle (i.e.,
the equivalent number of cascaded stages with optimum stage
effort equal to 4 [16]). Typical values of are respec-
tively equal to 10, 40, and 80 for high-performance, energy-ef-
ficient and low-energy microprocessors, respectively [14], [20].
To fairly compare DET and SET FFs, they are analyzed by
assuming the same throughput, i.e., by assuming that the clock
cycle of the former is half that of the latter ones (see also the
Appendix for details).
In regard to the temperature, the analyses are carried out by
setting the temperature to realistic values encountered in real ap-
plications (i.e., in the order of 70 C) instead of the room tem-
perature [17], [18]. This setting affects the speed of the circuits
and the strongly temperature-dependent leakage currents in a
realistic way.
, is the sum of and and thus depends on
the input data statistics and micro-architectural choices through
switching activity and logic depth .
D. Layout Issues: Local Wires Parasitics and Area Estimation
The extraction of the parasitic capacitances due to local inter-
connects is a task that must be necessarily accomplished when
analyzing nanometer circuits. This is especially true for FFs,
which have a more complex structure compared to combina-
tional logic gates. For example, we have the following:
• FFs are built with various cascaded logic stages and hence
long wires are needed to connect them to each other or to
• sometimes there are wires connecting the FF output with
the first stages (e.g., see the FF in [22]);
• the interconnects parasitics associated with the clock ter-
minal within FFs (especially the master-slave ones) tend
to be rather high (e.g., see the FFs in [10], [23]).
In principle, the FF layout should be redrawn for each set
of transistors sizes under evaluation, in order to include the FF
interconnects parasitics within the circuit design loop. Since a
large number of transistors sizings must be considered to reach
each optimal point in the space, this usually requires
the realization of hundreds of thousands layouts, which is obvi-
ously impracticable. Therefore, a strategy to estimate the inter-
connects parasitics as a function of the transistors sizes is essen-
tial. Obviously, these parasitics are purely capacitive (parasitic
resistive effects within a FF are clearly negligible, due to the
small dimension).
To estimate the interconnect capacitance, one needs to esti-
mate the wire length for each Poly, Metal1, and Metal2 line in
a reference layout. In this paper, we refer to standard cell lay-
outs [17], [18], which obviously must be as compact as possible
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
and where only Poly, Metal1, and Metal2 layers are employed
to connect transistors. In particular, the length of these inter-
connects depend on the relative position of the transistors along
their path, as well as the physical dimension of these transistors.
Stick diagrams are a useful tool to evaluate the relative posi-
tion [17], whereas the physical dimension of transistors can be
found from detailed layout consideration. From these consid-
erations, the adopted systematic methodology to extract inter-
connects parasitics is that reported in the Appendix A of [24].
Once the interconnect lengths are derived according to the above
methodology, the layout parasitics are found by multiplying the
lengths by the capacitances per unit length of the connecting
layers. Observe that the capacitances per unit length depend on
the detailed layout configuration, hence they must be properly
extracted from the design kit (see [24, App. A] for details).
The above procedure leads to the definition of expressions of
parasitics that depend on the sizes of the FF transistors. Hence it
can be automated in circuit simulations to include the effect of
interconnects when sizing transistors. The accuracy of the above
procedure has been validated through comparison with real lay-
outs of minimum- designs. On average, the parasitics are
underestimated by 10%–25% (for a detailed example, see Ap-
pendix A of [24]). The error in the delay and energy estimation is
actually lower (5%–10%), because each node capacitance also
includes the contribution of transistors.
The analysis of all topologies shows that layout parasitic ca-
pacitances are comparable to (or even greater than) the capaci-
tances of all transistors connected to the same node. From the LE
perspective, this means that the branching effort due to the pres-
ence of layout parasitics is typically 2 or more, thus confirming
that interconnects have a huge impact on the FF speed and en-
ergy. Compared with the case where such parasitics are not in-
cluded (as in previous works, [1]–[11]), the transistors sizes to
maintain a given speed strongly increase in high-speed designs
and the energy is nearly doubled.
To conclude, layout parasitics must be included in the tran-
sistor-level design loop to correctly characterize the
tradeoff of an FF, as well as to fairly compare different topolo-
gies. Moreover, observe that this procedure can predict the size
of the FF cell, other than the length of interconnects. Hence, it
is also a useful tool to estimate the FF area, thereby enabling a
thorough analysis of the energy-delay-area tradeoff for the first
time.
III. ENERGY-DELAY TRADEOFF
A. Energy-Delay Space Analysis
Since the last few years, digital VLSI circuits operate in a
power limited regime [25]. Hence, a deep understanding of the
tradeoff is crucial in both high-speed and low-energy
designs [12]–[14]. This justifies the adoption of composite met-
rics, such as the products or [26], [27], which can be
easily generalized to the class of figures of merit (FOMs).
Varying the exponents and , a wide range of different
tradeoffs can be explored.
FF topologies can be thoroughly and fairly compared by ex-
tracting the “energy-efficient curve” (EEC) in the space,
i.e., the set of design points showing minimum energy (delay)
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Fig. 2. Energy-Efficient curve and minimum E D design points.
for a given delay (energy). Given the circuit topology, load and
supply voltage, the EEC has a hyperbolic shape, as shown in
Fig. 2 [15]
(2)
where and are the energy and delay asymptotes of the cir-
cuit, and the parameter is determined by fitting experimental
data (typically ). Actually, there is a minimum energy
that is achievable with the minimum transistors sizes al-
lowing correct operation. Therefore, the points between and
must be discarded in the EEC (see Fig. 2). Regarding ,
it can be only asymptotically approached through transistors
sizing, and measures the speed potential of a specific topology.
can be estimated through methods that are focused on speed
optimization (e.g., the LE method [16]).
The resulting EEC is made up by the points minimizing the
products , with , as shown in Fig. 2. This result
was found in [15], [28] referring to the slightly different metrics
, where the parameter is called “hardware intensity”.
A fair comparison among FFs requires an exhaustive anal-
ysis across the entire space, i.e., the extraction of
the EEC under different loading, switching activity and logic
depth conditions. This task was somewhat accomplished in [6]
through extensive simulations, but with no reference to any
design metric. Instead, in the following, the relation between
the EEC and the metrics is exploited to efficiently extract
the EEC curve, as well as to give a clear physical meaning to
each point of the EEC.
B. Optimization Under a Varying Input Capacitance
Typically, previous FF comparisons considered a fixed input
size or, at most, a narrow set of values [1], [2], [4]–[11].
However, such a choice does not allow to extensively explore
the FF potentials in terms of both energy and delay. Indeed, a
considerable increment (reduction) of may bring a signifi-
cant speed improvement (energy savings). The same concept is
stated in [6], [12], [14] referring to generic circuits, but in those
papers is swept to a limited extent.
Here we suggest that, in the accomplishment of a fair design
strategy, (determined by the width of transistors in the
first stage of the path) should be adopted as an additional
design variable to be fully optimized, like the sizes of transistors
in the other stages within the FF. Hence, it is worth opportunely
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ALIOTO et al.: ANALYSIS AND COMPARISON IN THE ENERGY-DELAY-AREA DOMAIN OF NANOMETER CMOS FLIP-FLOPS
addressing the consequences of the optimization within a
wide range of exploration.
• If is increased with respect to medium values, it means
that the FF is being sized to achieve a high speed and
somewhat disregarding the energy consumption (which in-
creases since we include the energy to charge/discharge
; see the Appendix). Even if the FF imposes a signif-
icant load on the preceding logic stage in the pipeline, in
high-speed applications the speed penalty of the preceding
logic stages could be exceeded by the speed advantage that
the faster-FF brings at the beginning of the cycle time.
• If is strongly reduced, the FF is being sized for low-en-
ergy operation. Granted that the above mentioned tradeoff
is still valid, the low-energy applications typically have
high logic depths, and hence a slower FF can be tolerated
in favor of its smaller energy dissipation.
According to the above considerations, the adopted com-
parison strategy considers the input capacitance as a degree
of freedom. Given a value, from the LE point of view
this means that analysis is carried out by also optimizing the
electrical effort according to the desired tradeoff values
[8], as opposite to the usual analysis with fixed (non-optimal)
electrical effort.
IV. DESIGN AND OPTIMIZATION METHODOLOGIES
In this section, in order to provide a complete and in-depth
view of the issues involved in the FFs design, a brief overview
of the thorough design methodology, proposed by the authors
and described in detail in [24], is reported.
A. Transistor Sizing Strategy
Among all the transistors widths, only some of them can im-
prove the speed, i.e., those of the transistors along the critical
paths (i.e., the paths, as ), . These
transistors widths are hence design variables to be swept by the
optimization algorithm that extracts the EEC. To further reduce
the computational effort involved in the transistors sizes opti-
mization, let us introduce some reasonable simplifications. First,
series-connected transistors are equally sized, static gates are
symmetrically sized, whereas pull-up and pull-down networks
(lying in paths) of non-static gates are associated with dis-
tinct design variables. In the following, the widths of tran-
sistors along the paths are referred with their normalized
value, , with respect to the minimum width allowed by
the technology.
The sizes of the remaining transistors are not independent
variables, as they can be either set to a constant value (i.e., the
minimum value ensuring correct functionality), or are a func-
tion of the design variables (e.g., when their sizes set the
transparency window of pulsed FFs).
All the possible cases for such dependent variables are listed
in the following, and some are exemplified in Fig. 3 for the
semi-dynamic FF (SDFF) [29]. Normalized width/length (first/
second number) are shown next to each transistor.
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5
Fig. 3. Exemplification of transistors sizing (section of SDFF).
1) Clocked precharge transistors are sized to ensure a correct
precharge in half clock period.1 In general, a minimum size
is sufficient except when the clock frequency requirement
is very pressing or when the precharge is counteracted by a
non-gated keeper (in this case a width is sufficient).
2) Keepers inverting first stages (see Fig. 3) are minimum
sized. Keepers level-restoring second stages (see Fig. 3)
have always minimum widths. For non-gated keepers, their
length (normalized to the minimum value ) is set to
2 in order to weaken their driving strength.
3) Transistors involved in the clock gating logic and not be-
longing to paths are minimum sized.
4) Transistors placed in feedback paths (typically coming
from the output) that do not define the transparency
window (as in [23]) are minimum sized.
5) When sizing the pulse generators (delay paths) in explicit
(implicit) pulsed FFs [1], [2], the duration of the trans-
parency window is set equal to the whole delay.
This choice guarantees the FF functionality and links the
window duration to the speed of the FF for each specific
sizing. A detailed discussion on how to size each block of
Pulse Generators (e.g., those shown in Fig. 3) can be found
in [24] (see Section V and Appendix B).
The previous list covers all the cases encountered in this work
within the analysis and design of the considered FFs. Further
details and examples relative to the above sizing strategy can be
found in [24].
1A correct precharge means the reaching of 90% of the steady logic value
in half clock period. Hence, given: 1) the T =F O4 specification; 2) the ca-
pacitive load at the node to be precharged; and 3) the possible counteraction of
non-gated keepers, the required size of the precharged transistors is estimated
by resorting to LE model. Indeed, during the exploration of the design space,
the sizes of all FF transistors are known and LE can be applied (also including
the layout parasitics).
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

B. Definition of Design Space Bounds

As regards the widths to be swept within the optimization
procedure, realistic bounds for their ranges of variation need to
be identified to keep the computational effort within reasonable
limits. To this aim, we use the LE method since the LE sizing
leads to extreme high-speed designs (i.e., maximum possible
transistors sizes), as discussed in the following.
From the LE method, the optimized delay of a path of
cascaded gates (like a FF) is given by [16]

(3)

where and are the Logical Effort, the electrical effort

, the branching effort and the parasitic delay of
the entire path, respectively. Equivalently, one has
Fig. 4. LE-based procedure to identify a maximum C through opti-
(4) mized D to C sensitivity (SDFF example).

(5) • multiple reconvergent paths (which obviously must be

sized to exhibit the same delay).
where is the relative delay increment with respect to the ideal Nevertheless, the above arguments leading to (6) can be ex-
and practically inaccessible minimum path delay, i.e., the path ploited, given that, for high values, , and converge
parasitic delay . The sensitivity of the optimized path delay to somewhat constant values (i.e., the derivation of (6) from
to , from (3)–(5) is given by (4)–(5) is consistent in the high- region).
From a practical perspective, instead of directly applying
(6) (5)–(6), we apply an iterative procedure by increasing
until the condition (6) is satisfied with . For each
value, the LE method is employed, thus leading to the definition
From (6), we can evaluate the increment that leads to of the entire FF sizing (a set of nonlinear equations must be it-
the minimum acceptable sensitivity2 of the delay on , eratively solved). A fitted curve versus , upon which
and, in turn, from (5) we can evaluate the corresponding max- the sensitivity evaluation is carried out, is re-extrapolated for
imum input capacitance that keeps . each new value. When the sensitivity is equal to , the
Obviously, the upper bound of the input capacitance cycle stops, a practical maximum (i.e., ) is identified
corresponds to the upper bound of the size of the transis- and, correspondently, also the maximum values are found
tors in the first stage. The upper bounds of all other transistors (thanks to the LE method).
sizes ( , with ) can be found by considering that the As example, in Fig. 4 we report the results relative to the
LE design method permits to evaluate the transistor sizes that application of this procedure to SDFF, under a load. For
minimize the delay under a given and . Hence, since the instance, a sensitivity (i.e., we are significantly close
sizes found with LE method increase when increasing , to the FF parasitic delay) is reached for .
their upper bounds are found by optimizing the circuit with LE All the analyses in the paper are carried out by determining
for . the ranges of variation through a value, thus
Observe that, in practical cases, formulas (5)–(6) cannot be surely including the values that actually optimize the
applied straightforwardly because , and are not available FOMs considered in Section IV-C.
in a closed-form as a function of , which makes it impossible
to evaluate from (5). Indeed, , and can be found
only by numerically solving a set of nonlinear equations when C. Optimization in the Space
applying the LE method for a given [16]. This issue is well
known to arise in real circuits where the LE parameters of each Once the ranges of variation of the have been found, an
stage depend on both the transistors sizes of the stage optimization algorithm is applied to extract the optimum for
itself and of the other stages too, due to the presence of the each point of the EEC. As discussed in Section III-A, the EEC is
following: made up of the design points minimizing the FOMs, and
• keepers; hence the curve can be found by minimizing a discrete set of
• logic gates with fixed sizes outside the path under analysis these FOMs and interpolating them to extract the intermediate
(e.g., precharge transistors or PGs); points. We choose to consider the following ones, which cover
• interconnects capacitances (which depend on the ); a very wide range of applications
2Points in the EEC with very low sensitivity in (6) (say, a few percentage
points) are not of interest. Indeed, in this case the delay is almost insensitive to
an increase in C , and hence the FF becomes strongly energy inefficient. (7)

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ALIOTO et al.: ANALYSIS AND COMPARISON IN THE ENERGY-DELAY-AREA DOMAIN OF NANOMETER CMOS FLIP-FLOPS 7

deviation, maximum and minimum sensitivity for each point of

the EEC are reported in Table I. From Fig. 5 and Table I, it is ap-
parent that the dispersion of the simulated values is very small
and the resulting values agree very well with theoretical sensi-
tivity, thereby confirming the validity of the assumptions intro-
duced above (including the convexity of the functionals ).

V. ANALYZED FLIP-FLOP FAMILIES AND TOPOLOGIES

To cover the wide spectrum of adopted FF topologies, in our
analysis we consider the main four FF classes: master-slave
(MS), implicit-explicit pulsed (IP and EP), differential and DET
topologies. Nineteen FFs among the most representative and
best known ones are chosen for the four classes.
In particular, for the MS class we consider the following:
Fig. 5. Sensitivity analyses for the optimum designs. • Transmission Gate FF [10] (TGFF);
• Write-Port Master-Slave FF [30] (WPMS);
• Gated Master-Slave FF [10] (GMSL);
TABLE I
ANALYSIS OF THE SENSITIVITY S
• Data Transition Look-Ahead FF [31] (DTLA).
The latter two are also clock-gated structures.
The analyzed pulsed topologies are seven as follows:
• Hybrid Latch FF [32] (HLFF);
• Semi-Dynamic FF [29] (SDFF);
• UltraSPARC Semi-Dynamic FF [21] (USDFF);
• Implicitly Push-Pull FF [33] (IPPFF);
• Conditional Precharge FF [23] (CPFF);
• Static Explicit Pulsed FF [34] (SEPFF);
• Transmission Gate Pulsed Latch [35] (TGPL).
The first five are IP, whereas the remaining two are EP.
The identification of the optimum transistors sizes is carried out The four differential FFs investigated are as follows:
by resorting to a simple binary search algorithm, since the • Modified Sense-Amplifier FF [36] (MSAFF);
functionals are presumably convex (see later for details). • Skew-Tolerant FF [37] (STFF);
In order to reduce the computational effort, we restrict the • Conditional Capture FF [22] (CCFF);
search space by exploiting another property of the functionals • Variable Sampling Window FF [38] (VSWFF).
. Indeed, the optimum transistor sizes obtained when Finally, the four DET topologies are as follows:
minimizing are always greater than those minimizing • Transmission Gate Latch-Mux [39] (DET-TGLM);
, since the former gives more emphasis on the speed. • Symmetric Pulse Generator FF [40] (DET-SPGFF);
Therefore, starting from the extreme high-speed region (i.e., • Static Pulsed Latch [11] (DET-SPL);
), the ranges of for each FOM are progressively • Conditional Discharge FF [41] (DET-CDFF).
limited by those minimizing the previous one (i.e., the search The first is an MS, the second is IP and the other ones are EP.
space for each point of the EEC is progressively narrower). In Fig. 6(a)–(s) we report the schematics of each FF and the
Accordingly, each search relative to a specific metric has a location of the variable widths lying in the - paths and
number of iterations equal to , where that have to be optimized as explained in Section IV.
is the maximum optimum found by minimizing Note that, in the analysis of EP FFs, one PG for each latch is
the previous FOM ( stands for the closest integer considered. Obviously, this is a somewhat conservative choice
greater than a real number ). The EEC is finally extracted in the estimation of the energy consumption of such FFs, since,
through a hyperbolical fitting that interpolate the optimum by sharing the PG among a few different latches [11], [17], [35],
design points in the space, according to (2). the fraction of PG dissipation imputable to each latch slightly di-
We verified the consistency of the previous assumptions (e.g., minishes. This element must be taken into account when com-
convexity of the functionals) by comparing the energy-to-delay paring EP FFs with other topologies.
sensitivity in the minimum points with the theoretical In order to have an idea of the layout complexity and the re-
value, which is given by [15], [28] sulting impact of local wires, the layouts of the FFs are shown in
Fig. 7(a)–(s) for the minimum- sizings under typical values
(8) and .

The simulated and theoretical sensitivities are plotted in Fig. 5 VI. CONCLUSION
for all the optimum designs found within this work under var- In Part I, exhaustive analysis and design methodologies for
ious conditions and for all the considered FFs (see detailed re- nanometer CMOS FFs have been presented. Such methodolo-
sults in Part II). Detailed numerical values of the mean, standard gies are based on the notion of the Energy Efficient Curve and

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8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 6. Schematics of the analyzed FFs and variable widths (w ) to be optimized: (a) TGFF; (b) WPMS; (c) GMSL; (d) DTLA; (e) HLFF; (f) SDFF; (g) USDFF;
(h) IPPFF; (i) CPFF; (j) SEPFF; (k) TGPL; (l) MSAFF; (m) STFF; (n) CCFF; (o) VSWFF; (p) DET-TGLM; (q) DET-SPGFF; (r) DET-SPL; (s) DET-CDFF.

on the evaluation of its points that correspond to figures of merit meaning. Moreover, the FF input capacitance is considered as a
in the energy-delay space, which have a clear physical further independent variable to be optimized and the impact of

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ALIOTO et al.: ANALYSIS AND COMPARISON IN THE ENERGY-DELAY-AREA DOMAIN OF NANOMETER CMOS FLIP-FLOPS 9

Fig. 7. Layouts of the analyzed FFs (minimum ED sizing): (a) TGFF; (b) WPMS; (c) GMSL; (d) DTLA; (e) HLFF; (f) SDFF; (g) USDFF; (h) IPPFF; (i) CPFF;
(j) SEPFF; (k) TGPL; (l) MSAFF; (m) STFF; (n) CCFF; (o) VSWFF; (p) DET-TGLM; (q) DET-SPGFF; (r) DET-SPL; (s) DET-CDFF.

local wires parasitics is included in the transistor-level design APPENDIX

loop thanks to a stick-diagram based methodology, which is also
helpful to achieve good area estimations.
The FFs chosen for a thorough comparative analysis, whose
results are reported in Part II [42], cover the wide spectrum of
practically adopted solutions and have been here presented.
ACCURATE EVALUATION OF THE TRANSIENT
ENERGY CONSUMPTION
The proper evaluation of the energy dissipation related with
the input, internal and output nodes transitions is a somewhat

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10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

complicated task. In [2], [5] some significant guidelines were input signal (clock or data) that is varying and to the specific
outlined. For instance, the evaluation of the energy consump- transition or , the second subscript refers to the
tion must not include the energy dissipated in the charging/dis- value of the other stable input signal or and the third
charging of the external output load, since it is a value solely subscript is related with the output behavior, which can remain
depending on the load dimension and not on the FF features. stable or or can vary or . In the
However, one should not simply subtract the magnitude of following, with no loss of generality, we will refer to a non-in-
the current flowing from and towards the load, otherwise, the verting Positive SET FF. The first four contributions are those
effect of some undesired output transitions would not be taken related with the clock transitions when the input and output are
into account. To be more specific, some topologies (e.g., some stable
semi-dynamic FFs) can suffer from glitches both on the internal
and output nodes. In this case, the energy dissipation due to (A2)
output glitches must be included, since it is a shortcoming that (A3)
worsens the FF features right dependently on the load value. (A4)
The energy spent to charge the data and clock inputs has to
be included in the computation [2], [5], because it is a feature (A5)
dependent on the FF characteristics. The replicas of the data-
The second four contributions are related with the clock tran-
and clock-driving buffers are inserted in the simulation setup
sitions when the input and output are different. In the case of a
(see Fig. 1), to subtract the energy due to the parasitic load of
Positive SET FF, this does (not) lead to an output change for the
the same driving inverters [2], [5].
clock transition (the situation is reversed for a
Summarizing, defining , and as
Negative SET FF)
the currents drawn from the power supply by the FF, by the data-
and clock-driving inverters close to the FF and by their unloaded (A6)
replicas, the generic contribution to the transient energy (at the
(A7)
moment including the energy on the load) is
(A8)
(A1) (A9)

where the definition of the integration limits and has to
be properly done.
In [2], the authors deal with the energy breakdown by re-
ferring to four energy contributions: and
. They are evaluated by considering a single clock pe-
riod during which a single event on data occurs
. The authors state that it is possible to infer
clocking, precharge and internal nodes energy contributions by
simply combining the four terms according to transition proba-
bilities and subtracting the energy spent on load.
However, the simple approach shown in [2] does not allow to
accurately separate and localize the various sources of energy
consumption (clock, precharge, ), because the energy dissi-
pation related with the transition of one signal is influenced by
the values of the other signals. For instance, according to the FF
functionality, the transition of the data input can cause simply
the charging of the input gate capacitance or the transition of
internal nodes according to the state of the clock (e.g., in MS
circuits). If, after the transition, the data always remained stable
waiting for being transferred through the FF, the argument made
in [2] would be completely correct and exhaustive. But, actually,
the data can change during the opaque phase of the FF and one
needs to account for all the possible transition scenarios, in order
to have the most general information about the transient energy.
Moreover, the integration of the supply current over the entire
clock period includes the static energy due to leakage, whereas
it should be separately evaluated and weighted according to the
chosen logic depth . chitectural T =F O4 specification (as described in Section IV-A or [24]), the
For these reasons we suggest to consider all the possible tran-
sitions that arise according to all possible inputs combinations.
We adopt the following notation: the first subscript refers to the
Finally come the data input transitions, which can occur
during the high or low clock phase
(A10)
(A11)
(A12)
(A13)
These 12 contributions are evaluated by integrating the supply
current according to (A1), assuming to be the point of time
where the input experiences a transition, and to be the point
of time where the slowest node within the FF reaches 99% of
its steady value.3 In this way, the time window is suf-
ficiently wide to fully capture the dynamic and short-circuit en-
ergy contributions, whereas it is sufficiently narrow to neglect
the impact of leakage.
To determine the average transient energy in a clock cycle,
the switching activity needs to be used. If at most one data
transition occurs for each clock period (i.e., ), the av-
erage transient energy can be written as
3Sometimes, the nodes voltages can take long times to reach the 99% of the
steady value. Anyhow, when not employing simple pass-transistors that cause
a threshold drop and when all transistors are properly sized according to the ar-
99% value can be closely approached in practically acceptable times. Neverthe-
less, a good estimation of transient energy comes out also considering slightly
smaller values than 99% (e.g., 90%), and hence it is simply a matter of conven-
tion when characterizing an FF.

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ALIOTO et al.: ANALYSIS AND COMPARISON IN THE ENERGY-DELAY-AREA DOMAIN OF NANOMETER CMOS FLIP-FLOPS
(A14)
The quantity in (A14) is the energy required by
the load capacitance, and is hence subtracted because it depends
only on the adopted load (i.e., it is not a feature of the considered
FF).
Some further arrangements are required when dealing with
DET FFs. In this case (A6) and (A7) change into
(A15)
(A16)
because both the clock transitions enable the data-transfer
through the FF. To fairly compare SETs and DETs, the same
throughput must be assumed, which translates into an halved
clock frequency for DET with respect to SET. Therefore, in
order to consistently readjust the average transient energy
evaluation, one has to refer to the transitions occurring in a
half-cycle and hence (A14) is changed into
(A17)
It is worth noting that the proposed methodology also allows
for straightforwardly taking data glitches into account. This was
not possible in [2], since contributions in (A10)–(A13) were not
explicitly evaluated.
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(VLSI) Syst., accepted for publication.
Massimo Alioto (M’01–SM’07) was born in Brescia, Italy, in 1972. He received
the Laurea degree in electronics engineering and the Ph.D. degree in electrical
engineering from the University of Catania, Catania, Italy, in 1997 and 2001,
respectively.
In 2002, he joined the Dipartimento di Ingegneria dellInformazione (DII),
University of Siena, Siena, Italy, as a Research Associate and in the same year as
an Assistant Professor. In 2005, he was appointed Associate Professor of Elec-
tronics, and was engaged in the same faculty in 2006. In the summer of 2007,
he was a Visiting Professor at EPFL—Lausanne, Switzerland. In 2009-2010, he
is a Visiting Professor with BWRC, University of California at Berkeley, inves-
tigating on ultra-low power circuits and wireless sensor nodes. Since 2001, he
has been teaching undergraduate and graduate courses on advanced VLSI digital
design, microelectronics and basic electronics. He has authored or co-authored
more than 140 publications on journals (over 50, mostly IEEE Transactions)
and conference proceedings. Two of them are among the 25 most downloaded
TVLSI papers in 2007 (respectively, 10th and 13th). He is co-author of the book
Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and
SCL Digital Circuits (Springer, 2005). His primary research interests include the
modeling and the optimized design of CMOS high-performance, low-power and
ultra low-power digital circuits, arithmetic and cryptographic circuits, intercon-
nect modeling, design/modeling for variability-tolerant and low-leakage VLSI
circuits, circuit techniques for emerging technologies. He is the director of the
Electronics Lab at University of Siena (site of Arezzo).
Prof. Alioto is a member of the HiPEAC Network of Excellence. He is the
Chair Elect of the VLSI Systems and Applications Technical Committee of the
IEEE Circuits and Systems Society, for which he is also Distinguished Lecturer.
He is regularly invited to give talks and tutorials to academic institutions, confer-
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ences, and companies throughout the world. He has served as a member of var-
ious conference technical program committees (ISCAS, PATMOS, ICM, ICCD,
CSIE) and Track Chair (ICECS, ISCAS, ICM, ICCD). He serves as an Asso-
ciate Editor of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION
(VLSI) SYSTEMS, as well as of the Microelectronics Journal, the Integration
The VLSI Journal and the Journal of Circuits, Systems, and Computers. He is
Guest Editor of the Special Issue Advances in Oscillator Analysis and Design
of the Journal of Circuits, Systems, and Computers (2009).
Elio Consoli was born in Catania, Italy, in 1983. He received the Master’s de-
gree in microelectronic engineering from the University of Catania, Catania,
Italy, in 2008, where he is currently pursuing the Ph.D. degree in the Depart-
ment of Electrical, Electronic, and Systems Engineering (DIEES).
His primary research interests include clocking strategies and energy-efficient
design techniques for high-performance and low-power digital VLSI systems
in nanometer CMOS technologies. He is the co-author of scientific papers on
referred international Journals and Conferences.
Gaetano Palumbo (F’07) was born in Catania, Italy, in 1964. He received the
Laurea degree in electrical engineering and the Ph.D. degree from the University
of Catania, Catania, Italy, in 1988 and 1993, respectively.
Since 1993, he conducts courses on Electronic Devices, Electronics for Dig-
ital Systems, and Basic Electronics. In 1994, he joined the Dipartimento Elet-
trico Elettronico e Sistemistico (DEES), now Dipartimento di Ingegneria Elet-
trica Elettronica e dei Sistemi (DIEES), University of Catania, as a Researcher,
subsequently becoming an Associate Professor in 1998. Since 2000, he is a Full
Professor with the same department. His primary research interest has been
analog circuits with particular emphasis on feedback circuits, compensation
techniques, current-mode approach, low-voltage circuits. Then, his research has
also embraced digital circuits with emphasis on bipolar and MOS current-mode
digital circuits, adiabatic circuits, and high-performance building blocks fo-
cused on achieving optimum speed within the constraint of low power oper-
ation. In all these fields he is developing some the research activities in col-
laboration with STMicroelectronics of Catania. He was the co-author of three
books CMOS Current Amplifiers (Kluwer, 1999), Feedback Amplifiers: Theory
and Design (Kluwer, 2001), and Model and Design of Bipolar and MOS Cur-
rent-Mode Logic (CML, ECL and SCL Digital Circuits) (Kluwer, 2005) and a
textbook on electronic device in 2005. He is the author of 350 scientific papers
on referred international journals (over 150) and in conferences. Moreover he is
co-author of several patents.
Prof. Palumbo was a recipient of the Darlington Award in 2003. Since June
1999 to the end of 2001 and since 2004 to 2005, he served as an Associated Ed-
itor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: REGULAR
PAPERS for the topic analog circuits and filters and digital circuits and systems,
respectively. Since 2006 to 2007, he served as an Associated Editor of the IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: EXPRESS BRIEFS. Since
2008, he is serving as an Associated Editor of the IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS—PART I: REGULAR PAPERS. In 2005, he was one of
the 12 panelists in the scientific-disciplinare area 09-industrial and informa-
tion engineering of the Committee for Evaluation of Italian Research (CIVR),
which has the aim to evaluate the Italian research in the above area for the period
2001-2003.