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M4345 Service Manual Addemdum
M4345 Service Manual Addemdum
M4345 Service Manual Addemdum
Corrections or Additions
READY
DATA
READY | DATA
ATTENTION
READY | ATTENTION
DATA | ATTENTION
DATA | READY | ATTENTION
Serial
Description
Port
"A" Basic CPU initialization, TLB Pair 1 mapped for access to
Jedi/Unity internal blocks, Initial Stack setup in L2 Cache
configured as 32bit SRAM, The Uart and Compact or Nand Flas
interfaces have been initialized.
"B" Initial 8KB boot image has been moved from either CF or Nand
the L2 Cache still configured as 32bit SRAM.
"C" Second stage of the boot image has been DMA'd from either C
or Nand to the L2 cache configured as 32bit SRAM.
"D" Product ldr.ini (configuration) file is loaded from either CF or
Nand. Power-on bus clock frequencies are read from the PLLs.
Uart baud rate is adjusted to product specifications. NOTE: We
can shut down at this point if the ldr.ini file is corrupt!!!!
"E" Processor type is identified. Power-on cpu clock frequency is
read from the PLL. The formatter is identified. All DDR DIMMs
and onboard memory is discovered and mapped. A quick 1MB
DDR is tested with it's address as the data pattern. Dual Nand
chip are enabled. Compact Flash clock frequency is set to it's
most optimum value. Third stage of the boot image is now
DMA'd from either CF or NAND to DDR memory. NOTE: This is
another common hang point if DDR is not working correctly.
"F" Product NVRAM is initialized. Bootloader NVRAM is validated. P
values in NVRAM and ldr.ini are checked to see if we need to
adjust the PLL clock frequencies and reboot. All Unity based
products reboot to 133MHz from their strapped value of 131MH
"G" If no reboot, L1 and L2 caches are enabled, and the mmu is
enabled for virtual memory.
"H" Fourth stage of the boot image is DMA'd from CF or Nand Flash
This stage is compressed just like the OZ Image. Caches are
flushed and invalidated and we have a stable "C" environment
NOTE: This is another common hang point if the mmu isn't
operating correctly.