MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383 MARCH 2003

D
D
D
D
D
D
D
D
D
D

D Bootstrap Loader in Flash Devices

D Family Members Include:

Active Mode: 200 A at 1 MHz, 2.2 V

Standby Mode: 0.7 A
Off Mode (RAM Retention): 0.1 A
Five Power-Saving Modes
Wake-Up From Standby Mode in 6 s
Frequency-Locked Loop, FLL+
16-Bit RISC Architecture, 125-ns
Instruction Cycle Time
Scan I/F for Background Water, Heat, and
Gas Volume Measurement
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_A With Five
Capture/Compare Registers
Integrated LCD Driver for 96 Segments
On-Chip Comparator
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse

D
D

MSP430CW423:
8KB ROM,
512B RAM
MSP430CW425:
16KB ROM,
512B RAM
MSP430CW427:
32KB ROM,
1KB RAM
MSP430FW423:
8KB + 256B Flash Memory,
512B RAM
MSP430FW425:
16KB + 256B Flash Memory,
512B RAM
MSP430FW427:
32KB + 256B Flash Memory,
1KB RAM
Available in 64-Pin Quad Flat Pack (QFP)
For Complete Module Descriptions, Refer
to the MSP430x4xx Family Users Guide,
Literature Number SLAU056

description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6s.
The MSP430xW42x series are microcontroller configurations with two built-in 16-bit timers, a comparator, 96
LCD segment drive capability, a scan interface, and 48 I/O pins,
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process the data and transmit them to a host system. The comparator and timers make the configurations ideal
for gas, heat, and water meters, industrial meters, counter applications, handheld meters, etc.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA

40C to 85C

PLASTIC 64-PIN QFP

(PM)
MSP430CW423IPM
MSP430CW425IPM
MSP430CW427IPM
MSP430FW423IPM
MSP430FW425IPM
MSP430FW427IPM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001 2003, Texas Instruments Incorporated

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

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PRODUCT PREVIEW

D Low Supply-Voltage Range, 1.8 V . . . 3.6 V

D Ultralow-Power Consumption:

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

AVCC
DVSS
AVSS
P6.2/SIFCH2
P6.1/SIFCH1
P6.0/SIFCH0
RST/NMI
TCK
TMS
TDI
TDO/TDI
P1.0/TA00
P1.1/TA00/MCLK
P1.2/TA10
P1.3/TA01/SVSOut
P1.4/TA01

pin designation, MSP430xW42x

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48

47

46

45

44

43

42

MSP430xW42x

41

40

10

39

11

38

12

37

13

36

14

35

15

34

16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
P4.0/S9
P3.7/S10
P3.6/S11
P3.5/S12
P3.4/S13
P3.3/S14
P3.2/S15
P3.1/S16
P3.0/S17
P2.7/SIFCLKG/S18
P2.6/CAOUT/S19
P2.5/TACLK1/S20

PRODUCT PREVIEW

DVCC
P6.3/SIFCH3/SIFCAOUT
P6.4/SIFCI0
P6.5/SIFCI1
P6.6/SIFCI2/SIFDACOUT
P6.7/SIFCI3/SVSin
SIFCI
XIN
XOUT/TCLK
SIFVSS
SIFVCCEx
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4

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P1.5/TACLK0/ACLK
P1.6/CA0
P1.7/CA1
P2.0/TA20
P2.1/TA11
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P2.2/TA21/S23
P2.3/TA31/S22
P2.4/TA41/S21

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

functional block diagram

XIN

XOUT/
TCLK

DVCC

DVSS

RST/NMI

AVCC AVSS

Oscillator
ACLK

FLL+

8KB
16KB
32KB

512B
512B
1024B

Reset/SVS/

Flash/ROM

RAM

Brownout

Incl. 16 Reg.

P2

Port P1/P2
2x8 I/Os, all
Interr. Cap.
2 Vectors

ACLK
MCLK
SMCLK

Test
JTAG

4x8 I/Os

MCLK

CPU

Port P3/P4
Port P5/P6

Power- On

SMCLK

System Clock

P1

P3 P4 P5 P6

MAB,4 bit

MAB, 16 bit

Emu
lation
Module

Bus
Conv

MDB, 16 bit

MDB,8 bit

4
COM03
Timer_A0

Timer_A1

Scan I/F

TCK

Timer

3 CC
Registers

5 CC
Registers

Up to 4
sensors

TDI
TDO/TDI

ACLK
SMCLK

Comparator

15/16 Bit

Basic
Timer1
1 Interrupt
Vector

LCD

S015

96 Segments
1,2,3,4 MUX

CA0 CA1 CAOUT

R03

R23

R13

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S1619,
P2.7P2.6
S2023,
P2.5P2.2

f LCD
TACLK0 TA0.02 TACLK1 TA1.04

PRODUCT PREVIEW

Watchdog

TMS

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R33

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

Terminal Functions
MSP430xW42x
TERMINAL

PRODUCT PREVIEW

NAME

NO.

DESCRIPTION

I/O

AVCC

64

Positive terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A, port 6, and LCD
resistive divider circuitry; must not power up prior to DVCC.

AVSS

62

Negative terminal that supplies SVS, brownout, oscillator, FLL+, comparator_A. and port 6. Must be
externally connected to DVSS. Internally connected to DVSS.

DVCC

Digital supply voltage, positive terminal. Supplies all parts, except those which are supplied via AVCC.

DVSS

63

Digital supply voltage, negative terminal. Supplies all digital parts, except those which are supplied via
AVCC/AVSS.

SIFVSS
P1.0/TA00

10
53

I/O

General-purpose digital I/O/Timer_A0. Capture: CCI0A input, compare: Out0 output

P1.1/TA00/MCLK

52

I/O

General-purpose digital I/O/Timer_A0. Capture: CCI0B input/MCLK output. Note: TA00 is only an input
on this pin.

P1.2/TA10

51

I/O

General-purpose digital I/O/Timer_A0, capture: CCI1A input, compare: Out1 output

P1.3/TA01/SVSOut

50

I/O

General-purpose digital I/O/Timer_A1, capture: CCI0B input/SVS: output of SVS comparator. Note:
TA01 is only an input on this pin.

P1.4/TA01

49

I/O

General-purpose digital I/O/Timer_A1, capture: CCI0A input, compare: Out0 output

P1.5/TACLK0/
ACLK

48

I/O

General-purpose digital I/O/input of Timer_A clock/output of ACLK

P1.6/CA0

47

I/O

General-purpose digital I/O/Comparator_A input

P1.7/CA1

46

I/O

General-purpose digital I/O/Comparator_A input

P2.0/TA20

45

I/O

General-purpose digital I/O/Timer_A0, capture: CCI2A input, compare: Out2 output

P2.1/TA11

44

I/O

General-purpose digital I/O/Timer_A1, capture: CCI1A input, compare: Out1 output

P2.2/TA21/S23

35

I/O

General-purpose digital I/O/Timer_A1, capture: CCI2A input, compare: Out2 output/LCD segment
output 23 (see Note 1)

P2.3/TA31/S22

34

I/O

General-purpose digital I/O/Timer_A1, capture: CCI3A input, compare: Out3 output/LCD segment
output 22 (see Note 1)

P2.4/TA41/S21

33

I/O

General-purpose digital I/O/Timer_A1, capture: CCI4A input, compare: Out4 output/LCD segment
output 21 (see Note 1)

P2.5/TACLK1/S20

32

I/O

General-purpose digital I/O/input of Timer_A1 clock/LCD segment output 20 (see Note 1)

P2.6/CAOUT/S19

31

I/O

General-purpose digital I/O/Comparator_A output/LCD segment output 19 (see Note 1)

P2.7/SIFCLKG/
S18

30

I/O

General-purpose digital I/O/Scan I/F, signal SIFCLKG from internal clock generator/LCD segment
output 18 (see Note 1)

P3.0/S17

29

I/O

General-purpose digital I/O/ LCD segment output 17 (see Note 1)

P3.1/S16

28

I/O

General-purpose digital I/O/ LCD segment output 16 (see Note 1)

P3.2/S15

27

I/O

General-purpose digital I/O/ LCD segment output 15 (see Note 1)

P3.3/S14

26

I/O

General-purpose digital I/O/ LCD segment output 14 (see Note 1)

P3.4/S13

25

I/O

General-purpose digital I/O/LCD segment output 13 (see Note 1)

P3.5/S12

24

I/O

General-purpose digital I/O/LCD segment output 12 (see Note 1)

P3.6/S11

23

I/O

General-purpose digital I/O/LCD segment output 11 (see Note 1)

P3.7/S10

22

I/O

General-purpose digital I/O/LCD segment output 10 (see Note 1)

Scan I/F ground potential. Must be externally connected to DVSS.

NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

Terminal Functions (Continued)

MSP430xW42x
NAME

NO.

DESCRIPTION

I/O

P4.0/S9

21

I/O

General-purpose digital I/O/LCD segment output 9 (see Note 1)

P4.1/S8

20

I/O

General-purpose digital I/O/LCD segment output 8 (see Note 1)

P4.2/S7

19

I/O

General-purpose digital I/O/LCD segment output 7 (see Note 1)

P4.3/S6

18

I/O

General-purpose digital I/O/LCD segment output 6 (see Note 1)

P4.4/S5

17

I/O

General-purpose digital I/O/LCD segment output 5 (see Note 1)

P4.5/S4

16

I/O

General-purpose digital I/O/LCD segment output 4 (see Note 1)

P4.6/S3

15

I/O

General-purpose digital I/O/LCD segment output 3 (see Note 1)

P4.7/S2

14

I/O

General-purpose digital I/O/LCD segment output 2 (see Note 1)

P5.0/S1

13

I/O

General-purpose digital I/O/LCD segment output 1 (see Note 1)

P5.1/S0

12

I/O

General-purpose digital I/O/LCD segment output 0 (see Note 1)

COM0

36

Common output. COM03 are used for LCD backplanes

P5.2/COM1

37

I/O

General-purpose digital I/O/common output. COM03 are used for LCD backplanes

P5.3/COM2

38

I/O

General-purpose digital I/O/common output. COM03 are used for LCD backplanes

P5.4/COM3

39

I/O

General-purpose digital I/O/common output. COM03 are used for LCD backplanes

R03

40

P5.5/R13

41

I/O

General-purpose digital I/O/input port of third most positive analog LCD level (V4 or V3)

P5.6/R23

42

I/O

General-purpose digital I/O/input port of second most positive analog LCD level (V2)

P5.7/R33

43

I/O

General-purpose digital I/O/output port of most positive analog LCD level (V1)

P6.0/SIFCH0

59

I/O

General-purpose digital I/O/Scan I/F, channel 0 sensor excitation ouput and signal input

P6.1/SIFCH1

60

I/O

General-purpose digital I/O/Scan I/F, channel 1 sensor excitation ouput and signal input

P6.2/SIFCH2

61

I/O

General-purpose digital I/O/Scan I/F, channel 2 sensor excitation output and signal input

P6.3/SIFCH3/
SIFCAOUT

I/O

General-purpose digital I/O/Scan I/F, channel 3 sensor excitation output and signal input, Scan I/F
comparator output

P6.4/SIFCI0

I/O

General-purpose digital I/O/Scan I/F, channel 0 signal input to comparator

P6.5/SIFCI1

I/O

General-purpose digital I/O/Scan I/F, channel 1 signal input to comparator

P6.6/SIFCI2/
SIFDACOUT

I/O

General-purpose digital I/O/Scan I/F, channel 2 signal input to comparator, 10-bit DAC output

P6.7/
SIFCI3/SVSin

I/O

General-purpose digital I/O/Scan I/F, channel 3 signal input to comparator/SVS, analog input

PRODUCT PREVIEW

TERMINAL

Input port of fourth positive (lowest) analog LCD level (V5)

SIFCI

Scan I/F, input to Scan I/F Comparator

SIFVCCEx

11

Scan I/F, output of excitation signal with resistive bridge sensors, or output of of AVCC/2.

RST/NMI

58

Reset input or nonmaskable interrupt input port

TCK

57

Test clock. TCK is the clock input port for device programming and test.

TDI

55

Test data input. TDI is used as a data input port. The device protection fuse is connected to TDI.

TDO/TDI

54

I/O

TMS

56

Test mode select. TMS is used as an input port for device programming and test

XIN

Input port for crystal oscillator XT1. Standard or watch crystals can be connected.

XOUT/TCLK

I/O

Test data output port. TDO/TDI data output or programming data input terminal

Output terminal of crystal oscillator XT1 or test clock input

NOTE 1: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in conjunction with seven addressing modes for source
operand and four addressing modes for destination operand.

PC/R0

Stack Pointer

SP/R1
SR/CG1/R2

Status Register
Constant Generator

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The remaining registers are general-purpose registers.

PRODUCT PREVIEW

Program Counter

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.

CG2/R3

General-Purpose Register

R4

General-Purpose Register

R5

General-Purpose Register

R6

General-Purpose Register

R7

General-Purpose Register

R8

General-Purpose Register

R9

General-Purpose Register

R10

General-Purpose Register

R11

General-Purpose Register

R12

General-Purpose Register

R13

General-Purpose Register

R14

General-Purpose Register

R15

Table 1. Instruction Word Formats

Dual operands, source-destination

e.g. ADD R4,R5

R4 + R5 > R5

Single operands, destination only

e.g. CALL

PC >(TOS), R8> PC

Relative jump, un/conditional

e.g. JNE

R8

Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE

S D

Register

n n

MOV Rs,Rd

MOV R10,R11

Indexed

n n

MOV X(Rn),Y(Rm)

MOV 2(R5),6(R6)

Symbolic (PC relative)

n n

MOV EDE,TONI

M(EDE) > M(TONI)

n n

MOV and MEM,and

TCDAT

M(MEM) > M(TCDAT)

Absolute

EXAMPLE

OPERATION
R10

> R11

M(2+R5)> M(6+R6)

Indirect

MOV @Rn,Y(Rm)

MOV @R10,Tab(R6)

M(R10) > M(Tab+R6)

Indirect
autoincrement

MOV @Rn+,Rm

MOV @R10+,R11

M(R10) > R11

R10 + 2> R10

Immediate

MOV #X,TONI

MOV #45,TONI

NOTE: S = source

SYNTAX

D = destination

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#45

> M(TONI)

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:

D Active mode AM;

All clocks are active

D Low-power mode 0 (LPM0);

CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
FLL+ Loop control remains active

D Low-power mode 1 (LPM1);

CPU is disabled
FLL+ Loop control is disabled
ACLK and SMCLK remain active. MCLK is disabled

PRODUCT PREVIEW

D Low-power mode 2 (LPM2);

CPU is disabled
MCLK and FLL+ loop control and DCOCLK are disabled
DCOs dc-generator remains enabled
ACLK remains active

D Low-power mode 3 (LPM3);

CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCOs dc-generator is disabled
ACLK remains active

D Low-power mode 4 (LPM4);

CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCOs dc-generator is disabled
Crystal oscillator is stopped

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

interrupt vector addresses

PRODUCT PREVIEW

The interrupt vectors and the power-up starting address are located in the ROM with an address range
0FFFFh 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence.
INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up
External Reset
Watchdog
Flash memory

WDTIFG
KEYV
(see Note 1)

Reset

0FFFEh

15, highest

NMI
Oscillator Fault
Flash memory access violation

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)

(Non)maskable
(Non)maskable
(Non)maskable

0FFFCh

14

Timer_A5

TACCR01 CCIFG (see Note 2)

Maskable

0FFFAh

13

Timer_A5

TACCR11 to TACCR41
CCIFGs
TACTL1 TAIFG

Maskable

0FFF8h

12

Comparator_A

CMPAIFG

Maskable

0FFF6h

11

Watchdog Timer

WDTIFG

Maskable

0FFF4h

10

Scan I/F

SIFIFG0 to SIFIFG6
(See Note 1)

Maskable

0FFF2h

0FFF0h

0FFEEh

Timer_A3

TACCR00 CCIFG (see Note 2)

Maskable

0FFECh

Timer_A3

TACCR10 and TACCR20

CCIFGs, and TACTL0 TAIFG
(see Notes 1 and 2)

Maskable

0FFEAh

I/O port P1 (eight flags)

P1IFG.0 (see Notes 1 and 2)

To
P1IFG.7 (see Notes 1 and 2)

Maskable

0FFE8h

0FFE6h

0FFE4h

I/O port P2 (eight flags)

P2IFG.0 (see Notes 1 and 2)

To
P2IFG.7 (see Notes 1 and 2)

Maskable

0FFE2h

Basic Timer1

BTIFG

Maskable

0FFE0h

0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.

interrupt enable 1 and 2

7

Address

0h

ACCVIE

NMIIE

rw-0
7

Address
1h

rw-0
5

OFIE

WDTIE

rw-0
4

rw-0
1

BTIE

WDTIE:

Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is
configured in interval timer mode.

OFIE:

Oscillator-fault-interrupt enable

NMIIE:

Nonmaskable-interrupt enable

ACCVIE:

Flash access violation interrupt enable

BTIE:

Basic Timer1 interrupt enable

PRODUCT PREVIEW

rw-0

interrupt flag register 1 and 2

7

Address

02h

NMIIFG
rw-0
7

Address
3h

OFIFG

WDTIFG

rw-1
4

rw-0
1

BTIFG
rw-0

WDTIFG:

Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with VCC power-up,
or a reset condition at the RST/NMI pin in reset mode.

OFIFG:

Flag set on oscillator fault

NMIIFG:

Set via RST/NMI pin

BTIFG:

Basic Timer1 interrupt flag

module enable registers 1 and 2

Address

04h/05h
Legend: rw:
rw-0:

Bit Can Be Read and Written

Bit Can Be Read and Written. It Is Reset by PUC.
SFR Bit Not Present in Device

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

memory organization

Memory
Interrupt vector
Code memory

Size
Flash/ROM
Flash/ROM

MSP430CW423
MSP430FW423

MSP430CW425
MSP430FW425

MSP430CW427
MSP430FW427

8KB
0FFFFh 0FFE0h
0FFFFh 0E000h

16KB
0FFFFh 0FFE0h
0FFFFh 0C000h

32KB
0FFFFh 0FFE0h
0FFFFh 08000h

Information memory

Size

256 Byte (F device only)

010FFh 01000h

256 Byte (F device only)

010FFh 01000h

256 Byte (F device only)

010FFh 01000h

Boot memory

Size

1kB (F device only)

0FFFh 0C00h

1kB (F device only)

0FFFh 0C00h

1kB (F device only)

0FFFh 0C00h

Size

512 Byte
03FFh 0200h

512 Byte
03FFh 0200h

1KB
05FFh 0200h

16-bit
8-bit
8-bit SFR

01FFh 0100h
0FFh 010h
0Fh 00h

01FFh 0100h
0FFh 010h
0Fh 00h

01FFh 0100h
0FFh 010h
0Fh 00h

RAM
Peripherals

PRODUCT PREVIEW

bootstrap loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.

flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0n.
Segments A and B are also called information memory.

D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.

10

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

flash memory (continued)

8KB

16KB

0FFFFh 0FFFFh

32KB
0FFFFh

0FE00h 0FE00h 0FE00h

0FDFFh 0FDFFh 0FDFFh

Segment 0
With Interrupt Vectors
Segment 1

0FC00h 0FC00h 0FC00h

0FBFFh 0FBFFh 0FBFFh
Segment 2
0FA00h
0F9FFh

0FA00h
0F9FFh

0FA00h
0F9FFh

0E400h 0C400h
0E3FFh 0C3FFh

083FFh

0E200h 0C200h
0E1FFh 0C1FFh

08200h
081FFh

0E000h
010FFh

0C000h
010FFh

08000h
010FFh

01080h
0107Fh

01080h
0107Fh

01080h
0107Fh

08400h
Segment n1

Segment n

Segment A
Information Memory
Segment B
01000h

01000h

01000h

peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions.

oscillator and system clock

The clock system in the MSP430xW42x family of devices is supported by the FLL+ module that includes support
for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The FLL+ module
provides the following clock signals:

D
D
D
D

Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.

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11

PRODUCT PREVIEW

Main Memory

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).

digital I/O
There are six 8-bit I/O ports implementedports P1 through P6:

PRODUCT PREVIEW

D
D
D
D

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.

Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.

LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.

watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections

CCR0

CCR1

CCR2

Input Name

TACLK0

TACLK

ACLK

ACLK

SMCLK

SMCLK

TACLK0

INCLK

TA00

CCI0A

TA00

CCI0B

DVss

GND

DVCC
TA10

VCC
CCI1A

CAOUT (Internal)

CCI1B

DVss

GND

DVCC
TA20

VCC
CCI2A

ACLK (internal)

CCI2B

DVss

GND

DVCC

VCC

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Output
Signal

NA

TA00

PRODUCT PREVIEW

Input
Divider

Input Signal

TA10

TA20

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13

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

timer_A5
Timer_A5 is a 16-bit timer/counter with five capture/compare registers. Timer_A5 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A5 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A5 Signal Connections

Input
Divider

PRODUCT PREVIEW

CCR0

CCR1

CCR2

CCR3

CCR4

Input Signal

Input Name

TACLK1

TACLK

ACLK

ACLK

SMCLK

SMCLK

TACLK1

INCLK

TA01

CCI0A

TA01

CCI0B

DVss

GND

DVCC
TA11

VCC
CCI1A

CAOUT (Internal)

CCI1B

DVss

GND

DVCC
TA21

VCC
CCI2A

SIFO0sig (internal)

CCI2B

DVss

GND

DVCC
TA31

VCC
CCI3A

SIFO1sig (internal)

CCI3B

DVss

GND

DVCC
TA41

VCC
CCI4A

SIFO2sig (internal)

CCI4B

DVss

GND

DVCC

VCC

Output
Signal

NA

TA01

TA11

TA21

TA31

TA41

comparator_A
The primary function of the comparator_A module is to support precision slope analogtodigital conversions,
batteryvoltage supervision, and monitoring of external analog signals.

scan I/F
The scan interface is used to detect rotation and direction and supports LC sensors and resistive-bridge
sensors. The scan I/F incorporates a VCC/2 generator, a comparator, and a 10-bit DAC and supports up to four
sensors.

14

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

peripheral file map

PERIPHERALS WITH WORD ACCESS
Watchdog

Watchdog Timer control

WDTCTL

0120h

Timer_A5

Timer_A interrupt vector

TAIV1

011Eh

Timer_A control

TACTL1

0180h

Capture/compare control 0

TACCTL01

0182h

Capture/compare control 1

TACCTL11

0184h

Capture/compare control 2

TACCTL21

0186h

Capture/compare control 3

TACCTL31

0188h

Capture/compare control 4

TACCTL41

018Ah

Reserved

018Ch
018Eh

Timer_A register

TAR0

0190h

Capture/compare register 0

TACCR01

0192h

Capture/compare register 1

TACCR11

0194h

Capture/compare register 2

TACCR21

0196h

Capture/compare register 3

TACCR31

0198h

Capture/compare register 4

TACCR41

019Ah

Reserved

019Ch

Reserved
Timer_A3

019Eh

Timer_A interrupt vector

TAIV0

012Eh

Timer_A control

TACTL0

0160h

Capture/compare control 0

TACCTL00

0162h

Capture/compare control 1

TACCTL10

0164h

Capture/compare control 2

TACCTL20

0166h

Reserved

0168h

Reserved

016Ah

Reserved

016Ch

Reserved

016Eh

Timer_A register

TAR0

0170h

Capture/compare register 0

TACCR00

0172h

Capture/compare register 1

TACCR10

0174h

Capture/compare register 2

TACCR20

0176h

Reserved

0178h

Reserved

017Ah

Reserved

017Ch

Reserved
Flash

017Eh

Flash control 3

FCTL3

012Ch

Flash control 2

FCTL2

012Ah

Flash control 1

FCTL1

0128h

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Reserved

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

PERIPHERALS WITH WORD ACCESS (CONTINUED)

Scan I/F

SIF timing state machine 23

SIFTSM23

01EEh

SIF timing state machine 0

SIFTSM0

01C0h

SIF control register 5

SIFCTL5

01BEh

SIF control register 4

SIFCTL4

01BCh

SIF control register 3

SIFCTL3

01BAh

SIF control register 2

SIFCTL2

01B8h

SIF control register 1

SIFCTL1

01B6h

SIF processing state machine

SIFTPSMV

01B4h

SIF counter CNT1/2

SIFCNT

01B2h

LCD memory 20

LCDM20

0A4h

LCD memory 16

LCDM16

0A0h

LCD memory 15

LCDM15

09Fh

LCD memory 1

LCDM1

091h

LCD control and mode

LCDCTL

090h

Comparator_A port disable

CAPD

05Bh

Comparator_A control2

CACTL2

05Ah

Comparator_A control1

CACTL1

059h

Brownout, SVS

SVS control register

SVSCTL

056h

FLL+ Clock

FLL+ Control1

FLL_CTL1

054h

FLL+ Control0

FLL_CTL0

053h

System clock frequency control

SCFQCTL

052h

System clock frequency integrator

SCFI1

051h

System clock frequency integrator

SCFI0

050h

BT counter2

BTCNT2

047h

BT counter1

BTCNT1

046h

BT control

BTCTL

040h

PERIPHERALS WITH BYTE ACCESS

PRODUCT PREVIEW

LCD

Comparator_A

Basic Timer1

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

peripheral file map (continued)

Port P5

Port P4

Port P3

Port P2

Port P1

Special Functions

Port P6 selection

P6SEL

037h

Port P6 direction

P6DIR

036h

Port P6 output

P6OUT

035h

Port P6 input

P6IN

034h

Port P5 selection

P5SEL

033h

Port P5 direction

P5DIR

032h

Port P5 output

P5OUT

031h

Port P5 input

P5IN

030h

Port P4 selection

P4SEL

01Fh

Port P4 direction

P4DIR

01Eh

Port P4 output

P4OUT

01Dh

Port P4 input

P4IN

01Ch

Port P3 selection

P3SEL

01Bh

Port P3 direction

P3DIR

01Ah

Port P3 output

P3OUT

019h

Port P3 input

P3IN

018h

Port P2 selection

P2SEL

02Eh

Port P2 interrupt enable

P2IE

02Dh

Port P2 interrupt-edge select

P2IES

02Ch

Port P2 interrupt flag

P2IFG

02Bh

Port P2 direction

P2DIR

02Ah

Port P2 output

P2OUT

029h

Port P2 input

P2IN

028h

Port P1 selection

P1SEL

026h

Port P1 interrupt enable

P1IE

025h

Port P1 interrupt-edge select

P1IES

024h

Port P1 interrupt flag

P1IFG

023h

Port P1 direction

P1DIR

022h

Port P1 output

P1OUT

021h

Port P1 input

P1IN

020h

SFR module enable 2

ME2

005h

SFR module enable 1

ME1

004h

SFR interrupt flag2

IFG2

003h

SFR interrupt flag1

IFG1

002h

SFR interrupt enable2

IE2

001h

SFR interrupt enable1

IE1

000h

PRODUCT PREVIEW

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Port P6

absolute maximum ratings

Voltage applied at VCC to VSS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to + 4.1 V
Voltage applied to any pin (referenced to VSS) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 150C
Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 85C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages referenced to VSS.

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

recommended operating conditions

PARAMETER

MIN

MAX

UNITS

Supply voltage during program execution, SVS disabled

VCC (AVCC = DVCC = VCC)

MSP430xW42x

1.8

3.6

Supply voltage during program execution, SVS enabled (see Note 1),
VCC (AVCC = DVCC = VCC)

MSP430xW42x

2.2

3.6

Supply voltage during programming flash memory,

VCC (AVCC = DVCC = VCC)

MSP430FW42x

2.7

3.6

MSP430xW42x

40

85

Supply voltage, VSS (AVSS = DVSS = VSS)

Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 2)

LF selected, XTS_FLL=0

Watch crystal

32768

XT1 selected, XTS_FLL=1

Ceramic resonator

XT1 selected, XTS_FLL=1

Crystal

Hz

450

8000

kHz

1000

8000

kHz

DC

4.15

Processor frequency (signal MCLK), f(System)

VCC = 1.8 V
VCC = 3.6 V

DC

Flash-timing-generator frequency, f(FTG)

MSP430FW42x

257

476

kHz

Cumulative program time, t(CPT) (see Note 3)

VCC = 2.7 V/3.6 V

MSP430FW42x

ms

Cumulative mass erase time, t(CMEras) (see Note 4)

VCC = 2.7 V/3.6 V

MSP430FW42x

VIL(Xin, Xout)
VIH(Xin, Xout)

NOTES: 1.
2.
3.
4.

VCC = 2.2 V/3 V

XTS_FLL=1

f (MHz)

Supply Voltage Range

During Programming of
the Flash Memory

8 MHz

Supply Voltage Range, xW42x

During Program Execution

4.15 MHz

1.8 V

2.7 V

3V

3.6 V

VCC Supply Voltage V

Figure 1. Frequency vs Supply Voltage

18

200

MHz

ms

VSS
0.2VCC
V
0.8VCC
VCC
The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage.
POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.
The LFXT1 oscillator in LF-mode requires a watch crystal.
The cumulative program time must not be exceeded during a block-write operation.
The mass-erase duration generated by the flash timing generator is at least 11.1 ms. The cummulative mass-erase time needed
is 200 ms. This can be achieved by repeating the mass-erase operation until the cumulative mass-erase time is met (a minimum
of 19 cycles may be required).

Input levels at Xin and Xout

f(System) Maximum Processor Frequency MHz

PRODUCT PREVIEW

NOM

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted)
supply current into AVCC + DVCC excluding external current, (see Note 1)
TEST CONDITIONS

Active mode,
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz, XTS_FLL = 0
(FW42x: Program executes in flash)

I(AM)

NOM

MAX

CW42x TA = 40C
to 85C

VCC = 2.2 V
VCC = 3 V

160

200

240

300

FW42x TA = 40C
to 85C

VCC = 2.2 V
VCC = 3 V

200

250

300

350

32

45

55

70

11

14

17

22

0.95

1.4

0.8

1.3

I(LPM0)

Low-power mode, (LPM0)

FN_8=FN_4=FN_3=FN_2=0

TA = 40C
to 85C

VCC = 2.2 V
VCC = 3 V

I(LPM2)

Low-power mode, (LPM2),

to 85C

TA = 40C

VCC = 2.2 V
VCC = 3 V

TA = 40C
TA = 10C
TA = 25C
TA = 60C
I(LPM3)

Low-power mode, (LPM3) (see Note 2)

0.7

1.2

0.95

1.4

TA = 85C
TA = 40C

1.6

2.3

1.1

1.7

TA = 10C
TA = 25C

1.0

1.6

0.9

1.5

1.1

1.7

2.0

2.6

0.1

0.5

0.1

0.5

VCC = 2.2 V

VCC = 3 V

TA = 60C
TA = 85C
I(LPM4)

TA = 40C
TA = 25C

Low-power mode, (LPM4)

MIN

VCC = 2.2 V/3 V

UNIT

A
A

TA = 85C
0.8
2.5
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The current consumption in LPM2, LPM3, and LPM4
are measured with active Basic Timer1 and LCD (ACLK selected).
The current consumption of the Comparator_A and the SVS module are specified in the respective sections.
2. The LPM3 currents are characterized with a KDS Daishinku DT38 (6 pF) crystal.

current consumption of active mode versus system frequency, F version

I(AM) = I(AM) [1 MHz] f(System) [MHz]

current consumption of active mode versus supply voltage, F version

I(AM) = I(AM) [3 V] + 140 A/V (VCC 3 V)

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19

PRODUCT PREVIEW

PARAMETER

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
Schmitt-trigger inputs Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI, TDO
PARAMETER

TEST CONDITIONS

VIT+

Positive-going input threshold voltage

VIT

Negative-going input threshold voltage

Vhys

Input voltage hysteresis (VIT+ VIT)

MIN

TYP

MAX

VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V

1.1

1.5

1.5

1.9

0.4

0.9

VCC = 3 V
VCC = 2.2 V

0.9

1.3

0.3

1.1

VCC = 3 V

0.5

UNIT
V
V
V

outputs Ports P1, P2, P3, P4, P5, and P6

PARAMETER

VOL

High-level output voltage

Low-level output voltage

MIN

IOH(max) = 1.5 mA,

IOH(max) = 6 mA,

VCC = 2.2 V,
VCC = 2.2 V,

See Note 1

IOH(max) = 1.5 mA,

IOH(max) = 6 mA,

VCC = 3 V,
VCC = 3 V,

See Note 1

IOL(max) = 1.5 mA,

IOL(max) = 6 mA,

VCC = 2.2 V,
VCC = 2.2 V,

See Note 1

IOL(max) = 1.5 mA,

IOL(max) = 6 mA,

VCC = 3 V,
VCC = 3 V,

See Note 1

See Note 2
See Note 2

TYP

MAX

VCC0.25
VCC0.6

VCC
VCC

VCC0.25
VCC0.6

VCC
VCC

VSS
VSS

VSS+0.25
VSS+0.6

VSS
VSS

VSS+0.25
VSS+0.6

See Note 2
See Note 2

UNIT

NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 24 mA to satisfy the maximum
specified voltage drop.

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs
LOW-LEVEL OUTPUT VOLTAGE

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs
LOW-LEVEL OUTPUT VOLTAGE
25

16
14

TA = 25C

VCC = 2.2 V
P1.0

12

IOL Typical Low-Level Output Current mA

IOL Typical Low-Level Output Current mA

PRODUCT PREVIEW

VOH

TEST CONDITIONS

TA = 85C

10
8
6
4
2
0
0.0

0.5

1.0

1.5

2.0

2.5

VCC = 3 V
P1.0
20

TA = 85C

15

10

0
0.0

VOL Low-Level Output Voltage V

0.5

1.0

1.5

2.0

Figure 3

NOTE A: One output loaded at a time

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2.5

3.0

VOL Low-Level Output Voltage V

Figure 2

20

TA = 25C

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

outputs Ports P1, P2, P3, P4, P5, and P6 (continued)

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs
HIGH-LEVEL OUTPUT VOLTAGE

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs
HIGH-LEVEL OUTPUT VOLTAGE
0

2
4
6
8
10

TA = 85C
12
TA = 25C
14
0.0

0.5

1.0

1.5

2.0

VCC = 3 V
P1.0
5

10

15

20

25

30
0.0

2.5

VOH High-Level Output Voltage V

TA = 85C

PRODUCT PREVIEW

VCC = 2.2 V
P1.0

IOH Typical High-Level Output Current mA

IOH Typical High-Level Output Current mA

TA = 25C

0.5

1.0

1.5

2.0

2.5

3.0

3.5

VOH High-Level Output Voltage V

Figure 4

Figure 5

NOTE A: One output loaded at a time

inputs Px.x, TAxx

PARAMETER

t(int)

t(cap)

External interrupt timing

Timer_A, capture timing

TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External trigger signal
for the interrupt flag, (see Note 1)

TAxx, (see Note 2)

f(TAext)

Timer_A clock frequency

externally applied to pin

TACLKx, INCLK t(H) = t(L)

f(TAint)

Timer_A clock frequency

SMCLK or ACLK signal selected

VCC
2.2 V/3 V

MIN

TYP

MAX

1.5

2.2 V

62

3V

50

2.2 V/3 V

1.5

2.2 V

62

3V

50

UNIT
cycle
ns
cycle
ns

2.2 V

3V

10

2.2 V

3V

10

MHz

MHz

NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. The external capture signal triggers the capture event every time the mimimum t(cap) cycle and time parameters are met. A capture
may be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a
correct capture of the 16-bit timer value and to ensure the flag is set.

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21

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
output frequency
PARAMETER

TEST CONDITIONS

fPx.y

(1 x 6, 0 y 7)

CL = 20 pF,
IL = 1.5mA

fACLK,
fMCLK,
fSMCLK

P1.1/TA0/MCLK, P1.5/TACLK/ACLK

CL = 20 pF

VCC = 2.2 V
VCC = 3 V

TYP

MAX

DC

10

DC

12

VCC = 2.2 V

UNIT
MHz

8
MHz

VCC = 3 V

P1.5/TACLK/ACLK,
CL = 20 pF
VCC = 2.2 V / 3 V
tXdc

MIN

Duty cycle of output frequency

P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V

fACLK = fLFXT1 = fXT1

fACLK = fLFXT1 = fLF

12
40%

60%

30%

70%

fACLK = fLFXT1/n

50%

fMCLK = fLFXT1/n

50%
15 ns

50%

50%+
15 ns

fMCLK = fDCOCLK

50%
15 ns

50%

50%+
15 ns

PRODUCT PREVIEW

wake-up LPM3 (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

NOM

t(LPM3) Delay time

VCC = 2.2 V/3 V
NOTE 1: The delay time t(LPM3) is independent of the system frequency and VCC.

MAX
6

UNIT
s

leakage current (see Note 1)

PARAMETER
Ilkg(P1.x)
Ilkg(P6.x)

Leakage
current

TEST CONDITIONS
Port P1

Port 1: V(P1.x) (see Note 2)

Port P6

Port 6: V(P6.x) (see Note 2)

MIN

NOM

MAX
50

VCC = 2.2 V/3 V

50

UNIT
nA

NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as an input.

RAM (see Note 1)

PARAMETER

TEST CONDITIONS

VRAMh

CPU halted (see Note 1)

MIN
1.6

TYP

MAX

UNIT
V

NOTE 1: This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program
execution should take place during this supply voltage condition.

22

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
LCD
PARAMETER
V(33)
V(23)

TEST CONDITIONS

MIN

Voltage at P5.7/R33

TYP

2.5

Analog voltage

Voltage at P5.5/R13

VCC = 3 V

Voltage at R33/R03

I(R03)

R03 = VSS

I(R13)

Input leakage

P5.5/R13 = VCC/3
P5.6/R23 = 2 VCC/3

I(R23)
V(Sxx0)
V(Sxx1)
V(Sxx2)

Segment line
voltage

I(Sxx) = 3 A,

VCC +0.2

2.5

V(Sxx3)

(V(33)V(03)) 1/3 + V(03)

VCC +0.2
20

No load at all
segment and
common lines,
VCC = 3 V

VCC = 3 V

UNIT

(V33V03) 2/3 + V03

Voltage at P5.6/R23

V(13)
V(33) V(03)

MAX

20

nA

20
V(03)
V(13)

V(03) 0.1
V(13) 0.1

V(23)
V(33)

V(23) 0.1
V(33) + 0.1

PARAMETER

TEST CONDITIONS

I(CC)

CAON = 1, CARSEL = 0, CAREF = 0

I(Refladder/RefDiode)

CAON = 1, CARSEL = 0,
CAREF = 1/2/3,
No load at P1.6/CA0/TA1 and P1.7/
CA1/TA2

MIN

TYP

MAX

VCC = 2.2 V
VCC = 3 V

25

40

45

60

VCC = 2.2 V

30

50

VCC = 3 V

45

71

Voltage @ 0.25 V CC node PCA0 = 1, CARSEL = 1, CAREF = 1,

No load at P1.6/CA0 and P1.7/CA1
V CC

VCC = 2.2 V / 3 V

0.23

0.24

0.25

V(Ref050)

Voltage @ 0.5 V CC node

PCA0 = 1, CARSEL = 1, CAREF = 2,

No load at P1.6/CA0 and P1.7/CA1

VCC = 2.2V / 3 V

0.47

0.48

0.50

PCA0 = 1, CARSEL = 1, CAREF = 3,

No load at P1.6/CA0 and P1.7/CA1;
TA = 85C

VCC = 2.2 V

390

480

540

VCC = 3.0 V

400

490

550

Common-mode input
voltage range

CAON = 1

VCC = 2. 2V/3 V

Offset voltage

See Note 2

VCC = 2.2 V/3 V

30

Input hysteresis

CAON = 1

VCC = 2.2 V / 3 V
VCC = 2.2 V

V(RefVT)
V(IC)
V(offset)
Vhys

TA = 25
25C,
C,
Overdrive 10 mV, without filter: CAF = 0
t(response LH)

25C
TA = 25
C
Overdrive 10 mV, with filter: CAF = 1
TA = 25
25C
C
Overdrive 10 mV, without filter: CAF = 0

t(response HL)

UNIT
A

V(Ref025)

V CC

PRODUCT PREVIEW

Comparator_A (see Note 1)

mV

VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V

VCC1.0

30

mV

0.7

1.4

mV

160

210

300

80

150

240

1.4

1.9

3.4

0.9

1.5

2.6

130

210

300

80

150

240

ns
s
ns

1.4
1.9
3.4
s
VCC = 3.0 V
0.9
1.5
2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
TA = 25
25C,
C,
Overdrive 10 mV, with filter: CAF = 1

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23

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE

REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE

650

650
VCC = 2.2 V
V(RefVT) Reference Voltage mV

V(RefVT) Reference Voltage mV

PRODUCT PREVIEW

VCC = 3 V
600
Typical
550

500

450

400
45

25

15

35

55

75

600
Typical
550

500

450

400
45

95

25

TA Free-Air Temperature C

Figure 6

35

Figure 7

0 V VCC
0

15

CAF

1
CAON
Low Pass Filter

V+
V

+
_

To Internal
Modules

CAOUT
Set CAIFG
Flag
2 s

Figure 8. Block Diagram of Comparator_A Module

VCAOUT

Overdrive
V

400 mV
V+

t(response)

Figure 9. Overdrive Definition

24

55

TA Free-Air Temperature C

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75

95

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
POR brownout, reset (see Notes 1 and 2)
PARAMETER

TEST CONDITIONS

td(BOR)
VCC(start)

MIN

dVCC/dt 3 V/s (see Figure 10)

V(B_IT)
Vhys(B_IT)

MAX

UNIT

2000

0.7 V(B_IT)

dVCC/dt 3 V/s (see Figure 10, Figure 11, Figure 12)

dVCC/dt 3 V/s (see Figure 10)

Brownout

TYP

70

130

V
1.71

180

mV

Pulse length needed at RST/NMI pin to accepted reset internally,

2
s
VCC = 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT)
+ Vhys(B_IT) is 1.8 V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT) + Vhys(B_IT). The default FLL+
settings must not be changed until VCC VCC(min). See the MSP430x4xx Family Users Guide (SLAU056) for more information on
the brownout/SVS circuit.
t(reset)

PRODUCT PREVIEW

VCC
Vhys(B_IT)
V(B_IT)
VCC(start)

0
td(BOR)

Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage

VCC

VCC (min) V

tpw

3V

V cc = 3 V
Typical Conditions
1.5
1

VCC(min)

0.5
0
0.001

1000
1 ns

tpw Pulse Width s

1 ns
tpw Pulse Width s

Figure 11. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal

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25

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
VCC

VCC (min) V

2
1.5

tpw

3V
V cc = 3 V
Typical Conditions

1
VCC(min)

0.5

tf = t r

0
0.001

1000

tf

tr

tpw Pulse Width s

tpw Pulse Width s

Figure 12. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
SVS (supply voltage supervisor), reset (see Notes 1 and 2)

PRODUCT PREVIEW

PARAMETER

TEST CONDITIONS

td(SVSR)
td(SVSon)
V(SVSstart)
V(SVS_IT)
Vhys(SVS_IT)
ICC(SVS)
(see Note 1)

MIN

dVCC/dt > 30V/ms (see Note 2)

dVCC/dt 30V/ms (see Note 2)
SVSon, switch from 0 to 1, VCC = 3 V (see Note 2)
SVS

MAX

UNIT

150

2000

150

1.55

1.7

20

dVCC/dt 3 V/s (see Figure 13)

dVCC/dt 3 V/s (see Figure 13)

1.8

1.95

2.2

dVCC/dt 3 V/s (see Figure 13)

70

100

155

mV

10

15

VLD 0 (VLD bits are in SVSCTL register), VCC = 2.2V/ 3V

NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data.
2. The SVS is not active at power up.

26

TYP

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
Software Sets VLD>0:
SVS is Active
VCC
V

Vhys(SVS_IT)

(SVS_IT)

V(SVSstart)

Vhys(B_IT)

V(B_IT)
VCC(start)

Brownout

Brownout
Region

Brownout

Region

1
0
td(BOR)

SVS Circuit is Active From VLD > to VCC < V(B_IT)

1
0

td(BOR)

PRODUCT PREVIEW

SVS out

td(SVSon)

Set POR
1

td(SVSR)
Undefined

Figure 13. SVS Reset (SVSR) vs Supply Voltage

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27

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
VCC
3V

tpw

2
Rectangular Drop
VCC(min)
VCC(min) V

1.5

Triangular Drop

1
1 ns

PRODUCT PREVIEW

0.5

1 ns

VCC
3V

tpw

0
1

10

100

1000

tpw Pulse Width s

VCC(min)
tf = t r
tf

tr

t Pulse Width s

Figure 14. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal

28

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
DCO
f(DCOCLK)

TEST CONDITIONS

VCC
2.2 V/3 V

MIN

TYP

2.2 V

0.3

0.65

1.25

3V

0.3

0.7

1.3

2.2 V

2.5

5.6

10.5

3V

2.7

6.1

11.3

2.2 V

0.7

1.3

2.3

3V

0.8

1.5

2.5

2.2 V

5.7

10.8

18

3V

6.5

12.1

20

2.2 V

1.2

3V

1.3

2.2

3.5

2.2 V

15.5

25

3V

10.3

17.9

28.5

2.2 V

1.8

2.8

4.2

3V

2.1

3.4

5.2

2.2 V

13.5

21.5

33

3V

16

26.6

41

2.2 V

2.8

4.2

6.2

3V

4.2

6.3

9.2

2.2 V

21

32

46

3V

30

46

70

2 < TAP 20

1.07

N(DCO)=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2, DCOPLUS= 0

f(DCO2)

FN_8=FN_4=FN_3=FN_2=0 , DCO+ = 1

f(DCO27)

FN_8=FN_4=FN_3=FN_2=0, DCO+ = 1, (see Note 1)

f(DCO2)

FN_8=FN_4=FN_3=0, FN_2=1; DCO+ = 1

f(DCO27)

FN_8=FN_4=FN_3=0, FN_2=1; DCO+ = 1, (see Note 1)

f(DCO2)

FN_8=FN_4=0, FN_3= 1, FN_2=x; DCO+ = 1

f(DCO27)

FN_8=FN_4=0, FN_3= 1, FN_2=x;, DCO+ = 1, (see Note 1)

f(DCO2)

FN_8=0, FN_4= 1, FN_3= FN_2=x; DCO+ = 1

f(DCO27)

FN_8=0, FN_4=1, FN_3= FN_2=x; DCO+ = 1, (see Note 1)

f(DCO2)

FN_8=1, FN_4=FN_3=FN_2=x; DCO+ = 1

f(DCO27)

FN_8=1,FN_4=FN_3=FN_2=x,DCO+ = 1, (see Note 1)

f(NDCO)+1 = f(NDCO)

Dt

Temperature drift, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0

D = 2, DCO+ = 0, (see Note 2)

DV

Drift with VCC variation, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0

D = 2, DCO+ = 0 (see Note 2)

MAX

UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz

PRODUCT PREVIEW

PARAMETER

MHz
MHz
MHz
MHz

1.13

TAP > 20

1.1

2.2 V

0.2

0.3

1.17
0.4

3V

0.2

0.3

0.4

15

%/_C
/_
%/V

NOTES: 1. Do not exceed the maximum system frequency.

2. This parameter is not production tested.
f
f

(DCO)
f

(DCO3V)

(DCO)

(DCO20C)

1.0

1.0

1.8

2.4

3.0

3.6
VCC V

40

20

20

40

60

85
TA C

Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature

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29

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

f(DCO)

Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}

PRODUCT PREVIEW

Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range

FN_2=0
FN_3=0
FN_4=0
FN_8=0

FN_2=1
FN_3=0
FN_4=0
FN_8=0

FN_2=x
FN_3=1
FN_4=0
FN_8=0

FN_2=x
FN_3=x
FN_4=1
FN_8=0

FN_2=x
FN_3=x
FN_4=x
FN_8=1

Figure 16. Five Overlapping DCO Ranges Controlled by FN_x Bits

crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER

C(XIN)

C(XOUT)

TEST CONDITIONS

Integrated input capacitance

Integrated output capacitance

OSCCAP = 0

VCC
2.2 V / 3

MIN

TYP

OSCCAP = 1

2.2 V / 3

10

OSCCAP = 2

2.2 V / 3

14

OSCCAP = 3

2.2 V / 3

18

OSCCAP = 0

2.2 V / 3

OSCCAP = 1

2.2 V / 3

10

OSCCAP = 2

2.2 V / 3

14

OSCCAP = 3

2.2 V / 3

18

MAX

UNIT

0
pF

pF

NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2pF. The effective load capacitor for the crystal is
(XCIN x XCOUT) / (XCIN + XCOUT). It is independent of XST_FLL .
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines must be
observe:
Keep as short a trace as possible between the xW42x and the crystal.
Design a good ground plane around oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to XIN an XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation.
This signal is no longer required for the serial programming adapter.

30

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
Scan I/F, port drive, port timing
TEST CONDITIONS

VOL(SIFVCCEx)
VOL(SIFCHx)

I(SIFVCCEx) = 3 mA
I(SIFCHx) = 3 mA

VOH(SIFCHx)
ISIFCHx(tri-state)

I(SIFCHx) = 200 A
V(SIFCHx) = 0 V to AVCC, port function disabled

VCC
2.2 V/3 V

MIN

TYP

3V
3V
3V

50

MAX

UNIT

0.1

0.3

0.1

50

nA

tdSIFCH(HL)

Delay from
internal signal
Ex(tsm) to pin
SIFCHx

I(SIFCHx) = 3 mA,
twEx(tsm) = 500 ns 20%

2.2 V/3 V

100

ns

tdSIFCH(LH)

Delta delay
from internal
signal Ex(tsm)
to pin SIFCHx

I(SIFCHx) = 3 mA,
twEx(tsm) = 500 ns 20%

2.2 V/3 V

100

ns

tdSIFCH
(twEx(tsm)twSIFCH)

Change of
pulse width of
internal signal
Ex(tsm) to
pulse width at
pin SIFCHx

I(SIFCHx) = 3 mA,
twEx(tsm) = 500 ns 20%

2.2 V/3 V

20

ns

tEx(SIFCHx)
t dSIFCH(LH)

20

PRODUCT PREVIEW

PARAMETER

tdSIFCH(HL)

SIFEx(tsm)

P6.x/SIFCH.x
tSIFCH(x)

Figure 17. P6.x/SIFCHx timing, SIFCHx function selected

Scan I/F, sample capacitor/Ri timing
PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

CSHC(SIFCHx)

Sample capacitance
at SIFCHx pin

SIFEx(tsm) = 1, SIFSH = 1

2.2 V/3 V

pF

Ri(SIFCHx)

Serial input resistance

at the SIFCHx pin

SIFEx(tsm) = 1, SIFSH = 1

2.2 V/3 V

1.5

tHold
(See Notes 1 and 2)

Maximum hold time

Vsample < 3 mV

0.3

62

NOTES: 1. The sampled voltage at the sample capacitance varies less than 3 mV (Vsample) during the hold time tHold. If the voltage is sampled
after tHold, the sampled voltage may be any other value.
2. The minimum sampling time (7.6 x tau for 1/2 LSB accuracy) with maximum CSHC(SIFCHx) and Ri(SIFCHx) and Ri(source) is
tsample(min) ~ 7.6 x CSHC(SIFCHx) x (Ri(SIFCHx) + Ri(source))
with Ri(source) estimated at 3 k, tsample(min) = 319 ns.

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31

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
Scan I/F, VCC/2 generator

PRODUCT PREVIEW

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

AVCC

Analog supply voltage

AVCC and DVCC are connected together

AVSS and DVSS are connected together

AICC

Scan I/F VCC/2

generator operating
supply current into
AVCC terminal

CL at SIFVCCEx pin = 470 nF 20%,

frefresh(SIFVCCEx) = 32768 Hz

V(SIFVCCEx)

Output voltage at pin

SIFVCCEx

CL at SIFVCCEx pin = 470 nF 20%,

SIFVCCEx source
current

2.2 V

500

Isource(SIFVCCEx)

3V

900

SIFVCCEx sink
current

2.2 V

150

Isink(SIFVCCEx)

3V

180

VLoad(SIFVCCEx)

Voltage Drop on Load

trecovery(SIFVCCEx)

Time to recover from

Voltage Drop on Load

frefresh(SIFVCCEx)

VCC/2 refresh
frequency
Time to reach 98%
after VCC/2 is
switched on

CL at SIFVCCEX pin = 470 nF 20%

frefresh(SIFVCCEx) = 32768 Hz

2.2 V/3 V

ton(SIFVCCEx)

tSettle(SIFVCCEx)
(See Note 1)

Settling time to
VCC/1024 (1 LSB)
after sensor exitation

L = 1mH, C = 82pF, tex < 500ns

frefresh(SIFVCCEx) = 32768 Hz

2.2 V/3 V

kSVR(SIFVCCEx)

Supply voltage
rejection ratio

VCC = AVCC 100 mVPP, 1 kHz

tVccSettle(SIFVCCEx)
(See Note 2)

Settling time to
VCC/512 (2 LSB)
after av AVCC voltage
change

ILoad = 3 mA. tLoad(on) = 500ns,

CL at SIFVCCEx pin = 470 nF 20%
ILoad2 = 3 mA, ILoad1 = ILOAD3 = 0 mA,
tload(on) = 500nS,
CL at SIFVCCEx pin = 470 nF 20%
Source clock = ACLK
f(ACLK) = 32768 Hz
CL at SIFVCCEx pin = 470 nF 20%

2.2

3.6

2.2 V

220

320

3V

TBD

400

nA

AVCC/2
.05

2.2 V/3 V

AVCC/2
+ .05

2.2 V/3 V

V
A
nA

mV

30

2.2 V/3 V
30

32.768

1.7

kHz

ms

2.2 V/3 V

60

db

SIFEN = 1, SIFVCC2 = 1, SIFSH = 0,

AVCC = AVCC 100 mV
frefresh(SIFVCCEx) = 32768 Hz

2.2 V/3 V

TBD

AVCC = AVCC + 100mV

frefresh(SIFVCCEx) = 32768 Hz

2.2 V/3 V

s
TBD

NOTES: 1. The settling time is zero because the voltage drop of an LC-sensor excitement is less than 0.5 LSB.
2. The settling time after an AVCC voltage change is the time to for the voltage at pin SIFVCCEx to settle to AVCC/2 2LSB.

32

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
Scan I/F, 10-bit DAC (See Note 1)
TEST CONDITIONS

VCC

AVCC

Analog supply voltage

AVCC and DVCC are connected together

AVSS and DVSS are connected together

AICC

Scan I/F 10-bit DAC

operating supply
current into AVCC
terminal

CL at SIFVCCEx pin = 470 nF 20%,

frefresh(SIFVCCEx) = 32768 Hz

MIN
2.2

MAX
3.6

2.2 V

23

40

3V

33

50

UNIT
V

Resolution

10

INL

RL = 1000 M,
CL = 20 pF

2.2 V/3 V

DNL

RL = 1000 M,
CL = 20 pF

EZS
EG
RO (Figure 18)

Output resistance

ton(SIFDAC)

On time after AVCC of

SIFDAC is switched on

tSettle(SIFDAC)

TYP

bit
TBD

LSB

2.2 V/3 V

LSB

Zero Scale Error

2.2 V/3 V

10

mV

Gain Error

2.2 V/3 V

Settling time

25

0.6

50

V+SIFCA VSIFDAC = 6 mV

2.2 V/3 V

2.0

SIFDAC code = 1C0h 240h

VSIFDAC(240h) V+SIFCA = +6 mV

2.2 V/3 V

2.0

2.0

SIFDAC code = 240h 1C0h,

2.2 V/3 V
VSIFDAC(1C0h) V+SIFCA = 6 mV
NOTES: 1. The SIFDAC operates from AVCC and SIFGND. All parameters are based on these references.

PRODUCT PREVIEW

PARAMETER

RO

SIFDAC Output

1023

Figure 18. SIFDAC Typical Output Impedance

POST OFFICE BOX 655303

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33

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
Scan I/F, Comparator

PRODUCT PREVIEW

PARAMETER
AVCC

Analog supply voltage

AICC

Scan I/F comparator

operating supply
current into AVCC
terminal

TEST CONDITIONS

VCC

AVCC and DVCC are connected together

AVSS and DVSS are connected together

MIN

TYP

2.2

MAX
3.6

2.2 V

25

35

3V

35

50

UNIT
V

VIC

Common Mode Input

Voltage Range
(see Note 1)

2.2 V/3 V

VOffset

Input Offset Voltage

2.2 V/3 V

Dt(Offset)

Temperature Drift of
VOffset

2.2 V/3 V

10

V/_C

DV(Offset)

Drift of VOffset with

VCC variation

2.2 V/3 V

0.3

mV/V

Vhys

Input Voltage
Hysteresis

V+terminal = Vterminal = 0.5 x VCC

ton(SIFCA)

On time after SIFCA

is switched on

V+SIFCA VSIFDAC = +6 mV
V+SIFCA = 0.5 x AVCC

AVCC
0.5

0.9

15

2.2V

0.25

5.0

3.0V

0.25

6.0

2.2 V/3 V

2.0

V+SIFCA VSIFDAC= 12 mV 6 mV
2.2 V/3 V
2.0
V+SIFCA = 0.5 x AVCC
NOTES: 1. The comparator output is reliable when at least one of the input signals is within the common mode input voltage range.
tSettle(SIFCA)

Settle time

V
mV

mV
us
us

Scan I/F, SIFCLK Oscillator

PARAMETER
AVCC

Analog supply voltage

AICC

Scan I/F comparator

operating supply
current into AVCC
terminal

ton(SIFCLKG)

Settling time to full

operation after VCC is
switched on

S(SIFCLK)

Frequency Change
per +/1 Step of
SIFCLKFQ(SIFCTL5)

Dt

Temperature Drift

DV

Drift w/ VCC varation

VCC

AVCC and DVCC are connected together

AVSS and DVSS are connected together

MIN

TYP

2.2

MAX
3.6

2.2 V

70

3V

80

UNIT
V

A
TA = 25oC, SIFFNOM(SIFCTL5) = 0
TA = 25oC, SIFFNOM(SIFCTL5) = 1

f(SIFCLKG)
f(SIFCLKG)

34

TEST CONDITIONS

2.2 V/3 V

2.7

4.0

6.0

MHz

2.2 V/3 V

0.7

1.0

1.5

MHz

2.2 V/3 V

150

500

ns

1.06

Hz/Hz

S(SIFCLK) = f(SIFCLKFQ + 1) / f(SIFCLKFQ)

2.2 V/3 V

SIFCLKFQ(SIFCTL5) = 8
SIFCLKFQ(SIFCTL5) = 8

2.2 V/3 V

0.2

%/_C

2.2 V/3 V

1.2

%/V

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1.0

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)
JTAG, program memory and fuse
PARAMETER
f(TCK)

TEST CONDITIONS
TCK frequency (see Note 5)

JTAG/Test

VCC
2.2 V

MIN

TYP

MAX

DC

3V

DC

10

2.2 V/ 3 V

25

UNIT
MHz

R(TMS, TCK, TDI)

Pullup resistors on
TMS, TCK, TDI (see Note 1)

VCC(FB)

Supply voltage during fuse blow condition,

TA = 25C

2.5

Fuse blow voltage, C versions (see Note 4)

3.5

3.9

Fuse blow voltage, F versions (see Note 3)

6.0

7.0

100

mA

ms

mA

3
5
10

mA

Supply current on TDI during fuse is blown

Time to blow the fuse

I(DD-PGM)

F-versions only

Current from programming voltage source

(see Note 6)

I(DD-Erase)

F-versions only

Programming time, single pulse (see Note 6)

NOTES: 1.
2.
3.
4.
5.
6.

JTAG/Fuse
(see Note 2)

IFB
tFB

t(retention)

90

F-versions only

2.7 V/3.6 V
2.7 V/3.6 V

Write/Erase cycles

104

Data retention TJ = 25C

100

cycles
years

TMS, TDI, and TCK pullup resistors are implemented in all C- and F-versions.
Once the fuse is blown, no further access to the MSP430 JTAG/test feature is possible. The JTAG block is switched to bypass mode.
The supply voltage to blow the fuse is applied to TDI pin.
The power source to blow the fuse is applied to the TDI pin.
f(TCK) may be restricted to meet the timing requirements of the module selected.
Duration of the program/erase cycle is determined by f(FTG) applied to the flash timing controller. It can be calculated as follows:
t(word write) = 35
1/f(FTG)
t(block write, byte 0) = 30
1/f(FTG)
t(block write, byte 1 63) = 20
1/f(FTG)
t(block write, sequence end) = 6
1/f(FTG)
t(mass erase) = 5297
1/f(FTG)
t(segment erase) = 4819
1/f(FTG)

POST OFFICE BOX 655303

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35

PRODUCT PREVIEW

VFB

60

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic
Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
Pad Logic

CAPD.x
P1SEL.x

0: Input
1: Output

P1DIR.x
Direction Control
From Module
P1OUT.x

1
0
1

Module X OUT

Bus
keeper

P1.0/TA00
P1.1/TA00(I)/MCLK
P1.2/TA10
P1.3/TA01/SVSOut
P1.4/TA01
P1.5/TACLK0/ACLK

P1IN.x
EN
D

PRODUCT PREVIEW

Module X IN

P1IE.x

P1IRQ.x

P1IFG.x

EN

Interrupt
Edge
Select

Set

P1IES.x

P1SEL.x

NOTE: 0 x 5.
Port Function is Active if CAPD.x = 0
PnSEL.x

PnDIR.x

Direction
Control
From Module

PnOUT.x

Module X
OUT

PnIN.x

Module X IN

PnIE.x

PnIFG.x

PnIES.x

P1SEL.0

P1DIR.0

P1DIR.0

P1OUT.0

Out0 Sig.

P1IN.0

CCI0A

P1IE.0

P1IFG.0

P1IES.0

P1SEL.1

P1DIR.1

P1DIR.1

P1OUT.1

MCLK

P1IN.1

CCI0B

P1IE.1

P1IFG.1

P1IES.1

P1SEL.2

P1DIR.2

P1DIR.2

P1OUT.2

Out1 Sig.

P1IN.2

CCI1A

P1IE.2

P1IFG.2

P1IES.2

P1SEL.3

P1DIR.3

P1DIR.3

P1OUT.3

SVSOut

P1IN.3

CCI0B

P1IE.3

P1IFG.3

P1IES.3

P1SEL.4

P1DIR.4

P1DIR.4

P1OUT.4

Out0 Sig.

P1IN.4

CCI0A

P1IE.4

P1IFG.4

P1IES.4

P1SEL.5

P1DIR.5

P1DIR.5

P1OUT.5

ACLK

P1IN.5

TACLK

P1IE.5

P1IFG.5

P1IES.5

Timer_A0
Timer_A1

36

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

Port P1, P1.6, P1.7 input/output with Schmitt-trigger
Pad Logic

Note: Port Function Is Active if CAPD.6 = 0

CAPD.6
P1SEL.6

0: Input
1: Output

0
P1DIR.6
1

P1DIR.6

P1.6/
CA0

0
P1OUT.6
1

DVSS

Bus
Keeper

P1IN.6
EN
unused

D
P1IE.7
EN

Interrupt
Edge
Select

Q
P1IFG.7
Set

P1IES.x

PRODUCT PREVIEW

P1IRQ.07

P1SEL.x

Comparator_A

P2CA
AVcc

CAREF

CAEX
CA0

CAF
CCI1B

to Timer_Ax

CA1

2
Reference Block

CAREF

Pad Logic

Note: Port Function Is Active if CAPD.7 = 0

CAPD.7
P1SEL.7

0: Input
1: Output

P1DIR.7

P1.7/
CA1

P1DIR.7
0
P1OUT.7
1

DVSS

Bus
Keeper

P1IN.7
EN
unused

P1IE.7
P1IRQ.07

EN
Q
P1IFG.7
Set

Interrupt
Edge
Select

P1IES.7

P1SEL.7

POST OFFICE BOX 655303

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37

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

port P2, P2.0 to P2.7, input/output with Schmitt-trigger
P2.0, P2.1
LCDM.5
LCDM.6
P2.2 to P2.5
LCDM.7
P2.6, P2.7
0: Port Active
1: Segment xx
Function Active

Pad Logic

Segment xx

P2SEL.x

PRODUCT PREVIEW

0: Input
1: Output

P2DIR.x
Direction Control
From Module
P2OUT.x

1
0

P2.x

Module X OUT

Bus
keeper

P2.0/TA20
P2.1/TA11
P2.2/TA21/S23
P2.3/TA31/S22
P2.4/TA41/S21
P2.5/TACLK1/S20
P2.6/CAOUT/S19
P2.7/SIFCLKG/S18

P2IN.x
EN
Module X IN

D
P2IE.x

P2IRQ.x

P2IFG.x

EN
Set

NOTE: 0 x 7

Interrupt
Edge
Select
P2IES.x

P2SEL.x

PnSEL.x

PnDIR.x

Direction
Control
From Module

PnOUT.x

Module X
OUT

PnIN.x

Module X IN

PnIE.x

PnIFG.x

PnIES.x

P2SEL.0

P2DIR.0

P2DIR.0

P2OUT.0

Out2 Sig.

P2IN.0

CCI2A

P2IE.0

P2IFG.0

P2IES.0

P2SEL.1

P2DIR.1

P2DIR.1

P2OUT.1

Out1 Sig.

P2IN.1

CCI1A

P2IE.1

P2IFG.1

P2IES.1

P2SEL.2

P2DIR.2

P2DIR.2

P2OUT.2

Out2 Sig.

P2IN.2

CCI2A

P2IE.2

P2IFG.2

P2IES.2

P2SEL.3

P2DIR.3

P2DIR.3

P2OUT.3

Out3 Sig.

P2IN.3

CCI3A

P2IE.3

P2IFG.3

P2IES.3

P2SEL.4

P2DIR.4

P2DIR.4

P2OUT.4

Out4 Sig.

P2IN.4

CCI4A

P2IE.4

P2IFG.4

P2IES.4

P2SEL.5

P2DIR.5

P2DIR.5

P2OUT.5

DVSS

P2IN.5

TACLK1

P2IE.5

P2IFG.5

P2IES.5

P2SEL.6

P2DIR.6

P2DIR.6

P2OUT.6

CAOUT

P2IN.6

Unused

P2IE.6

P2IFG.6

P2IES.6

P2SEL.7

P2DIR.7

P2DIR.7

P2OUT.7

SIFCLKG

P2IN.7

Unused

P2IE.7

P2IFG.7

P2IES.7

Timer_A0
Timer_A1
Scan I/F

38

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

port P3, P3.0, P3.7, input/output with Schmitt-trigger
LCDM.5
LCDM.6
LCDM.7

P3.2 to P3.7

P3.0, P3.1
0: Port Active
1: Segment xx
Function Active

Pad Logic

Segment xx

P3SEL.x

0: Input
1: Output

P3DIR.x
Direction Control
From Module
P3OUT.x

1
0
1

Bus
keeper

P3.0/S17
P3.1/S16
P3.2/S15
P3.3/S14
P3.4/S13
P3.5/S12
P3.6/S11
P3.7/S10

P3IN.x
EN
D

Module X IN

PRODUCT PREVIEW

Module X OUT

P3.x

NOTE: 0 x 7

PnSEL.x

PnDIR.x

Direction
Control
From Module

PnOUT.x

Module X
OUT

PnIN.x

Module X IN

P3SEL.0

P3DIR.0

P3DIR.0

P3OUT.0

DVSS

P3IN.0

Unused

P3SEL.1

P3DIR.1

P3DIR.1

P3OUT.1

DVSS

P3IN.1

Unused

P3SEL.2

P3DIR.2

P3DIR.2

P3OUT.2

DVSS

P3IN.2

Unused

P3SEL.3

P3DIR.3

P3DIR.3

P3OUT.3

DVSS

P3IN.3

Unused

P3SEL.4

P3DIR.4

P3DIR.4

P3OUT.4

DVSS

P3IN.4

Unused

P3SEL.5

P3DIR.5

P3DIR.5

P3OUT.5

DVSS

P3IN.5

Unused

P3SEL.6

P3DIR.6

P3DIR.6

P3OUT.6

DVSS

P3IN.6

Unused

P3SEL.7

P3DIR.7

P3DIR.7

P3OUT.7

DVSS

P3IN.7

Unused

POST OFFICE BOX 655303

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39

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

port P4, P4.0 to P4.7, input/output with Schmitt-trigger
LCDM.5
LCDM.6
LCDM.7

0: Port Active
1: Segment xx
Function Active

Pad Logic

Segment xx

P4SEL.x

0: Input
1: Output

P4DIR.x
Direction Control
From Module
P4OUT.x

1
0
1

Module X OUT

P4.x
Bus
keeper

P4.0/S9
P4.1/S8
P4.2/S7
P4.3/S6
P4.4/S5
P4.5/S4
P4.6/S3
P4.7/S2

P4IN.x

PRODUCT PREVIEW

EN
D

Module X IN

NOTE: 0 x 7

40

PnSEL.x

PnDIR.x

Direction
Control
From Module

PnOUT.x

Module X
OUT

PnIN.x

Module X IN

P4SEL.0

P4DIR.0

P4DIR.0

P4OUT.0

DVSS

P4IN.0

Unused

P4SEL.1

P4DIR.1

P4DIR.1

P4OUT.1

DVSS

P4IN.1

Unused

P4SEL.2

P4DIR.2

P4DIR.2

P4OUT.2

DVSS

P4IN.2

Unused

P4SEL.3

P4DIR.3

P4DIR.3

P4OUT.3

DVSS

P4IN.3

Unused

P4SEL.4

P4DIR.4

P4DIR.4

P4OUT.4

DVSS

P4IN.4

Unused

P4SEL.5

P4DIR.5

P4DIR.5

P4OUT.5

DVSS

P4IN.5

Unused

P4SEL.6

P4DIR.6

P4DIR.6

P4OUT.6

DVSS

P4IN.6

Unused

P4SEL.7

P4DIR.7

P4DIR.7

P4OUT.7

DVSS

P4IN.7

Unused

POST OFFICE BOX 655303

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

port P5, P5.0, P5.1, input/output with Schmitt-trigger
LCDM.5
LCDM.6
LCDM.7

0: Port Active
1: Segment
Function Active

Pad Logic

Segment xx or
COMx or Rxx
P5SEL.x

0: Input
1: Output

P5DIR.x
Direction Control
From Module
P5OUT.x

1
0
1

Module X OUT

P5.x
Bus
keeper

P5.0/S1
P5.1/S0

P5IN.x

PRODUCT PREVIEW

EN
D

Module X IN

NOTE: x = 0, 1

PnSEL.x

PnDIR.x

Direction
Control
From Module

PnOUT.x

Module X
OUT

PnIN.x

Module X IN

Segment

P5SEL.0

P5DIR.0

P5DIR.0

P5OUT.0

DVSS

P5IN.0

Unused

S1

P5SEL.1

P5DIR.1

P5DIR.1

P5OUT.1

DVSS

P5IN.1

Unused

S0

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41

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

port P5, P5.2, P5.4, input/output with Schmitt-trigger
0: Port Active
1: COMx Function
Active

Pad Logic

COMx

P5SEL.x

0: Input
1: Output

P5DIR.x
Direction Control
From Module
P5OUT.x

1
0
1

Module X OUT

P5.x
Bus
keeper

P5.2/COM1
P5.3/COM2
P5.4/COM3

P5IN.x

PRODUCT PREVIEW

EN
D

Module X IN
NOTE: 2 x 4

PnSEL.x

PnDIR.x

Direction
Control
From Module

PnOUT.x

Module X
OUT

PnIN.x

Module X IN

COMx

P5SEL.2

P5DIR.2

P5DIR.2

P5OUT.2

DVSS

P5IN.2

Unused

COM1

P5SEL.3

P5DIR.3

P5DIR.3

P5OUT.3

DVSS

P5IN.3

Unused

COM2

P5SEL.4

P5DIR.4

P5DIR.4

P5OUT.4

DVSS

P5IN.4

Unused

COM3

NOTE:
The direction control bits P5SEL.2, P5SEL.3, and P5SEL.4 are used to distinguish between port
and common functions. Note that a 4MUX LCD requires all common signals COM3 to COM0, a
3MUX LCD requires COM2 to COM0, 2MUX LCD requires COM1 to COM0, and a static LCD
requires only COM0.

42

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

port P5, P5.5 to P5.7, input/output with Schmitt-trigger
0: Port Active
1: Rxx Function
Active

Pad Logic

Rxx

P5SEL.x

0: Input
1: Output

P5DIR.x
Direction Control
From Module
P5OUT.x

1
0
1

Module X OUT

P5.x
Bus
keeper

P5.5/R13
P5.6/R23
P5.7/R33

P5IN.x

PRODUCT PREVIEW

EN
D

Module X IN
NOTE: 5 x 7

PnSEL.x

PnDIR.x

Direction
Control
From Module

PnOUT.x

Module X
OUT

PnIN.x

Module X IN

Rxx

P5SEL.5

P5DIR.5

P5DIR.5

P5OUT.5

DVSS

P5IN.5

Unused

R13

P5SEL.6

P5DIR.6

P5DIR.6

P5OUT.6

DVSS

P5IN.6

Unused

R23

P5SEL.7

P5DIR.7

P5DIR.7

P5OUT.7

DVSS

P5IN.7

Unused

R33

NOTE:
The direction control bits P5SEL.5, P5SEL.6, and P5SEL.7 are used to distinguish between port
and LCD analog level functions. Note that 4MUX and 3MUX LCDs require all Rxx signals R33 to
R03, a 2MUX LCD requires R33, R13, and R03, and a static LCD requires only R33 and R03.

POST OFFICE BOX 655303

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43

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

port P6, P6.0 P6.1, P6.2, P6.4, P6.5, input/output with Schmitt-trigger
P6SEL.x
0

P6DIR.x
Direction Control
From Module

0: Input
1: Output
Pad Logic
P6.X

P6OUT.x
Module X OUT

1
P6.0/SIFCH0
P6.1/SIFCH1
P6.2/SIFCH2
P6.4/SIFCI0
P6.5/SIFCI1
Bus Keeper

P6IN.x

PRODUCT PREVIEW

EN
Module X IN

To/From Scan I/F

x: Bit Identifier = 0, 1, 2, 4, or 5
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 01 or 10. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 A.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin.
PnSel.x

PnDIR.x

Dir. Control
From Module

PnOUT.x

Module X OUT

PnIN.x

Module X IN

P6Sel.0

P6DIR.0

P6DIR.0

P6OUT.0

DVSS

P6IN.0

unused

P6Sel.1

P6DIR.1

P6DIR.1

P6OUT.1

DVSS

P6IN.1

unused

P6Sel.2

P6DIR.2

P6DIR.2

P6OUT.2

DVSS

P6IN.2

unused

P6Sel.4

P6DIR.4

P6DIR.4

P6OUT.4

DVSS

P6IN.4

unused

P6IN.5

unused

P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
NOTE: The signal at pins P6.x/SIFCHx and P6.x/SIFCIx are shared by Port P6 and the San I/F module.

44

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

port P6, P6.3 input/output with Schmitt-trigger
P6SEL.3
0

P6DIR.3

0: Input
1: Output
Pad Logic
P6.3/SIFCH3/SIFCAOUT

P6OUT.x
SIFCAOUT

Bus Keeper
P6IN.3

Module X IN

To/From Scan I/F

NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if
the analog signal is in the range of transitions 01 or 10. The value of the throughput current depends on the driving capability of the
gate. For MSP430, it is approximately 100 A.
Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin.

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45

PRODUCT PREVIEW

EN

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

port P6, P6.6 input/output with Schmitt-trigger
P6SEL.6
0

P6DIR.6

0: Input
1: Output
Pad Logic
P6.6/SIFCI2/DACOUT

P6OUT.6
DVss

Bus Keeper
P6IN.6

PRODUCT PREVIEW

EN
Module X IN

From Scan I/F DAC

To Scan I/F comparator input mux

46

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MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

input/output schematic (continued)

port P6, P6.7 input/output with Schmitt-trigger
SVS VLDx=15
P6SEL.7
P6DIR.7

0
1

0: Input
1: Output
Pad Logic
P6.6/SIFCI3/SVSin

P6OUT.7
DVss

Bus Keeper
P6IN.7

Module X IN

PRODUCT PREVIEW

EN
D

SVS VLDx=15
1

To SVS
To Scan I/F comparator (+) terminal

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47

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

JTAG pins TMS, TCK, TDI, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI

JTAG
Controlled
by JTAG

DVCC

TDI

Burn and Test

Fuse

PRODUCT PREVIEW

TDI
Test
and
Emulation

DVCC
TMS

Module
TMS
DVCC
TCK
TCK
RST/NMI

Tau ~ 50 ns
Brownout

TCK

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D
U
S

D
U
S

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

JTAG fuse check mode

MSP430 devices that have the fuse on the TDI terminal have a fuse check mode that tests the continuity of the
fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current,
ITF , of 1.8 mA at 3 V can flow from the TDI pin to ground if the fuse is not burned. Care must be taken to avoid
accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 19). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
The JTAG pins are terminated internally, and therefore do not require external termination.
Time TMS Goes Low After POR

ITDI

PRODUCT PREVIEW

TMS

ITF

Figure 19. Fuse Check Mode Current, MSP430CW42x, MSP430FW42x

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49

MSP430xW42x
MIXED SIGNAL MICROCONTROLLER
SLAS383 MARCH 2003

MECHANICAL DATA
PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27
0,17

0,50

33

48

PRODUCT PREVIEW

0,08 M

49

32

64

17
0,13 NOM

16
7,50 TYP
10,20
SQ
9,80
12,20
SQ
11,80

Gage Plane

0,25
0,05 MIN

07

0,75
0,45

1,45
1,35

Seating Plane
0,08

1,60 MAX

4040152 / C 11/96
NOTES: A.
B.
C.
D.

50

All linear dimensions are in millimeters.

This drawing is subject to change without notice.
Falls within JEDEC MS-026
May also be thermally enhanced plastic with leads connected to the die pads.

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