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Chapter 5 Ee604 PDF
Chapter 5 Ee604 PDF
Chapter 5 Ee604 PDF
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CHAPTER 5:
FULL CHIP
INTEGRATION AND
TAPE OUT
3/23/2015
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SYLLABUS
5.0 FULL CHIP INTEGRATION AND TAPE OUT
5.1 Explain full chip integration and tape out
5.1.1 Arrange Basic Full Chip Development
Cycle
5.2 Determine Basic Full Chip Layout Components
5.2.1 Identify Basic Tape Out Flow and
Activities involved
5.2.2 Classify Elements of Optical Proximity
Corrections (OPC)
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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Physical Layout
TAPEOUT
Mask Generation
Wafer Generation
Assembly
Testing
Shipment of Final Product
3/23/2015
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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5.2
Determine
Basic
Full
Chip
Full Chip Components
Layout Components
Full Chip Floorplan
IOs
-Inputs/Outputs buffers
-pads
-periphery
EBBs
-datapath
-memory
-analog special circuit
CBD
-Standard cells APR
-Sea Of Cells
-core
3/23/2015
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Course Title
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
Introduction
Full chip floorplanning is a top down process
and bottom up fine tuning.
Setting the size, shape, and placements of
the blocks
Planning the power, clock and signal
routing
Repeating the process for each lower
level of hierarchy
This process continues until the EBB floor
plan is complete when the floor plan
reflects exact sizes and placements for all
the blocks in the EBB, and routing that
fully connects all these blocks.
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Logic Gate
Transitors
VCC
Sticks
ethel
P-diffusion
lucy
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DEMO
N-Diffusion
Layout
VSS
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EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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Stream out or merge the notchfix cell into the fullchip then submit jobs (30 mins)
XOR
2 hrs
DRCD
6 hrs
DRCBM
2 hrs
ERC
4 hrs
LVS
4 hrs
TFC
1.5 hrs
NAC
3 hrs
C- thru
2hrs
NAC
3 hrs
C- thru
2 hrs
NO
Clean?
YES
Metals
Dummification.
( 4hrs for each layer)
Risk Fracture
database
DRCD
6 hrs
TAPEOUT
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
DRCBM
2 hrs
ERC
4 hrs
YES
LVS
4 hrs
Clean ?
TFC
1.5 hrs
NO
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b) 2
c) 3
d) 4
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Initial Concept
Logic
Schematic Design
Physical Layout
TAPEOUT
Mask Generation
Wafer Generation
Assembly
Testing
Shipment of Final Product
3/23/2015
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My Design done
Fabrication
1
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
Tapeout Process
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
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Layout
Logic
Verification
Concept
Tapeout
FAB PE
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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Fracture
Drawn database showing poly, diffusion regions, and
contacts
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Fracture - Sizing
Fracture will alter (size) the data to meet the
requirements of the process and Fab.
Data sized
up by 0.2
m per
side
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Synthesis
AND poly N+
npoly
AND poly P+
ppoly
OR npoly
ppoly gate
Metal
ppoly
npoly
P+
N+
Poly
pWell
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Fracture - CF Mask
Poly fractures to a clear field mask
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
Simple drawn
geometries are
comprehensively
modified using
post-layout flows
6x increase in vertices means larger database sizes
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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DRAWN
What We draw is
Not what we get.
ACTUAL
Silicon
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
Lines shorter
Curves
bulge/larger
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Input
Output
2-D corrections
applied
Uncorrected Data
Uncorrected Data
3/23/2015
Corrected Data
1-D and 2-D
corrections applied
Corrected Data
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More Vertices
More Vertices
3/23/2015
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Fewer Vertices
Fewer Vertices
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More Vertices
Fewer Vertices
More Vertices
Fewer Vertices
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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Metal stub
3/23/2015
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Original Layout
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
Better
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Original Layout
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
Better
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Applies to diffusion,
poly, and metal layers
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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Small
Dummies
Large Dummies
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
Etch
Polish
Annealing
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3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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Oxide
Oxide
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
Polish Breakthrough
Polish Breakthrough
No Remaining Nitride!
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What is CAMDEX
CAMDEX stands for CATS based Metal Density
Extraction (CATS stands for Computer Aided
Transcription System)
Metal Density and CAMDEX- Pre-Tapeout layers
density review.(STR/PLY/Metals)
CAMDEX provides die level modeling of mask
layer pattern density and polish thickness
variation
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What is CAMDEX
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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What is CAMDEX
Example:
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
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Metal
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Metal
Diffusion
3/23/2015
EE604 CMOS VLSI LAYOUT DESIGN
3/23/2015
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