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EE604 CMOS VLSI

LAYOUT DESIGN

CHAPTER 3:
PROCESS OF DESIGN
PRINCIPLES

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CHAPTER 3: EE604

3.2
Understand Layout
Hierarchy Concept
and
Advanced Hierarchy

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SYLLABUS
3.2 Understand Layout Hierarchy Concept and
Advanced Hierarchy
3.2.1 Categorize what is the hierarchy
3.2.2 Determine what are the instance arrays
3.2.3 Describe Basic Hierarchy Planning
3.2.4 Compare what is the Design versus
Planning Methodology"
3.2.5 Assess Array cell Layout and Full chip
Roll up
3.2.6 Differentiate basic concepts involved in
signal planning
3.2.7 Evaluate Assembly and Design Change

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3.2.1 Categorize what is the hierarchy

Why Use Hierarchy?

Definitions

Hierarchy - different levels of layout on a ______

Country state county city neighborhood
Chip cluster unit block cell

Instance - a cell placed within _____________

Perak is an instance of a state
Intel is an instance of a corporation

Child Cell - cell contained in larger cell is child of

that cell
Parent Cell - cell containing _____________ is
parent of those cells
Hierarchy organizes & simplifies complexity

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3.2.1 Categorize what is the hierarchy

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Hierarchy Illustrated

Block diagram of hierarchy

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3.2.1 Categorize what is the hierarchy

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Hierarchy Illustrated
Layout representation of hierarchy

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3.2.1 Categorize what is the hierarchy

Schematic and Layout Hierarchy
Hierarchy is usually determined by schematic
design
Hierarchy should make sense ___________
Suggest modifications if necessary

Schematic organization of logic follows layout

design

Schematic and Layout hierarchy should match

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Simplifies use of design and verification tools:

Allows verification to be run at ___________________

Verification runtimes are ________
Easier to get parasitic data back into simulations
Easier to complete ECO (Engineering Change Order)

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3.2.2 Determine what are the instance arrays

What is an Array?
Array - ordered instantiation (placement) of ___________ or
objects in a design
Object can be a cell, group of cells, or other structure
Objects are related, physically and logically
Array can extend in X and/or Y direction
Flipping each alternate instance is the mirror image in X
and/or Y direction of the _____________
Stepping the distance between _____________________
User can specify stepping (counted from origin to origin of
instances)
Row vs column row horizontal, column vertical

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3.2.2 Determine what are the instance arrays

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Stepped cell
The example below shows _______________
instances placed with the same orientation (no
flipping) and same distance between neighbors.
The origin of the instantiated cell is determined
by the small triangle in the lower ___________.
Origin at X:0, Y:0 of child cell

6 X 1 array of the cell circuit

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3.2.2 Determine what are the instance arrays

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Stepped cell with space

This example shows multiple cell instances
placed with the same orientation, without
flipping but with _____________. Notice the
equal distance between each cell.
4 X 1 array of the cell circuit

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3.2.2 Determine what are the instance arrays

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Flipped cell

This example shows multiple cell instances

placed with the same orientation, with _______
and no stepping.

5 X 1 array of the cell circuit

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3.2.3 Describe Basic Hierarchy Planning

Understanding your constraints

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Interface signals
_______________
Metal allocations
_____________

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3.2.3 Describe Basic Hierarchy Planning

Basic Wire Planning

When creating a wire plan, you need to:
Include all the _____ and output pins on your block.
Include all the M2/M3/M4 feed thru to your block.
Include _____________ if needed.
Plan to have two or more power lines in larger-pitch
cells.
Use the standard line pitch for signals and power
lines (unless they are specified differently).
Plan to _________________ when possible.

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3.2.3 Describe Basic Hierarchy Planning

Basic Wire Planning cont.

Keep in mind, when parallel lines are routed at

minimum design rule widths, there is no room to make a
connection to the upper layer due to metal overlap
requirements for the via.
______ making unnecessary jogs in routing (i.e. if a wire
can go straight it should). This will help performance
and area.
Your wire plan specifies the tracks needed for your
over-the-cell routing, in conjunction with your port
definitions.
You need a wire plan to see if your fub will be metallimited and to reserve room for over-the-cell routing.
Make sure this is planned before starting layout.

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3.2.3 Describe Basic Hierarchy Planning

Basic Wire Planning example

Estimate the minimum height required to draw this buffcell block.

Given: - cell pitch = 12um.

- horizontal M2 lines (minimum space = 0.50um)
. in @ metal width = 0.50um
. out @ metal width = 0.80 um
. Power lines @ metal width = 1.0um

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3.2.3 Describe Basic Hierarchy Planning

Basic Wire Planning cont.

Keep in mind, when parallel lines are routed at

minimum design rule widths, there is no room to
make a connection to the upper layer due to metal
overlap requirements for the via.
Avoid making unnecessary jogs in routing (i.e. if a
wire can go straight it should). This will help
performance and area.
Your wire plan specifies the tracks needed for your
over-the-cell routing, in conjunction with your port
definitions.
You need a wire plan to see if your fub will be metallimited and to reserve room for over-the-cell routing.
Make sure this is planned before starting layout.

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3.2.3 Describe Basic Hierarchy Planning

Basic Wire Planning example. Cont.

device legged 12 times

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3.2.3 Describe Basic Hierarchy Planning

Basic Wire Planning cont.

Keep in mind, when parallel lines are routed at

minimum design rule widths, there is no room to
make a connection to the upper layer due to metal
overlap requirements for the via.
Avoid making unnecessary jogs in routing (i.e. if a
wire can go straight it should). This will help
performance and area.
Your wire plan specifies the tracks needed for your
over-the-cell routing, in conjunction with your port
definitions.
You need a wire plan to see if your fub will be metallimited and to reserve room for over-the-cell routing.
Make sure this is planned before starting layout.

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3.2.3 Describe Basic Hierarchy Planning

Block Sizing Fundamentals

The area required by a design is determined by the
number of transistors _______________ or by the
interconnects ________________.

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If device-limited, the area is based on transistor

density. The density is found by multiplying the

number of transistors by the area needed for one
transistor (in sq. mils/device).
If metal-limited, the cells area is determined
by the total number of line pitch.

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3.2.3 Describe Basic Hierarchy Planning

Block Placement Fundamentals

Place blocks efficiently using the __________
of routing. This is especially important for
critical nets.
The Clock driver should be placed close to the
clock input.
If available, use the ______________ as a
template to start placing your blocks.
Utilize track-sharing and use the crossreference file to understand how the blocks
relate to each other.

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3.2.3 Describe Basic Hierarchy Planning

Datapath Definition
Datapath describes layout that has the chips
data buses running through it and being used
in it, in a ___________ fashion.
Data busses are large (up to 86 bits for
floating point), and typically use arrays to
implement the logic; one cell is created, and
then instantiated for each data bit.
Unique inputs and outputs to particular cell
positions (bits) are usually handled with ports.
Making the right connections at the upper
levels is called ____________.

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3.2.3 Describe Basic Hierarchy Planning

Basic Datapath Pitch Planning

In planning a datapath pitch (cell width),
the pitch will usually be determined by the
____________.
It is desirable to match pitches through
different parts of the chip to reuse
common layout (for example, adders).
Pitches usually fall in the range between
25 and 60 microns. Outside these values,
the aspect ratios become inefficient
and/or cumbersome to use.

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3.2.3 Describe Basic Hierarchy Planning

Basic Datapath Pitch Planning cont.

Datapath Pitch Planning Process:
Obtain a cross-reference file for all your
blocks.
Have Wire planning and Cell pitch sizing
ready.
Dont skimp on power line widths.
If the pitch seems too narrow for an efficient
layout, you can always upsize it. Dont go any
smaller than the worst-case pitch.
Be creative.

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3.2.3 Describe Basic Hierarchy Planning

Estimating Layout Time

Plan the layout before __________ the schedule.
Determine your priorities: is getting the job done
quickly or is density* more important for this
project?
_____________is an example of productivity
factor from Wmt project.
The actual number depends on the type of layout
(Datapath vs. Control vs. Ram) and the layout
tools used.
Do not include your planning time here because
Layout and Planning are two different tasks. You
should have a plan ready before you can begin to
estimate the layout time.

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3.2.4 Compare what is the Design versus

Planning Methodology"

Design versus Planning Methodology

Introduction

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In this section we discuss methodologies for

designing and planning at different levels of
hierarchy.
Three methodologies that we will discuss have
industry wide names associated with them.
Top-Down
_____________
Middle-Out

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3.2.4 Compare what is the Design versus

Planning Methodology"

Design versus Planning Methodology

Determine what type of circuitry you have
Datapath Layout
Limited in one dimension by pitch and the
other by area
Random Layout
Limited in both directions by ________
Array
Limited in both directions by ________

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3.2.4 Compare what is the Design versus

Planning Methodology"
Follow these steps while planning a block:
1. How does this block fit into the unit relative to other blocks?
2. What direction should metal levels run?
3. Is there a pitch that must be followed? Almost all datapath
blocks will have a fixed pitch.
4. Is there a template cell or pin ring from the top level plan
available?
5. Is there a pre-determined cell size that is expected to be met?
6. What is the layout of the power network?
7. Clock network - gate alignment requirements/widths/shielding
8. Are there any feedthroughs going through the block?
9. Where are the outputs going to and where are the inputs
coming from?
10. Draw a stick plan of the cell, using all the above information
that has been acquired.

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3.2.4 Compare what is the Design versus

Planning Methodology"

Top-Down Planning
Introduction
In top-down planning, there are three main
areas of focus:
1. signal cross references
2. _______________
3. large block preparation

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3.2.4 Compare what is the Design versus

Planning Methodology"

Top-Down Planning
At the full-chip level, planning occurs
without any knowledge of what the _______
circuitry will look like.
This is done by using output from design tools that use a
High-level Design Language (HDL).

Using the HDL design tools, the chip may

be __________ into different sections with
different circuit functions associated with
each section.

We will call the sections clusters.

Some examples of clusters might be a BUS cluster, an
ALU cluster, or a MEMORY cluster.

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3.2.4 Compare what is the Design versus

Planning Methodology"

Top-Down Planning
Area Estimates Per Device Count

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With these clusters comes device counts and an

estimate for which types of layout will be used for
different functions inside each cluster.
The areas of each cluster may be derived from
the device count output of the HDL tools.
The amount of area taken up by a single device will
depend on which type of layout the device is used
in.

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3.2.4 Compare what is the Design versus

Planning Methodology"

Top-Down Planning
Area Estimates Per Device Count

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There may be many different types of layout that

will effect the device area.
For our purposes, we will use three categories of
layout types:
Array
Datapath
Random Logic

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3.2.4 Compare what is the Design versus

Planning Methodology"

Top-Down Planning
Area Estimates Per Device Count

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Each type of layout has a different device density

factor.
The area is calculated in square mils per device.

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3.2.4 Compare what is the Design versus

Planning Methodology"

Top-Down

Planning

Large Block Preparation

Pin Placement according to full chip

interconnect

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Using the cross-reference files you can determine

the interconnect needed between each of your
blocks. This will determine what size your routing
channel should be between your blocks.

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3.2.4 Compare what is the Design versus

Planning Methodology"

Top-Down Planning
Large Block Preparation (cont.)
Routing Channels
Areas reserved only for signal routing are
called channels.
Routing channels allow adjacent fubs to
have mismatched pin locations.

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3.2.4 Compare what is the Design versus

Planning Methodology"

Top-Down Planning
Overall cell size
M4 Pin Location, size and direction

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Inputs/Outputs to the top level cell

Metal type and width

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3.2.4 Compare what is the Design versus

Planning Methodology"

Bottom-Up Planning
Introduction

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In bottom-up planning the area of focus is on ________

or cell studies (layouts done early in the project).
This planning is used ____ the cluster level planning is
finished.
Repeated structures such as _______, memory arrays
and decoders are sized to help with the final sizing of
each block.

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3.2.4 Compare what is the Design versus

Planning Methodology"

Bottom-Up Planning
Array Cell Layout

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Array Cell layout includes RAM and ROM arrays,

decoders, drivers and any other highly repeated
structures.
Use the same planning process as you would for
datapath planning except arrays are usually done in
PLE. Because these structures are repeated so many
times, it is valuable to get them as small as possible.
Using PLE allows you to use the smaller array design
rules which in turn gives you a smaller cell.
In this situation taking longer to draw something smaller
is better than getting it done faster because of the
amount of area you could save.

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3.2.5 Assess Array cell Layout and

Full chip Roll up

Bottom-Up Planning
Layout of Array Leaf Cell
The array leaf cell will set the pitch in the x and y
direction for the entire array and interfacing cells
Figure 12-4: Array Leaf Cell

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3.2.5 Assess Array cell Layout and

Full chip Roll up

Full Chip Roll-Up

What is a full chip roll-up?
A Full Chip Roll-up is a coordinated checkin of all
data into the iDMS library. This provides the
fullchip planners a __________ of the design to
work with.

How often is a full chip roll-up?

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This event occurs approximately _____ every 3-4

months and more often toward the ______ of the
project, but varies depending on the project.

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3.2.6 Differentiate basic concepts involved

in signal planning

Signal Planning

Introduction

This section discusses the basic concepts

involved in planning inter-block signal flow.
Proper signal planning is essential in minimizing
area. It is also important from an engineering
perspective, as certain critical signals will require
special considerations for speedpath reasons.

Pin Placement from cross-reference files (review)

Parasitic information

Metal Layers
Metal Widths/spacings
Shielding

Channel Routing

When and Why?

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3.2.6 Differentiate basic concepts involved

in signal planning

Signal Planning
Pin Placement
________ cross-reference files are generated from
High-Level Design Language (HDL) tools. These
files are then used to determine block placement in
such a way as to minimize interconnect (which will
minimize routing area).
Once the optimal block placement is determined, the
pins can be assigned to a block edge.
Unless bottom-up layout considerations dictate
otherwise, pins should be placed on block edges to
minimize signal routing distances.

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3.2.6 Differentiate basic concepts involved

Figure 12-7
in signal planning
- An example is shown in Figure 12-6, which shows a
group of signals common to two blocks separated by a
small channel.

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3.2.6 Differentiate basic concepts involved

in signal planning

Parasitic (Resistance/Capacitance)
Considerations
Introduction
Parasitic information is an important aspect of
signal planning. Speed-critical signals identified by
engineering may need to be routed in particular
metal layers and with specific widths. Noisesensitive signals may need to be spaced at certain
distances from other switching signals, or be
shielded from other signals by power (VCC/VSS).
All of these issues should be discussed with the
engineer prior to, during, and after you do any
planning.

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3.2.6 Differentiate basic concepts involved

in signal planning
Parasitic (Resistance/Capacitance)
Considerations
Metal Layers

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Resistance and capacitance (RC) values for

each individual layer need to be taken into
account when planning signal routing, as certain
layers have higher values than others.
Upper metal layers, such as Metal5 and Metal6
would be used mainly for global power and clock
signals, and therefore not available for local
signals without the approval of the unit planner.
For the remainder of this discussion, assume
that these conditions are true.

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3.2.6 Differentiate basic concepts involved

in signal planning

Parasitic (Resistance/Capacitance)
Considerations
Figure 12-9

Figure 12-8

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3.2.6 Differentiate basic concepts involved

in signal planning
Parasitic (Resistance/Capacitance)
Considerations
Metal Widths and Spacings
Introduction
Increasing the ______ of each layer reduces the
resistance over a given length, thus increasing
the _____. The speed critical signals will usually
need to be routed not only in a particular layer or
layers, but also in particular widths determined
by engineering. The width will vary according to
the speed increase required by the signal and
the particular RC values for each layer.

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3.2.6 Differentiate basic concepts involved

in signal planning
Parasitic (Resistance/Capacitance)
Considerations
Signal Necking

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Figure 12-11 (Signal Necking)

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3.2.6 Differentiate basic concepts involved

in signal planning

Parasitic (Resistance/Capacitance)
Considerations
Signal Necking
- Design engineer need to avoid signal necking.
- For critical signal, it might act like a _____. The
broken connection may kill the entire chip.

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3.2.6 Differentiate basic concepts involved

in signal planning

Parasitic (Resistance/Capacitance)
Considerations
Shielding
Shielding is accomplished by ___________
the signal with power (therefore nonswitching) signals (VCC/VSS), either on the
same layer as the signal (lateral shielding) or
adjacent layers (vertical shielding).
Noise-sensitive signals may also be
protected from electrical coupling by
shielding.

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3.2.7 Evaluate Assembly and Design

Change

Assembly
Introduction

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Assembly is an ongoing task. It is performed not

just once, when all sub-block layout is complete, but
at ____________ intervals.
Any block area changes, or block pin changes which
affect channel area, can be identified as early as
possible.
This is important, as any growth in area is more
easily accommodated early in the design process. It
also allows for the fullchip and other unit interfaces
to be __________________.

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3.2.7 Evaluate Assembly and Design

Change

Assembly
Reading in pin rings from actual layout
Top-down pin placements need to match bottom-up
layout. It is extremely important to read in actual
bottom-up pin rings from DLS top level database
whenever they become available.

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This enables pins abutting the blocks to be

adjusted to match (and channels to be rerouted using the new pin locations)

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3.2.7 Evaluate Assembly and Design

Change

Assembly

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It also enables the assembler to feed back

any problems encountered such as . . .

wrong metal layers/widths

missing/extra pins
pin on the wrong edge of the block
block area changes.

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3.2.7 Evaluate Assembly and Design

Change

Assembly
Update Pin Rings for Place and Route blocks
Place and route block pin rings are read in after
each iteration of the place and route tool.

Since the blocks are tool-generated, any unexpected changes

to the original pins or block size must be accommodated by the
assembler, or fixed by the tool the next time the block is run.

Pins along place and route block edges generally

shift each time the tool is run but usually keep their
order; therefore, the pin rings are much more
unstable than those for hand-drawn blocks.
Final iterations of the place and route tools are
often performed late in the design process, when
any pin movements are highly undesirable.

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3.2.7 Evaluate Assembly and Design

Change

Assembly
Routing All Channels
Once all the blocks abutting a channel are read
in and the channel pins adjusted to match the
new pin locations, the channel is re-routed as
described in the Signal Planning section of this
Module.

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If a zipper channel abuts the channel, the zipper

should be routed first to ensure that any zipper
growth can be accommodated within the
channel.

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3.2.7 Evaluate Assembly and Design

Change

Design Changes
Some Sources of Design Changes

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Layout Reviews
______________
Reliability Verification

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3.2.7 Evaluate Assembly and Design

Change

Design Changes
ECOs are changes filed by either _____ OR
the engineer to let everyone know that your
unit or block is changing. These changes
could be because of device size changes,
wire width, spacing or routing needs that
have to be fixed.

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ECO form is filled out by you or your Engineer

Take care of any issues that arise from other units that
your ECO effects
Change layout
Rerun ISS
Page 56
Review changes with engineer

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3.2.7 Evaluate Assembly and Design

Change

Design Changes

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ECO forms are filed in the web based tool called

Tibet.
ECO items that are documented in Tibet:
Priority, Status
Title, Owner
Areas Affected
Model & Stepping
ETA
ECO Reason, Cause, Description, Justification
Approval & AR lists