SIGNAL STRENGTH

Strength of signal

How close it approximates ideal voltage source

VDD and GND rails are strongest 1 and 0

nMOS pass strong 0

pMOS pass strong 1

But degraded or weak 1

But degraded or weak 0

Thus nMOS are best for pull-down network

BASIC LOGIC GATES USING CMOS LOGIC

TRANSISTOR SWITCH MODEL

NFET or n transistor

on when gate H

"good" switch for logic L

"poor" switch for logic H

"pull-down" device
PFET or p transistor

ON when gate L

"good" switch for logic H

"poor" switch for logic L

"pull-up" device

L
ON
when gate=L

OFF
when gate=H
L

ON
when gate=H

OFF
when gate=L
H

SERIES AND PARALLEL

a

nMOS: 1 = ON

pMOS: 0 = ON

Series: both must be ON

Parallel: either can be ON

g1
g2

(a)

g2

OFF

OFF

OFF

ON

ON

OFF

OFF

OFF

(c)

1
b

g2

0
b

g1

(b)

g2

g1

a
g1

0
b

(d)

OFF

ON

ON

ON

ON

ON

ON

OFF

CMOS LOGIC DESIGN

Complementary
transistor
networks
Pullup: p
transistors Inputs

Pulldown - n
transistors

VDD
VDD
Pullup
Network
(p-transistors)

Out

In

Out

Pulldown
Network
(n-transistors)
Gnd
Inverter

Gnd

DESIGN OF CMOS CIRCUITS

All logic is either combinational or sequential

All combinational logic can be implemented
by

nand gates

nor gates

All sequential logic can be implemented by

flip-flops
Flip-flop is back-to-back NAND/NOR Gates
SRAM is basically flip-flop
If I can design a NAND/NOR Gate I can
design any digital system

CONDUCTION COMPLEMENT
Complementary CMOS gates always produce 0 or
1

Ex: NAND gate

Series nMOS: Y=0 when both inputs are 1

Thus Y=1 when either input is 0

Requires parallel pMOS

Rule of Conduction Complements

Pull-up network is complement of pull-down

Parallel -> series, series -> parallel

Y
A
B

COMPOUND GATES

Sketch a static CMOS gate computing Y = (A + B + C) D.

CMOS compound gate for function Y = (A B) + (C D)

 2X1 MUX Implementation using CMOS Logic

 2X1 MUX Implementation using Pseudo-nMOS Logic

 Design a circuit to compute F = AB + CD using NANDs

and NORs.

PASS TRANSISTORS

Transistors can be used as switches

g
s

g
s

PASS TRANSISTORS

Transistors can be used as switches

g=0

g
s

Input g = 1 Output
0
strong 0

g=1
s

d
g=1
s

1
Input

g=0

g
s

g=1

degraded 1
g=0

Output
degraded 0

g=0

strong 1

 Give an expression for the output voltage for the pass transistor networks

shown in Figure 2.35.

 Suppose VDD = 1.2 V and Vt = 0.4 V. Determine Vout in Figure

2.36 for the
following. Neglect the body effect.
a) Vin = 0 V
b) Vin = 0.6 V
c) Vin = 0.9 V
d) Vin = 1.2 V.

EX-OR Gate

T-GATE VS. PASS TRANSISTOR

Twice the number of transistors

Spike compensation between n and p MOS

Zero transmission by NMOS

One transmission by PMOS

TRANSMISSION GATES
Pass transistors produce degraded outputs

Transmission gates pass both 0 and 1 well

Input
g
a

b
gb

b
gb

g = 0, gb = 1
a
b

g = 1, gb = 0
0
strong 0

g = 1, gb = 0
a
b

g = 1, gb = 0
strong 1
1

g
a

g
b

gb

Output

b
gb

TRANSMISSION GATE MUX

Nonrestoring mux uses two transmission gates

Only 4 transistors

S
D0
Y

S
D1
S

TRISTATES

Tristate buffer produces Z when not enabled

EN

EN
Y

EN
Y

A
EN

TRISTATE INVERTER

Tristate inverter produces restored output

Violates conduction complement rule

Because we want a Z output

A
EN
Y
EN

TRISTATE INVERTER

Tristate inverter produces restored output

Violates conduction complement rule

Because we want a Z output

A
EN
Y

EN = 0
Y = 'Z'

EN = 1
Y=A

EN

INVERTING MUX

Inverting multiplexer
Use compound AOI22

Or pair of tristate inverters

Essentially the same thing

Noninverting multiplexer adds an inverter

D0
S

S
D1

D0

D1

Y
S

S
Y

D0

0
Y

S
D1

MULTIPLEXERS

2:1 multiplexer chooses between two inputs

S
S

D1

D0

D0

0
Y

D1

GATE-LEVEL MUX DESIGN

Y = SD1 + SD0 (too many transistors)

How many transistors are needed? 20

D1
S
D0

D1
S
D0

2
4

4:1 MULTIPLEXER

4:1 mux chooses one of 4 inputs using two selects

Two levels of 2:1 muxes

Or four tristates

S1S0 S1S0 S1S0 S1S0

D0
S0
D0

S1

0
D1

D1

0
Y

Y
D2

D3

1
D2

D3

D LATCH
When CLK = 1, latch is transparent

When CLK = 0, the latch is opaque

D flows through to Q like a buffer

Q holds its old value independent of D

a.k.a. transparent latch or level-sensitive latch

CLK
D

Latch

CLK

Q
D
Q

D LATCH DESIGN

Multiplexer chooses D or old Q

CLK
D

CLK

Q
Q

0
CLK

CLK

CLK

D LATCH OPERATION
Q
D

CLK = 1

CLK
D
Q

Q
D

CLK = 0

D FLIP-FLOP
When CLK rises, D is copied to Q

At all other times, Q holds its value

a.k.a. positive edge-triggered flip-flop, masterslave flip-flop

CLK

Flop

CLK

D FLIP-FLOP DESIGN

Built from master and slave D latches

CLK

CLK
CLK

QM

D
CLK
QM

Latch

Latch

CLK

CLK

Q
CLK

CLK

Q
CLK

CLK

D FLIP-FLOP OPERATION
D

QM

CLK = 0

CLK = 1

CLK
D
Q

QM