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Fts 2007
Fts 2007
Fts 2007
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1. (a) How does a feedback briding fault leads the circuit into oscillation. What are
the conditions? [4+4]
(b) What are temporary faults? Differentiate between Transient faults and inter-
mittent faults. Which one is preferrable? [3+2+2+1]
2. (a) A circuit realizes the function.
Z=X1 X4 +X2 X3 +X1 X4
Using Boolean Difference method find the test vectors for SA0, SA1 faults on
all input lines of the circuit.
(b) What are the different properties of Boolean differences? Explain [5+5+6]
3. (a) Construct a seven-bit error correcting code to represent the decimal digit by
augmenting the Excess-3 code and by using add-1 parity check.
(b) Design a redundant circuit for f = a ⊕ b [9+7]
4. (a) What is the mechanism adopted in COPRA a fault Tolerant system. Explain
in detail.
(b) What is meant by Time redundancy? Explain. [4+4+4+4]
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5. (a) What is the need for self checking circuits
(b) Design a totally self checking checker by using reddy’s partition method for
2out of 5 code. [6+10]
6. Explain in detail about fail-safe sequential circuits design with an example. [16]
7. Write a short notes an [4x4=16]
(a) Controllability
(b) Observability
(c) Positive unate function
(d) Syndrom relations of all types of terminating gates.
8. (a) Discuss the sequential circuit design using nonscan techniques.
(b) i. What is meant by Enhanced controllability?
ii. How is a sequential circuit modified for the above sequential circuit and
enhanced controllability? [6+4+6]
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so that it becomes hazard free?
Figure 1:
3. (a) Analyze the circuit shown in fig2 below for static hazards. Redesign the circuit
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7. Explain the technique for designing minimally testable network which produces a
circuit which can be tested by three tests only.Modify the function f = A BC +A
B C into a circuit which has only three tests. [10+6]
8. (a) Draw the logic diagram of Hazard-free polarity hold latch, and explain with
[16]
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2. (a) What is a tree like circuit. Give properties of tree like circuits.
(b) For the given tree like circuit find the complete test set using path sensitizing
method as show in figure1. [3+5+8]
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3. (a) Explain fail soft-operation.
Figure 1:
(b) Explain the 5 MR reconfiguration mechanism and also explain how it care
tolerate single, double and Trible faults in a given system.
6. Explain in detail about fail-safe sequential circuits design with an example. [16]
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8. (a) Draw the logic diagram of Built-in Logic Block Observer.
(b) Discuss BILBO based BIST architecture. [8+8]
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4. (a) What is the goal of “pluibus” system used in ARPA network. Explain its
working.
(b) What is ment by fail soft operation? What should a system have to achieve
the capability of fail soft operation. [4+4+4+4]
5. Design a totally
(a) self-checking circuit for m out of n codes by translating the code to 1 out of 2.
(b) Verify it for 3 out of 5 code. [8+8]
6. (a) Explain the design consideration of self checking PLA considering stray faults
with suitable example.
(b) How do you implement strong fault service for the functional PLA. [8+8]
7. (a) Prove that five tests are sufficient to detect all faults in a combinational logic
circuit by inserting addition control logic to the following function, obtain the
test pattern.
f=(A,B,C,D)=AB+BC+BD
(b) Obtain the ten sequences denoted as P = {xo x1 ......xa } from the basic module
of the above circuit and get the compatable pair from the set P. [8+8]
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