Purushottam Institute of Engineering & Technology

Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

EXPERIMENT NO.: 06
AIM OF THE EXPERIMENT:
Design a schematic and simple layout for CMOS
Inverter, parasitic extraction and simulation.

REQUIREMENTS:

1. Computer
2. Tanner Tools

Prerequisites:
Layout Design in L-Edit (expt. No. 5)

Theory:

Static CMOS NAND Gate

Stick Diagram of NAND Gate

Instruction Sheet for VLSI Design Lab

Prepared by Debashish Mohapatra, Lecturer, AEIE Dept

Instrumentation Systems Design Laboratory

Page 1 of 5

Purushottam Institute of Engineering & Technology

Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

Layout of NAND:

Instruction Sheet for VLSI Design Lab

Prepared by Debashish Mohapatra, Lecturer, AEIE Dept

Instrumentation Systems Design Laboratory

Page 2 of 5

Purushottam Institute of Engineering & Technology

Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

Spice Netlist of NAND for Simulation:

Cpar1 Vdd 0 C=15.93186f
Cpar2 Gnd 0 C=8.9820675f
Cpar3 Out 0 C=13.300315f
M1 Vdd InB Out Vdd PMOS L=700n W=1.75u AD=6.2475p PD=10.5u
AS=4.808125p PS=7.175u $ (8.5 40.5 10.5 45.5)
M2 Out InA Vdd Vdd PMOS L=700n W=1.75u AD=4.808125p PD=7.175u
AS=6.2475p PS=10.5u $ (-8 40.5 -6 45.5)
M3 Out InB 6 Gnd NMOS L=700n W=1.75u AD=6.2475p PD=10.5u
AS=4.440625p PS=6.825u $ (8.5 9 10.5 14)
M4 6 InA Gnd Gnd NMOS L=700n W=1.75u AD=4.440625p PD=6.825u
AS=6.2475p PS=10.5u $ (-8 9 -6 14)
.model nmos nmos level=1
.model pmos pmos level=1
v1 vdd gnd dc 5
*Definition of the voltage source, vdd
VinA InA Gnd PULSE (0 5 0 .2n .3n 4n 8n)
VinB InB Gnd PULSE (0 5 0 .2n .3n 8n 16n)
* Definition of the Pulse voltage source at the input node of the inverter
.tran 1n 80n
* the command to perform a transient analysis starting from 1ns till 40ns.
.print tran v(out) v(inA) V(inB)
* To print the result (i.e. the Output and the Input voltage)in a graphical form
.END

Instruction Sheet for VLSI Design Lab

Prepared by Debashish Mohapatra, Lecturer, AEIE Dept

Instrumentation Systems Design Laboratory

Page 3 of 5

Purushottam Institute of Engineering & Technology

Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

Simulated Waveforms of 2-input NAND Gate:

Instruction Sheet for VLSI Design Lab

Prepared by Debashish Mohapatra, Lecturer, AEIE Dept

Instrumentation Systems Design Laboratory

Page 4 of 5

Purushottam Institute of Engineering & Technology

Purushottam Vihar, Mandiakudar, Rourkela-770034

Department of Applied Electronics & Instrumentation Engineering

Instruction Sheet for VLSI Design Lab

Prepared by Debashish Mohapatra, Lecturer, AEIE Dept

Instrumentation Systems Design Laboratory

Page 5 of 5