Professional Documents
Culture Documents
ALU Design
ALU Design
CPU
Datapath
ALU
Regs
Control
Shifter
Nand
Gate
Design Refinement
Informal System Requirement
Initial Specification
Intermediate Specification
refinement
increasing level of detail
Final Architectural Description
Design as Search
Problem A
Strategy 1
SubProb 1
BB1
BB2
Strategy 2
SubProb2
SubProb3
BB3
BBn
"VHDL Behavior"
16
A
Co
ALU
3
M
mode/function
Cin
S
16
ECE468 ALU design
top
down
bottom
up
mux design
meets at TT
Circuit Diagrams
Gate Count
Delay
[Package Count]
Pin Out
ECE468 ALU design
Logic Levels
Power
Fan-in/Fan-out
Cost
Design time
Adapted from VC and UCB
Binary
0000
0001
0010
0011
Decimal
4
5
6
7
Binary
0100
0101
0110
0111
Examples:
3+2=5
3+3=6
1
Decimal
0
1
2
3
4
5
6
7
8
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
Decimal
0
-1
-2
-3
-4
-5
-6
-7
-8
Bitwise
Inverse
1111
1110
1101
1100
1011
1010
1001
1000
0111
2s Complement
0000
1111
1110
1101
1100
1011
1010
1001
1000
Binary
0000
0001
0010
0011
0100
0101
0110
0111
Decimal
0
-1
-2
-3
-4
-5
-6
-7
-8
Examples: 7 - 6 = 7 + (- 6) = 1
1
2s Complement
0000
1111
1110
1101
1100
1011
1010
1001
1000
3 - 5 = 3 + (- 5) = -2
Zero
ALU
Result
Overflow
N
CarryOut
Function
000
001
And
Or
010
110
Add
Subtract
111
Set-on-less-than
CarryIn
A
Mux
Result
1-bit
Full
Adder
CarryOut
Adapted from VC and UCB
CarryIn
A
1-bit
Full
Adder
CarryOut
Truth Table:
Inputs
Outputs
CarryIn
CarryOut
Sum
Comments
0 + 0 + 0 = 00
0 + 0 + 1 = 01
0 + 1 + 0 = 01
0 + 1 + 1 = 10
1 + 0 + 0 = 01
1 + 0 + 1 = 10
1 + 1 + 0 = 10
1 + 1 + 1 = 11
Outputs
CarryIn
CarryOut
Sum
Comments
0 + 0 + 0 = 00
0 + 0 + 1 = 01
0 + 1 + 0 = 01
0 + 1 + 1 = 10
1 + 0 + 0 = 01
1 + 0 + 1 = 10
1 + 1 + 0 = 10
1 + 1 + 1 = 11
CarryOut = (!A & B & CarryIn) | (A & !B & CarryIn) | (A & B & !CarryIn)
| (A & B & CarryIn)
CarryOut = B & CarryIn | A & CarryIn | A & B
Adapted from VC and UCB
Outputs
CarryIn
CarryOut
Sum
Comments
0 + 0 + 0 = 00
0 + 0 + 1 = 01
0 + 1 + 0 = 01
0 + 1 + 1 = 10
1 + 0 + 0 = 01
1 + 0 + 1 = 10
1 + 1 + 0 = 10
1 + 1 + 1 = 11
Sum = (!A & !B & CarryIn) | (!A & B & !CarryIn) | (A & !B & !CarryIn)
| (A & B & CarryIn)
Sum = (!A & !B & CarryIn) | (!A & B & !CarryIn) | (A & !B & !CarryIn)
| (A & B & CarryIn)
Sum = A XOR B XOR CarryIn
Truth Table for XOR:
X XOR Y
0
0
1
1
0
1
0
1
0
1
1
0
CarryOut
Sum
A 4-bit ALU
1-bit ALU
4-bit ALU
CarryIn0
CarryIn
A0
A
B0
A1
Mux
Result
B1
A2
B2
1-bit
Full
Adder
A3
B3
1-bit
Result0
ALU
CarryIn1 CarryOut0
1-bit
Result1
ALU
CarryIn2 CarryOut1
1-bit
Result2
ALU
CarryIn3 CarryOut2
1-bit
ALU
CarryOut
Result3
CarryOut3
Adapted from VC and UCB
A
4
1
4 !B
ECE468 ALU design
ALU
2x1 Mux
Sel
0
Zero
4
Result
4
CarryOut
Adapted from VC and UCB
Overflow
Decimal
0
1
2
3
4
5
6
7
Binary
0000
0001
0010
0011
0100
0101
0110
0111
Decimal
0
-1
-2
-3
-4
-5
-6
-7
-8
2s Complement
0000
1111
1110
1101
1100
1011
1010
1001
1000
-4 - 5 = -9
7
3
-6
but ...
-4
-5
Overflow Detection
Overflow: the result is too large (or too small) to represent properly
Example: - 8 < = 4-bit binary number <= 7
When adding operands with different signs, overflow cannot occur!
Overflow occurs when adding:
2 positive numbers and the sum is negative
2 negative numbers and the sum is positive
Homework exercise: Prove you can detect overflow by:
Carry into MSB ! = Carry out of MSB
7
3
-6
0
1
-4
-5
1-bit
Result0
ALU
CarryIn1 CarryOut0
1-bit
Result1
ALU
CarryIn2 CarryOut1
A2
1-bit
ALU
B2
A3
B3
X XOR Y
0
0
1
1
0
1
0
1
0
1
1
0
Result2
CarryIn3
1-bit
ALU
Overflow
Result3
CarryOut3
Adapted from VC and UCB
Result0
1-bit
ALU
CarryIn1 CarryOut0
Result1
1-bit
ALU
CarryIn2 CarryOut1
Result2
1-bit
Zero
ALU
CarryIn3 CarryOut2
Result3
1-bit
ALU
CarryOut3
1-bit
Result0
ALU
CarryIn1 CarryOut0
CarryIn
1-bit
Result1
ALU
CarryIn2 CarryOut1
1-bit
Result2
ALU
CarryIn3 CarryOut2
A3
B3
1-bit
ALU
CarryOut
Result3
CarryOut3
Adapted from VC and UCB
A[3:0]
CarryIn
4
ALU
Result[3:0]
ALU
Result[7:4]
B[3:0]
4
A[7:4]
4
4
B[7:4]
4
CarryOut
CarryIn
4
ALU
Result[3:0]
4
B[3:0]
A[7:4]
B[7:4]
A[7:4]
C0
ALU
Y[7:4]
4
1 Sel
C4
C4
Sel
2 to 1 MUX
ALU
X[7:4]
Result[7:4]
4
B[7:4]
4
0
2 to 1 MUX
C1
CarryOut
Adapted from VC and UCB
Cout0
Cout1
1-bit
ALU
Cin1
Cin2
B0 A0
1-bit
ALU
Cin0
gi = Ai & Bi
pi = Ai or Bi
Adapted from VC and UCB
gi = Ai & Bi
pi = Ai or Bi
We can rewrite:
Cin1 = g0 | (p0 & Cin0)
Cin2 = g1 | (p1 & g0) | (p1 & p0 & Cin0)
Cin3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & Cin0)
Carry going into bit 3 is 1 if
We generate a carry at bit 2 (g2)
Or we generate a carry at bit 1 (g1) and
bit 2 allows it to propagate (p2 & g1)
Or we generate a carry at bit 0 (g0) and
bit 1 as well as bit 2 allows it to propagate (p2 & p1 & g0)
Or we have a carry input at bit 0 (Cin0) and
bit 0, 1, and 2 all allow it to propagate (p2 & p1 & p0 & Cin0)
Adapted from VC and UCB
8-bit Carry
Lookahead
Adder
Result[31:24]
Result[23:16]
A[7:0]
B[7:0]
8
C8
8-bit Carry
Lookahead
Adder
C0
8
Result[7:0]
Adapted from VC and UCB
Summary