Professional Documents
Culture Documents
Cmos Design Objective Questions
Cmos Design Objective Questions
Cmos Design Objective Questions
1.
Which of the material used as gate
[
]
a). photoresistive
b). polysilicon c). metal
d). glass
2.
The ---------- of the VLSI chip ranges from pre-assembly wafer preparation to
fabrication
techniques
for the packages that provide electrical connections and mechanical and
environmental
protection [
]
3.
------------------ is the electrical consideration for VLSI packages [
]
a) low ground resistance . b) short signal leads c) minimum power supply spiking d)
All
4.
A MOS transistor which has conducting channel region at zero gate bias is called [
]
a) Depletion mode b) Enhancement mode c) Saturated mode d) Non- saturated
mode
5.
If packing density area and performance are the constraints, power dissipation is not
a constraint, the
technology you prefer [
]
a).BJT
b) CMOS
c). NMOS
d). PMOS
6.
The speed of the CMOS logic is less, when compared to other technologies due to [
]
a) High noise immunity
b) High input capacitance
c) High driven current d) All
A. sink current is obtained under which condition.
[
]
a) TTL
b) DTL
c) ECL
d) All the above
9.
The partial current flowing through p and n channels is called [
]
a) Voltage spikes
b) current spikes
c) both a and b
d) none of the above
10. -------------- is the non-saturated digital logic family [ ]
a) TTL
b) ECL
c) MOS d) RTL
a) RTC
b) DTL c) TTL
d) ECL
MOS circuits are formed from the following basic layers ________
The layers of the MOS circuits are isolated from each other by _______
3.When Polysilicon and thinox regions cross each other forms
__________
Green colour is used in Stick diagrams in NMOS design for _________
Red colour is used in stick diagrams in NMOS design for _________
Blue colour is used in stick diagrams in NMOS design for _________
Brown colour is used in stick diagrams in NMOS design for _________
In 2M CMOS design rules for Bi cmos buried n-sub collector is _______
In 2M CMOS design rules for Bi cmos p-base the colour is _______
Scaling means to _________the feature size and to achieve _____pcircuitry chip
1/ is used as scaling factor _______
Gate area Ag is scaled by __________
gate capacitance per Unit area is scaled by ______
Gate capacitance Cg is given by the equation______
Parastic capacitance is proportional to ________
The intrinsic and extrinsic delay of submicron logic circuits [ ]
What is the color code of metal-I ? [ ]
What is the colour code of n-diffusion? [ ]
What is the colour code of p-well? [ ]
----------------- is required to connect two metal lines
Switch logic is based on ___________
Gate logic is based on _____________
For the 4X4 bit barrel shifter, the regularity factor is given by
8 b . 4 c . 2 d 16
The level of any particular design can be measured by
SNR b .Ratio of amplitudes c. regularity d. quality
In tackling the design of system the more significant property is
NOR
A CMOS PLA is realized by
pseudo nmos NOR gate
CMOS NOR gate
pseudo nmos NAND gate
CMOS NAND gate
The mapping of irregular combinational logic functions into regular
structures is provided by the
FPGA
CPCD
standard cells
PLA
The general arrangement of PLA is
AND/OR structure
OR/AND structure
NAND/NOR structure
EX-OR/OR structure
V XP X Z PLA represents as
V-no.of input variables P-no.of output functions Z-no.of gates
V-no.of gates P-no.of OR gates Z- no.of AND gates
V-no.of input variables P-no.of product terms Z-no.of output
functions
Theadvantageofprechargeevaluatelogicis___________.
Standardcellscanbeplaced___________onsiliconchip.
DRAMiswidelyusedbecause___________
Predesignedlogiccellsareknownas___________
StandardcellareasinCBICarea___________
Powerbussesarealsoknownas___________
Interconnectionsare___________inFPGA.
Devicesizesingatearrayare___________.
Thesmallsquaresontheedgeofthecellareraisedfor___________
Connectingdatapathelementtoformadatapathresultsin___________and
___________layoutthanusingstandardcells
Crosstalkresultsfrom___________
Siliconcircuitryisconnectedtooutsideworldby___________
LUTisusedin___________
InfullcustomASICdesignallthelayersare___________
FPGAisa___________
PALandPLAareknownas___________
Theoutputofaphysicaldesignis___________
INaPLA___________areprogrammable
ThesizeofanICisgenerallymeasuredby___________
CLBareusedIn___________
Theexampleofphysicaldefectis___________
___________technologyisnotusedinFPGA.
TheimportantdesignpointsaboutSOCare___________.
Designqualityofchipismeasuredon___________
Theexampleofelectricalfaultis___________
Inapostsiliconvalidationtestingisdoneon___________
Instructuredgatearray___________iscustomized?
Theobjectivesoffloorplanningare___________
SomeVLSItestproceduresusedare___________
Toincreaseobservabilitytechniquesusedare___________
TypicalmanufacturingdefectsinICfabricationare___________
Logicalfaultsgeneratedbyelectricalfaultsare___________
___________isnousedfortestingofcombinationallogic.
Timingfailureresultingfromdelayfaultsarisesdueto___________
Thedisadvantageofthescanbasedtechniquesare___________
Boundaryscantechniquesusedfor___________
Thescanbasedtechnique___________israceandhazardfree.
SignatureanalysisisusedIn___________
BISTtechniquessuffersfrom___________
InaBISTtechniqueORAandPSBRGuses___________