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07 Chapter2
07 Chapter2
CHAPTER 2
ARCHITECTURES OF OPERATIONAL
TRANSCONDUCTANCE AMPLIFIER
2.1
INTRODUCTION
Operational Transconductance Amplifier (OTA) is an integral part
of many analog and mixed signal systems. The topology of OTAs plays a
critical role in the design of low power system. The design of OTA continues
to pose challenge as the supply voltage and transistor channel length scale
down with each newer generation of CMOS technologies. The OTA is the
versatile building block of any analog processing system. Designing these
building blocks in terms of gain, power consumption and gain bandwidth
product efficiently is still a challenging task. Operational Transconductance
Amplifiers are mainly classified into Single ended output OTAs and
Differential ended output or Fully Differential OTAs.
In this chapter, various single ended and fully differential OTAs
available in the literature are discussed and their performances are compared
with each other. Under single ended structures, telescopic and folded cascode
OTA architectures with Wilson and Cascode current mirror load are
described. In fully differential category, two stage OTA and gain boosted
OTA are detailed along with telescopic and folded cascode OTAs. The fully
differential OTAs have several advantages over single-ended output OTAs
such as a stable input common mode voltage, reduced harmonic distortion,
doubling of the output voltage swing and suppression of coupled noise due to
14
substrate and power lines. Hence, in this work, a high performance CMOS
fully differential OTA has been proposed using the folded cascode
architecture to achieve high gain, high output swing and a good slew rate. The
proposed OTA structures use an NMOS transistor in its input differential
stage to achieve high transconductance gain. The Selection criterion is
based on various parameters like transconductance gm, DC gain, gain
bandwidth product (GBW), Common Mode Rejection Ratio (CMRR) and
average power.
Signal processing system contains one or more analog
continuous time filters that are used in a wide range of applications. Low
pass filters act as an important signal processing element in any analogue
base band circuitry. These filters are specifically very useful in continuous
time filtering. In recent years, Gm-C filters have evolved as a suitable
processing element in low power and high frequency operations. A second
order Butterworth Gm-C low pass filter is used as a channel selection
filter in the wireless communication receiver. The proposed OTA structure
is implemented in a second order Butterworth Gm-C Low pass filter
because of its ability to operate at low supply voltage and power over a
wide tuning range.
2.2
LITERATURE SURVEY
Currently research studies are focussing on designing high
15
for a two stage OTA and its alternative structures are discussed. This gives
insight into improving performance parameters like voltage gain, Common
mode rejection ratio and Power supply rejection ratio etc. However, the
design considerations for the fully differential circuits have not been detailed
in it. The basic architectures of various single ended and fully differential
structures are described along with their design complexities, limitations and
disadvantages by Gregorian and Razavi (1999). This helps in choosing a
specific category of OTA for a particular application. It also details about the
various advantages of fully differential structure over the single ended
structures. Hernes and Sansen (2005) discuss the classification of single stage,
two stage and three stage structures based on harmonic distortion. A
performance comparison of single stage amplifier and two stage amplifier
shows that single stage amplifier works well at high frequency while two
stage amplifier is good at mid frequency range. The study also assures that
noise level is maintained low for differential amplifiers with an increasing in
common mode rejection ratio and power supply rejection ratio. The input
stage transistors affect the overall operation of a circuit at high frequencies
and output transistors at low frequencies. Thus, the choice of transistor made
at the input and output stage also decides the amount of nonlinearity present
in the circuit. Jakbson et al (1992) give a clear explanation about flicker (1/f)
noise in MOS transistors. The usage of p-channel transistors as the input
differential stage in an amplifier reduces the third order and total harmonic
distortion. This enhances the choice of OTA, based not only on gain and gain
bandwidth product but also on noise performance. A two-stage OTA for
digital audio applications is designed by Dessouky and Kaiser (2001). This
OTA is used in delta sigma modulator, where the first stage is a folded
cascode stage and the second stage is a common source amplifier. There is a
limitation on slew rate in both the stages. Furthermore, there is an increase in
16
power dissipation as large bias current is drawn from the second stage due to
large load capacitance. This inhibits the use of OTA in low power
applications.
A two-stage class A/AB OTA is discussed in Brandt et al (1991)
which comprises of the differential pair at the first stage and active current
mirrors with class AB operation at the second stage. The class AB operation
does not limit the slew rate that often happens to the class A stage. So, there is
no trade off between static power consumption and slew rate in class AB
OTA when the large input signal is applied. This OTA is also present in the
delta sigma modulator which is being used in audio applications. It again uses
miller compensation for stability and cascode compensation for improved
amplifier bandwidth and better slew rate. Thus, multistage amplifiers are
preferred for very high mid band gain. However, each stage adds a new pole
which requires additional compensation in frequency. This results in
increased power consumption as the circuit draws a large amount of current.
The two stage operational transconductance amplifier described by Behzad
Razavi (2002) achieves high gain and voltage swing due to the presence of
two stages in the circuit. This helps in obtaining good signal to noise ratio and
dynamic range. However, this amplifier also requires a miller compensation
to maintain stability, which reduces unity gain bandwidth and speed. Yet
again, the power consumption is increased due to increased area. So, single
stage amplifiers are the best choice to work in reduced voltage and power
circuits.
Houda et al (2006) designed the single stage Telescopic OTA
structure which proves to achieve high gain and unity gain bandwidth. But,
the structure attains less output voltage swing and the input common mode
level should be maintained to match the output common mode level. This
17
OTA FUNDAMENTALS
The OTA is a transconductance device in which the input voltage
V )
(2.1)
18
V+
Io +
+
Io
gm
V-
Io -
Performance Parameters
There are various parameters to validate the performance of the
OTA. The important parameters that help in the designing of OTA are gain,
slew rate, power dissipation, common mode rejection ratio, power supply
rejection ratio and harmonic distortion. The performance of an OTA is
classified based on time domain and frequency domain parameters as given
by Phillip and Holberg (2002). The frequency domain parameters are
bandwidth, quality factor, gain, and phase. Slew rate is an important
parameter that influences the circuit design in its time and frequency domain.
19
Slew rate
Slew rate (SR) defines the fastest possible rate of change of OTAs
output voltage, whose rate of change is limited due to the electronic circuitry
inside the OTA. It supplies small current to charge and discharge the
capacitor C.
The capacitor charge Q is calculated by integrating the current
i = gm (v+-v-) = gmvin Q = v C =
g v dt =
i dt
(2.2)
(2.3)
(2.4)
V0 .
Thus,
|
= SR =
(2.5)
where
i|
(2.6)
= gm/C is the unity gain frequency. The above equation shows that
20
Gain
The gain is a measure of the ability of an amplifier to increase the
power or amplitude of a signal from the input to the output. It is usually
defined as the mean ratio of the signal output of a system to the signal input of
the same system. It may also be defined on a logarithmic scale, in terms of the
decimal logarithm of the same ratio (dB gain). DC gain can be improved by
increasing the transconductance of the input transistors or the output
impedance. The open loop gain of an amplifier determines the precision of the
feedback system. A high open loop gain is necessary to suppress nonlinearity.
Circuit setup for calculation of open loop gain is given in the Figure 2.2. The
open loop gain is given by Equation (2.7)
A (dB) = 20log
(2.7)
Vdd
Vi +
gm
Vi -
Vo+
+
Vo-
CL
CL
Vss
21
it is easy to calculate the total dissipation and then subtract the load
dissipation to obtain the device dissipation. When the load capacitance is
increased, both the slew rate and the unity gain frequency of the OTA circuit
are reduced. To maintain a constant settling behavior, the power consumption
of the OTA must be increased linearly with an increase in the load
capacitance.
Common Mode Rejection Ratio (CMRR)
The relative sensitivity of an OTA to a difference signal as
compared to a common mode signal is called common mode rejection ratio
(CMRR) and is the figure of merit of the differential amplifier. CMRR is
given by
CMRR =
A
A
(2.8)
Where ADM is the differential mode gain and ACM is the common mode gain.
Ideally ADM should be large and ACM should be zero. The higher the value of
CMRR, better is the performance of OTA. Ideally, changes in the common
mode input should have no effect on the differential gain of the amplifier. As
it is practically not possible, Common-Mode Rejection Ratio is defined as the
ratio of differential mode gain to common mode gain. The circuit setup for
calculation of Common-Mode Rejection Ratio (CMRR) is given in
Figure 2.3.
22
Vdd
Vi +
gm
Vi -
Vo+
+
Vo-
CL
CL
Vss
+
-
VCM
( )
( )
dB
(2.9)
If the OTA involves two power supplies namely positive power supply V DD
and negative power supply VSS, a power supply gain for each power node can
be defined separately. In this case Ap, Vdd (Ap, Vss) is called the transfer
23
function from the Vdd (Vss) node to the output node where by the Vss (Vdd) is
ac grounded. The PSRR of each power supply can be defined as
PSRR, Vdd =
and
PSRR, Vss =
(2.10)
Vdd
+
Vi +
gm
Vi -
Vo+
+
Vo -
CL
CL
Vss
+
VSS
24
the unity-gain frequency, fu, which exceeds 1GHz in today CMOS OTAs.
The 3-dB frequency, f3-dB, may also be specified to allow easier prediction of
closed loop frequency response.
20 log(AV)
f 3-dB
fu
f (log scale)
(2.11)
Where Vf is the amplitude of the fundamental and Vhi is the amplitude of the
ith harmonic component.THD is presented as a percentage value.
25
(2.12)
where HD1 and HD3, are the amplitudes of the fundamental and thirdharmonic terms respectively.
DIFFERENTIAL
TWO-STAGE
TRANSCONDUCTANCE
AMPLIFIER
The differential two stage transconductance amplifier shown in
Figure 2.6 is formed by differential cascade pair transistors M1 and M2 as the
first stage and common source amplifier as the second stage as in Shailesh
and Khalid (2008). Since two transistors are present at the output, the
presence of two stages helps the circuit to attain high gain and high dynamic
range. This in turn helps the OTA to achieve good SNR at low power supply
voltages. The simulation result of the two-stage OTA achieves a
transconductance of 2.07 ms and open loop DC gain of 85.69 dB.
26
VDD
M3
M4
Vb2
M8
M6
Rz
Vout+
Rz
Cc
Vout-
Cc
V+
M1
M2
V-
Vb1
M9
M5
M7
Values
Vdd (V)
3.3
Channel Length ( m)
0.35
RZ (k )
CC (pF)
0.1
W1,2
m)
20
W3,4
m)
W5
W6,8
m)
m)
10
W7,9 ( m)
Vb1 (mV)
500
Vb2 (mV)
233.6
27
Since two stages are present, the stability of the OTA is maintained
using a compensation capacitor (Cc) and a resistor (Rz) or a MOSFET during
feedback operation. This reduces the unity gain bandwidth and the speed of
operation. Also, the structure requires two Common Mode Feedback (CMFB)
Circuits vb1, vb2 for the four current branches M3, M4, M5, M7 and M9
present in the circuit. Hence, the power consumption of the OTA increases
with a increase in area. This inhibits the performance of the two stage OTA.
In order to achieve high gain and large bandwidth with less power
consumption, the telescopic topologies are used in building OTA.
2.5
Cascode current mirror and Wilson current mirror. Input transistors M1 and
M2 acts as a voltage to current converters and converts applied input voltage
to output current. The transistors M5, M6, M7 and M8 form a Cascode/
Wilson current mirror (John and Martin 1997) load as shown in Figure 2.7
while a biasing current Ibias is used to bias the transistors M9 and M10, a bias
voltage V1 is used to bias the transistors M3 and M4. (Houda et al 2006).
VDD
VDD
M7
M8
M7
M8
M5
M6
M5
M6
Vout
Vout
IBIAS
IBIAS
CL
M3
CL
M4
M3
M4
V1
V+
V1
M1
M10
M2
V-
M9
VSS
V+
M1
M10
M2
V-
M9
VSS
28
The operation of the circuit requires only two current branches and
thus, the power consumption is improved. The slew rate depends upon the
bias currents and the output load capacitance and is better than the two stage
amplifier. The cascode device in the circuit helps to achieve high gain and
reduces the noise contributed by the bias transistors. The circuit gain is given as
Av = g
where g
and g
[ (g
r ) (g
r )]
(2.13)
29
single ended structure but for the addition of the M11 and M12 transistors, as
shown in Figure 2.8. The advantages of fully differential OTAs over singleended designs are stable input common mode voltage, reduction of harmonic
distortion, doubling of output voltage swing, and suppression of coupled noise
due to substrate and power lines. The slew rate is better than the two stage
amplifier proposed by Shailesh and Khalid (2008).
In the telescopic cascode OTA, the main source of noise is due to
the input transistors M1 and M2 and the bias transistors M6 and M8.
However, the effect of noise is minimized through the cascode devices, since
the devices help the circuit to obtain high gain. There are only two current
branches M11 and M12, (Behzad Razavi 2002) which substantially improve
the power consumption. The main disadvantage of this design is that the
output swing is low and input common mode level has to be set accurately to
match with the output common mode level. When the common mode level
voltages decrease, it affects OTAs linear range of operation.
30
VDD
M7
M8
M11
M5
M6
M12
Vout-
Vout+
CL
CL
M3
Ibias
M4
Vbias
V+
M10
M1
Ibias
M2
V-
M9
VSS
31
Values
CL (pF)
0.1
Ibias ( A)
15
Vdd/Vss (V)
Channel Length ( m)
W1,2
35
m)
W3,4,9,10
W5,6,7,8
W11,12
m)
m)
m)
Vbias (mV)
6
18
33.5
600
32
mirror has a limited output swing. So, the OTA circuit has been modified to
improve the output swing using a Cascode current mirror. In a folded cascode
OTA using a Wilson current mirror, the maximum output voltage was set to a
value lower than: Vdd+VT+2Vds,sat. Thus, in order to restore this fall to
+2Vds,sat, a cascode current mirror is used. The folded Cascode OTA with
Wilson and Cascode current mirror is shown in Figure 2.9. The folded
cascode OTA has a PMOS differential input stage with transistors M9 and
M10 to charge the Wilson/Cascode current mirror transistors M1-M4.
Transistors M11 and M12 provide the DC bias voltages to M5, M6, M7, M8
transistors (Houda et al 2006).
The open-loop voltage gain is given by the equation
Av = g
{[(g
where g
+g
,g
and g
)r (r llr )] (g
)r r ]}
+g
(2.14)
and
respectively. The
VDD
M1
M2
M3
V-
M9
M10
M1
M2
M3
M4
Ibias
Ibias
M4
V+
Vout
Ibias
V-
M9
M10
V+
Vout
CL
M5
M6
M5
M6
M11
M7
Ibias
CL
M8
M11
M7
M8
M12
VSS
M12
VSS
33
The specifications of the circuit are as in Table 2.4. The open loop
DC gain of single stage single ended folded cascode OTA with Wilson
current mirror load is 84 dB and unity gain bandwidth is 84.02 dB MHz. A
transconductance of 102.9
CMRR and PSRR values found to be 187.5 dB and of 104 dB are achieved
using a Wilson current mirror in the folded cascode OTA.
Table 2.4 Design Parameters of Single Ended Folded Cascode OTA
Parameters
Values
CL (pF)
0.1
Ibias ( A)
30
Vdd/Vss (V)
Channel Length ( m)
W1,2,3,4
18
m)
W5,6,7,8,11,12
m)
W9,10 ( m)
6
35
S of
by its input stage. Mobility of NMOS device is always greater than that of
PMOS device and the PMOS input differential pair has a lower
34
M1
M2
M12
M3
Vout+
M4
Vout-
V1
CL
V+
M9
M10
Ibias
CL
M5
V-
M6
Ibias
V2
M7
M8
M11
VSS
35
(2.15)
GBW =
(2.16)
Where, gm4, gm6 and gm9 are the transconductance of transistors M4, M6 and
M9 respectively. ID is the bias current flowing through transistors M9, M4,
and M6 and CL is the output node capacitance.
and
(2.17)
36
Values
CL (pF)
0.1
Ibias ( A)
69
Vdd/Vss (V)
Channel Length ( m)
W1,2,12
m)
W3,4
m)
W5,6,7,8
m)
10.8
5.4
2
W9,10 ( m)
14
W11
m)
V1 = V2 (mV)
318
37
VDD
M1
M2
Ibias1
M15
M3
V+
M9
M10
M4
V-
M16
Vout+
Vout-
CL
M14
M11
M13
M12
M5
M6
M7
M8
CL
Ibias2
VSS
CMRR +
(2.18)
38
where
PSRR +
(2.19)
where
The open-loop voltage gain and gain bandwidth product are given
in Equation (2.20) and Equation (2.21) respectively
A =g
(g
r r
r (r
r ))
(2.20)
GBW =
(2.21)
where, gm3, gm5 and gm9 are respectively the transconductance of transistors
M3, M5 and M9. The drain to source resistances of transistors M1, M3, M5,
M7 and M9 are r01, r03, r05, r07 and r09 respectively. CL is the capacitance at the
output node.
The power-supply rejection ratio (PSRR) is expressed as:
PSSR =
)(
(
=R r g
=r g
(R
)
)
(2.22)
(2.23)
+r )
(2.24)
= r
(2.25)
=r r g
(2.26)
39
(2.27)
Values
CL (pF)
0.1
Ibias1 ( A)
60
Ibias2 ( A)
90
Vdd/Vss (V)
1.8
Channel Length ( m)
W1,2,15,16
W3,4
m)
34.85
m)
W5,6,7,8, 11,12,13,14
W9,10 ( m)
23
m)
47.15
49.9
40
41
42
2.9
FULL
DIFERENTIAL
FOLDED
CASCODE
GAIN
r (g
r (A
+ 1) + 1) + g
(2.28)
r (A
+ 1) + 1)r
+r
(2.29)
43
Vx
44
Values
3.3
Channel Length ( m)
W1,2
m)
600
W3,4
m)
100
W5,6
m)
200
W7,8,11
W9,10
m)
m)
80
40
V1 (m V)
600
Bias (V)
0.8
Vcmfbp (V)
Vcmfbn (V)
0.7
Offset
0.9
45
single stage structure and difficulties found in using two stage structures at
high speed. The cascode device decreases the output voltage swing. So, the
gain boosting stages are developed to increase the output impedance without
adding more cascode devices. In contrast to two stage OTA where the entire
signal experience the poles associated with each stage, the signal directly
follows through the cascode devices in a gain boosting OTA. So, the extra
stage does not change the original unity gain bandwidth.
In order to increase the gain of the OTA an N-type folded cascode
amplifier has been used to increase the impedance of PMOS part of the main
FDFCGB OTA and a P-type folded cascode stage has been used to increase
the impedance of NMOS part of the main FDFCGB OTA (Zarifi et al 2007).
The schematic diagram of the NMOS and PMOS boosting stage is shown in
Figure 2.18 (a) and (b) respectively. In both the boosting stages, the input
transistors M1 and M2 act as transconductors and convert applied input
voltage to output current. The transistors M3, M4, M5 and M6 act as load for
OTA (Behzad Razavi 2002). BN1/BP1, BN2/BP2, BN3/BP3, BN4/BP4 and
BN5/BP5 provide bias voltages for designing the OTA. Design parameters for
NMOS and PMOS boosting stage are listed in Table 2.8. The simulated
results of the NMOS and PMOS boosting stage are given in Table 2.9.
46
47
Vdd (V)
3.3
Vdd (V)
3.3
Channel Length ( m)
0.35
Channel Length ( m)
0.35
W1,2
500
W1,2
m)
800
20
W3,4
m)
40
10
W5,6
m)
60
BN1 (mV)
40
W7,8,9,10
10
BN2 (mV)
600
W11
50
BN3 (mV)
0.8
BP1,BP5 (mV)
2.8
BN4 (mV)
BP2 (mV)
2.4
BN5 (mV)
0.7
BP3 (mV)
0.8
BP4 (mV)
0.63
m)
W3,4,5,6,11
m)
W7,8,9,10
m)
Values
NMOS
Boosting
PMOS
Boosting
FDFCGB
OTA
DC Gain (dB)
55
61
100
GBW (MHz)
40
60
850
Offset (V)
2.8
2.5
0.9
CMRR (dB)
85
80
110
PSRR (dB)
90
80
140
Transconductance ( S)
295
70
1700
SR (V / s)
0.12
0.05
0.251
THD @fc
0.55%
0.55%
0.85%
HD3 (dB)
-63
-75
-53
3.3
3.3
3.3
1.6
1.7
(CL =2 pF)
48
The Table 2.9 lists all the performance parameters calculated for
the NMOS and PMOS boosting stages individually along with the folded
cascode gain boosted OTA. The gain boosted OTA has a maximum gain
when compared to all the other OTAs in literature but with increased power
consumption. As the objective is to design an OTA for low power
applications, gain boosted OTAs are utilized only for certain unique
application where there is a trade off for power. Hence, fully differential high
performances OTA has been proposed using folded cascode architecture as it
can operate at reduced supply voltage and yields low power with gain
comparable to telescopic structure with large unity gain bandwidth.
2.10
differential signal voltages, but does not affect the common mode voltages. It
49
P2
Vout+
MF1
MF2
Cs
Ca
P1
P2
MF3
MF4
P2
P1
MF5
MF6
Vout-
Ca
Vcmfb
VDD
Itune
Cs
P2
P1
MF7
MF8
MF9
VSS
50
signals applied to the MOS transistors in the CMFB circuit which act as
switches. By varying the Itune, the tuning range of the OTA is varied to
accommodate a wider frequency range in the filter. The MOSFET design
specifications are given in Table 2.10.
Table 2.10 Design Parameters of SC CMFB
Parameters
CS (pF)
0.01
Ca (pF)
0.1
Itune ( A)
15
Vref (V)
0.65
Channel Length ( m)
0.5
W1,2,3,4
W5,6,7,8,9
2.11
Values
m)
m)
6
6
transistors as it is the first stage that provides the largest gain. Since, an
NMOS transistor exhibits a higher transconductance than a PMOS transistor,
an NMOS pair is chosen in the input differential pair to provide gain of the
OTA. This is due to the fact that the mobility of NMOS device is larger than a
PMOS device for a comparable device dimensions and bias currents. Here, a
fully differential folded cascode OTA has been proposed with NMOS as the
input differential stage because of its greater mobility and higher
transconductance.
51
2.11.1
Architecture Analysis
The folded cascode OTA has a differential stage consisting of
NMOS transistors M9 and M10. Transistors M11, M12, M13 and M14
provide the DC bias voltages to M8, M2, M4, M6 transistors as shown in
Figure 2.20. Cascode transistors M3, M4, M5, M6 are controlled by
transistors M13 and M14 respectively, which is not present in the
conventional fully differential folded cascode OTA 1. There is symmetric
nature between the transistors M3 and M5.The open-loop voltage gain and
gain bandwidth are given in Equations (2.30) and (2.31) below
A =g
(g
r r
(g
r (r
r ))
(2.30)
GBW =
(2.31)
Where, gm3, gm5 and gm9 are the transconductances of transistors M3, M5 and
M9 and CL is the output node capacitance respectively.
VDD
M1
M2
M12
M3
M4
M13
Vout+
Vout-
CL
V+
M9
M10
M5
M6
Ibias
CL
VM14
Ibias
M7
M8
M11
VSS
52
PSSR =
(2.32)
where
= (R
+R
=r g
+r
(R
R r g
+r )
(2.33)
(2.34)
= r
(2.35)
=r r g
(2.36)
Where r01, r03, r05, r07 and r09 are the drain-source resistances of transistors
M1, M3, M5, M7 and M9 respectively. The slew rate (SR) can be written as
SR =
(2.37)
(2.38)
Sizing Algorithm
In this section, same design procedure introduced by Silveira
(1996) is applied based on the gm/ID methodology. The aim is to determine the
values of the design parameters that optimize an objective feature while
satisfying specific constraints. The top-down design flow methodology for
CMOS OTA architecture is shown in Figure 2.21.
53
g
I
I
W
L
(2.39)
54
g
I
I
W
L
(2.40)
Values
CL (pF)
0.1
Ibias ( A)
15
Vdd/Vss (V)
Channel Length ( m)
W1,2,12
W3,4
W5,6,7,8
m)
m)
m)
10.8
5.4
2
W9,10 ( m)
14
W11 ( m)
55
56
parameters
like
output
swing,
power
consumption,
transconductance, CMRR, PSRR etc. of these OTAs are improved and are
comparable to OTAs in literature. These OTAs are less complex in design
and achieves a higher gain. Various OTAs such as two stage OTA and single
stage OTAs with single ended output and differential outputs are designed
and simulated. The performance comparison among these OTAs are
tabulated in Table 2.12.
Specification
(CL = 0.1 pF)
SE Folded
FD Folded
FD
SE Folded
SE Telescopic SE Telescopic
Telescopic
OTA
cascode
OTA Wilson OTA cascode
OTA cascode
OTA
Wilson
OTA 1
Houda et al Houda et al
Houda et al
Razavi et al Houda et al
Houda et al
2006
2006
2006
2002
2006
2008a
FD Folded
cascode
Proposed FD
Folded cascode
OTA 2
OTA
Houda et al
2008
DC Gain (dB)
84.8
83.2
77
84
84
75.3
79.8
86.4
270
111
181
160
107
873
946
304
Offset (mV)
0.45
0.63
0.96
0.1
1.0
0.49
4.81
83.3
CMRR (dB)
128
128
114
187
195
158
127
164
PSRR (dB)
84.8
84.8
97
104
110
84.4
119
129
Trans conductance ( S)
197
197
28.1
102
103
330
327
105
SR (V / s)
827
328
26.7
120
101
355
168
78.7
1.8
Bias current ( A)
30
15
15
15
15
60
15
0.21
0.19
0.04
0.12
0.11
0.49
0.27
0.16
3.24
3.75
1.24
1.00
0.88
8.89
3.21
4.49
69
57
58
59
and implemented with the single second order section in this chapter, using
the proposed folded cascode OTA. The circuit realization proposed by Uwe et
nd
al (2003) is used for implementation of the 2 order low pass filter because of
its advantages in design and layout. Four OTA blocks are used to develop the
nd
2 order low pass filter, as shown in Figure 2.26. All filter stages operate with
one common bias generating circuit, which improves the matching between
the filter stages over the tuning range.
2C 1
+Vi
gm1
-Vi
2C 2
g m2
+
+Vo
g m3
+
2C 1
g m4
2C 2
-Vo
H(s) =
(2.41)
H(s) =
(2.42)
60
H(s) =
(2.43)
Where
Q=
(2.44)
(2.45)
2K
(2.46)
of the 2nd order filter from (2.42) and (2.43)
is
g
= 1.848 g
(2.47)
The parameters
obtained are tabulated in Table 2.13. The filters cutoff frequency is found to
be 2.53 MHz with 1 mW of power and -50.7 dB THD.
61
Performance
Technology
0.35m
Supply Voltage
2V
THD @fc=2.5MHz
-50.7dB
Power
1mW
Tuning Range
50KHZ-2.5MHz
The 2nd order Gm- C Bi-quad Low Pass Filter implemented with
the proposed fully differential Folded Cascode OTA exhibits a wide tuning
range from 50 kHz to 2.5 MHz and supports wireless standards like GSM,
UMTS and WCDMA.
62
2.13
CONCLUSION
Different architectures of single and fully differential Operational