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Custom Integrated Circuits Conference
Custom Integrated Circuits Conference
Custom Integrated Circuits Conference
Sabio Labs, Palo Alto, CA, 2Marvell Semiconductor, Sunnyvale, CA, 3ATI Technologies, Santa Clara, CA,
4
Synopsys, Hillsboro, OR, 5Cypress Semiconductor, San Jose, CA
Abstract
This work presents a differential ring oscillator architecture
along with a design methodology that yields a compact, wellmatched layout. A process independent attribute called the
effective number of stages quantifies performance trade-offs
in speed, jitter and power consumption. Design guidelines
eliminate undesired modes of operation and guarantee robust
differential oscillation. Theoretical predictions for four, five
and six stage oscillators agree with measurements of CMOS
90nm and 0.13m implementations operating from 25 MHz
to 6 GHz.
Keywords: Differential Ring Oscillator, CMOS VCO, Jitter
and Multiphase.
Introduction
CMOS ring oscillators are ubiquitous in clocking and datarecovery applications [1], [2]. While single-ended rings are
well understood, easy to size and convenient to port over
processes, they are limited to an odd number of delay stages
(N), and therefore cannot provide complementary outputs. As
a result, differential ring oscillators are preferred for
multiphase clocking applications [1].
Differential operation can be realized by using delay stages
with source-coupled pairs biased by tail current sources.
However, supply rejection is compromised in this approach
because of the finite output impedance of the tail current
Fig. 1. Architecture: (a) CMOS inverter. (b) Delay stage with m inverter pairs. (c) N stage differential ring oscillator.
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nf
i =0
k i
i
i =0
( k i ) cos p + 1
i=0
N
The mode numbered p=1 corresponds to the desired
differential oscillation with 2N distinct output phases. All the
other modes exhibit N or fewer distinct phases. A negative Ap
indicates a mode that cannot be sustained. The mode
numbered p=N refers to the zero frequency (DC) state. The
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T =
Design Implications
The design methodology is independent of process
parameters and control voltage. The expressions in (1)-(4)
are functions of only the normalized drive strengths, ki, and
the number of stages, N, thereby permitting the design of
robust, easy to port oscillators. This design framework also
quantifies the limitations of previous work that relied on dual
input inverters to couple oscillators [1],[3]. For example, the
fastest (minimum Neff) theoretical implementations using only
k0 and k1 are Neff=4.6 for N=4 (k0=0.13, k1=0.87) and Neff=6.4
for N=6 (k0=0.07, k1=0.93). Interestingly, the fastest possible
two stage realization (N=2, k0=1/3, k1=2/3, Neff=3) has the
same Ne ff as that of a single-ended three stage oscillator. On
the other hand, even N implementations based only on k1 and
TABLE I
FABRICATED OSCILLATORS
Osc ID
CMOS
Process
1
2
3
4
5
6
7
8
130nm
130nm
90nm
90nm
90nm
90nm
90nm
90nm
Num
Stages
N
4
4
4
4
5
6
6
6
Transistor Fingers
total
path allocation
0
1
2
12
2
5
5
12
2
8
2
12
2
5
5
12
2
8
2
14
2
10
2
14
0
7
7
14
2
10
2
14
2
12
0
Neff
3.2
4.0
3.2
4.0
5.0
4.0
6.0
7.0
desired
p=1
2.17
1.57
2.17
1.57
1.31
1.46
1.20
1.13
Area
um^2
54x46
54x46
40x26
40x26
58x28
69x31
69x31
69x31
Sample Measurements
freq.
volt.
cur.
GHz
V
mA
2.80
1.2
4.79
2.11
1.2
3.92
5.95
1.0
5.68
4.55
1.0
5.17
3.62
1.0
5.84
4.93
1.0
8.03
3.10
1.0
6.27
2.73
1.0
5.15
Notes:
1.The drawn channel lengths of all devices are set to 160nm for osc1-osc2 and 120nm for osc3-osc8.
2.Layout area includes 10um wide control voltage and ground planes (designed to comply with electromigration and IR drop requirements) , as
well as matched interconnects, dummy poly fingers and poly fill to ensure good phase matching.
3.Oscillators with a given number of stages in a given process technology have the same area (example: osc6-osc8) as the different instances are
configured by via and contact connections.
4.The measured oscillators are loaded by the input capacitance of the buffers which drive the phase selectors and IO circuits in the test setup. The
effective fan-out is approximately 2.5 for osc1-osc2, 2.2 for osc3-osc4 and 2.0 for osc5-osc8.
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505
Conclusion
The differential ring oscillator architecture and design
methodology described in this work permit the systematic
tradeoff of speed, jitter and power consumption. The design
equations are process independent, thereby ensuring robust
operation.
Performance is quantified in terms of the
normalized drive strengths, ki, and the effective number of
stages, Neff. Theoretical predictions agree with measurements
of 90nm and 0.13m CMOS implementations operating from
25MHz to 6GHz over a wide range of control voltages and
currents. While primarily intended for CMOS inverter based
implementations, this methodology provides a general design
framework for multiphase oscillators and is valid for many
oscillator families.
Acknowledgment
The authors thank Prof. Ali Hajimiri for helpful
discussions, Cathy Chang and Becky Sun for layout, and
Xiling Shen and Matthew Parker for board design.
Note: The authors completed this work while at Barcelona
Design, CA.
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References
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