SoC Design & Its Challenges

Atul Jain

November 11, 2004

IEEE CAS (Dallas Chapter)

AJ 11/11/04

12/6/2004

SoC Design & Its Challenges

Outline
What is SoC?
Why SoCs?
Why SoC Methodology?
Design Challenges
Summary

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SoC Design & Its Challenges

What is System on a Chip (SoC)?

Application Specific Chip with:
Embedded hard/soft/firm

GPP

DSP

Memory
Peripherals
User logic Analog

processor cores
Embedded memories
Multiple peripherals
Modules interconnected via
standard busses
User logic 500K+ gates
Analog Modules (Phys,
ADC, DAC)
Application S/W for the
processor core(s)

Design Reuse a MUST for SoC success

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SoC Design & Its Challenges

Why SoCs: Potential chip-level savings?

A typical broadband application consists of following chips:

DSP, CPU, Data Converters, ASIC/FPGA (Peripherals and

Custom Logic), Ethernet PHY, and Memories.
Memory
Memory
$9 - $10

Ethernet
Phy

CPU

$1.5

$5

Number of
packages reduced
from 5 1.

DSP
$5

SoC
$16 - $24

ASIC

Data
Converters

$15 - $20

$2.5

Die area
reduction in
integrated
solution

Typical chip-level Savings of 30% - 45% using SoC!!!

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SoC Design & Its Challenges

Why SoCs?
Advanced technologies enabling more

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integration on a chip Reduced Product

Cost.
Physical size of products shrinking
Minimize number of parts on a board.
Consumer electronics requiring low cost
products More integration.
Minimize number of silicon vendors for a
product Reduced Business Cost.
Improved Reliability.
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SoC Design & Its Challenges

Why SoC Methodology?

Time-to-Market extremely important for business.
Easy integration of Intellectual Properties (IPs) from

multiple sources.
Resource management
Minimize number of Resources Required to complete a

design.
Efficiently manage resources across projects.
Share domain expertise across multi-site design teams.
Make effective use of design automation.

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Advancement in technology Handle Increased

Complexity of Integration.
Maximize Performance.
Manage Feature Creep and Engineering Changes
quickly.
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SoC Design & Its Challenges

Typical Methodologies
Waterfall Model*
Spiral Model*
Construct by Correction*

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Source: Reuse Methodology Manual For System-On-a-Chip

Designs, Michael Keating and Pierre Bricaud, Kluwer
Academic Publishers.
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SoC Design & Its Challenges

Waterfall Model
Specification

Based on traditional ASIC flow

Serial design flow, design transition

RTL Development
Functional Verification

phases in a step function.

Assumes all steps are Perfect and
NO need to revisit a completed
design phase.
Specification is Golden, NO
changes permitted without having a
major impact on design schedule.
Expects clean handoffs from one
team to the next.
Works well for ~1M gate designs.
Not suitable for large complex Deep
SubMicron (DSM) designs.

Synthesis
Timing Analysis (wireload model)
Scan Insertion & ATPG
Place & Route
Timing Analysis (with SDF)
Gate-level Sims (with SDF)
Mfg. & Test
Deliver to software and systems teams.

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SoC Design & Its Challenges

Spiral Development Model

RTL & Verification

Software

Architecture
Block Partitioning
RTL Coding
Module & Chip-level
verification
DFT Planning

Physical Design

Synthesis & Timing

Library selection
Package selection
Floorplan
Clock expansion
Placement
Routing
Signal Integrity
IR Drop Analysis

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Application Prototype
Prototype testing
Application development
Application testing

Constraints and
exceptions definition
Block-level Synthesis
Top-level Synthesis
Scan Insertion / ATPG
Static Timing Analysis

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SoC Design & Its Challenges

Construct by Correction
Used for development of UltraSPARC.
Single team took design from Architectural definition

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through Place and Route.

Engineers had to learn required tools.
Team understood impact of architectural decisions
on Area, Power, and Performance of final design.
Planned multiple passes from architecture to layout
to learn more about design.
Multiple iterations allowed the team to learn from
their mistakes and correct them in next iteration.
UltraSPARC development project was one of the
most successful in Sun Microsystems history.
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SoC Design & Its Challenges

Design Start
Design Specification
Library selection

Target technology node

Frequency and Power limits
Layout density entitlement
IP Selection
Hard vs. Soft Macro
Internal vs. external IP
Embedded RAMs/ROMs
PLLs & Analog blocks
Custom Cells (if needed)
Chip-level Power estimation
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SoC Design & Its Challenges

Design Start (contd)

Selection of verification environment.
Selection of configuration management

environment.
IO Selection.
Package Selection.
Die size estimate tradeoffs

Preliminary floorplan
IO limited vs. Core limited vs. Megamodule
limited vs. Package limited

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SoC Design & Its Challenges

Challenges for DSM designs

Reusable IP deliverables.
Design prototyping & partitioning.
Process variations impact on timing analysis.
Cross talk noise.
Voltage drop & power management.
Design management.

Design Planning essential for all of the above.

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SoC Design & Its Challenges

Hard IP
Need to support the following models:
Floorplanning
Functional
Physical Design
Timing
Software tools for
Synthesis
processor core
DFT
Scan hookup requirements
Clock insertion delay numbers and skew

requirements
Power requirements
Integration/Test documentation
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SoC Design & Its Challenges

Soft IP
Synthesizable RTL
Functional Verification

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Coverage metrics
models to speed-up verification
Synthesis / Timing Analysis
Timing exceptions and constraints
Clock and Reset requirements
Critical paths should be documented
DFT scripts
Physical design
Memory placement guidelines
Special clock handling requirements
Software tools for processor cores
Implementation and integration documentation
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SoC Design & Its Challenges

Design Prototyping & Partitioning

Hardware vs. Software tradeoffs
Prototyping Early assessment of design

planning decisions
Partitioning designs into subchips or
hierarchical modules
Flat vs. Physical hierarchy decisions
Partitioning is needed to
Meet Area, Timing, and Power budgets.
Minimize top-level logic and routes.

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SoC Design & Its Challenges

Design Partitioning: Example

RAM
RAM

RAM
RAM

RAM
RAMRAM
RAM

SubChip4
SubChip4

SubChip3
SubChip3

0.8M logic gates

RAM
RAM
1.6M logic gates
ROM

5M
RAM
RAM

gates of
logic +
RAM
processorRAM SubChip2
SubChip2
RAM
RAM
Core +
Memories

1.1M logic gates

0.5M logic gates

RAM
RAM

0.4M logic gates

@ 250 MHz

CORE
CORE

RAM
RAM
RAM
RAM

SubChip1
SubChip1

0.6M logic gates

@ 125 MHz

Divide and Conquer approach for partitioning the design into

several smaller blocks.
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SoC Design & Its Challenges

Timing Analysis for Process Variability

Typical observations in DSM and sub-nanometer

regime:
Parameters (Leff, VT, Tox, etc.) across chips (inter-die) are
different.
Parameters within the same chip (intra-die) are also different.
Why?

Feature size is getting smaller than Lithography Wavelength

Some mask information is lost.
Critical dimensions are scaling faster Less Control.
Back End Of Line (BEOL) variability.
Across Chip Line-width Variations (ACLV).
Across-the-chip temperature and VDD variation.

Designers and Business goals require as many chips

as possible to work.
NanoNano-CMOS Circuit and Physical Design, Ban Wong, Anurag Mittal,
Mittal, Yu Cao,
Cao, Greg Starr, ISBN:0ISBN:0-471471-4661046610-7

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SoC Design & Its Challenges

Interconnect variation - Net delays, Path

delays are f(P)
CNET= fcap(P0, P1, P2, )
DELAYNET= fnet(P0, P1, P2, )
P5
P4 Pitch is well controlled
These dimensions
can vary
independently

P2

Width and
spacing are not
independent

P3

P1
P0
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SoC Design & Its Challenges

OCV Analysis
Cannot assume constant PTV across die Essential

to comprehend impact of these variations in timing

analysis.
STA tools support OCV analysis mode
Compute min and max delays for cells and nets by

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multiplying annotated delay with min and max timing de-rate

value, respectively.
Apply min and max delays to different paths simultaneously.
For setup check, annotate worst case SDF. Use max delay
for launch path and min delay for capture path.
For hold check, annotate best case SDF. Use min delay for
launch path and max delay for capture path.

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SoC Design & Its Challenges

Crosstalk Analysis
Wire aspect ratio changes for DSM

technologies.

Cc

Cc

Cs

Cs

0.5 m

0.13 m

Coupling capacitance has gone up with

shrink in feature size.

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SoC Design & Its Challenges

Crosstalk Effects
Crosstalk affects the circuits in two ways:

Functionality and Timing.

Suffering from noise

Glitch propagation
Victim

problem.

Glitches on Clocks

Aggressor

Contributing
noise

can be a real
problem.
Victim

Delay Variation can

be an issue.
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Aggressor

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SoC Design & Its Challenges

Crosstalk Delay Variation: Example

Aggressor

Victim

Victim
Victim
without
with noise
noise
Vdd
Vdd

Vdd/2
Vdd/2

Aggressor/Victim net

Opposite
direction
switching

Same direction switching

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switching in same direction

leads to reduced signal
delay through the victim net.
Aggressor/Victim net
switching in opposite
direction leads to increased
signal delay through the
victim net.

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SoC Design & Its Challenges

Crosstalk Delay: Timing Window

Aggressor 1

Victim

Aggressor 2

Victim
Crosstalk
VictimNet
NetDelay
Delaywithout
with Crosstalk
Victim

Aggressor 1
Aggressor 2

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SoC Design & Its Challenges

Effects of Crosstalk Delay

Delay changes due to affect of switching

aggressor net on victim net needs to be

comprehended:

During setup check worst case condition

capture clock is faster; data path and launch clock
are delayed.

During hold check worst case condition

capture clock is slower; data path and launch clock
are speedup.

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SoC Design & Its Challenges

How to Manage Crosstalk?

Ensure transition timing window for coupling

nets do not overlap.

For heavily loaded nets improve transition
time.
Minimize use of low drive cells.
For clocks, shield to minimize coupling.
Use Physical Design tools capabilities of
avoiding crosstalk during detail route.

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SoC Design & Its Challenges

Power Management Trends

250

Power (W)

200

40-50% is leakage
power

150
100
50
0
0.25

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0.18

0.13

0.09

0.065

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Leakage Power
Active Power

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SoC Design & Its Challenges

Power Management Motivation

Active or Dynamic Power

Pdynamic = Pswitching + Pshort-circuit

Pswitching: Primarily due to actively changing states of the
circuit due to constantly charging and discharging of the
effective capacitive loads

Pswitching = Switching Activity x freq x Ceff x Vdd2

Clock power is the largest contributor (nearly 75%)
Interconnect is the largest consumer

Pshort-circuit: Momentary crowbar current flowing between

VDD and GND when transistor stacks switch state

Leakage or Static Power

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Primarily contributed by source-to-drain leakage current that

increases with lowering VT (threshold) and increasing
temperature.
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SoC Design & Its Challenges

Dynamic Power Management Techniques

Clock Gating

Selectively turn OFF registers when not needed.

Power Gating
Shut OFF power to blocks in stand-by mode.
Retention flip-flops (on an isolated power supply) can be

used to save the logic state of all sequential elements when

the chip is powered down.
Eliminates need to re-initialize the device when coming out
of stand-by mode.

Power-aware Physical design

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Reduce capacitive loading by down-sizing gates.

Minimize wire length.

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SoC Design & Its Challenges

Voltage Islands

Partition design into:

High speed blocks fed by higher voltage.

Low speed blocks fed by lower voltage.

Need Level Shifters (LS) between blocks operating at different

voltage levels and ensure correctness of LS connectivity.
V1
V1
1.2V
1.2V
250
250 MHz
MHz

V2
V2
1.5V
1.5V
300MHz
300MHz
LS
V3
V3 (0.8V)
(0.8V)
150
150 MHz
MHz
LS

CORE
CORE

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V2
V2 (1.5V)
(1.5V)
300
300 MHz
MHz

Need Scaleable Polynomial Library (SPM) support

Additional careabouts related to scan stitching and clock
distribution required.
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SoC Design & Its Challenges

Design Management
Configuration management
Paramount for Multi-site development

Design and Scope changes

Feature Creep
Process Requirement Changes
Test and Reliability Requirement Changes.

External deliverables, e.g., IPs, custom cell.

Handoffs and milestones
Design Milestones, e.g., RTL freeze, Initial synthesis,
tapeout.
Design team (or customer) handoffs.

Optimize engineering and compute resources.

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SoC Design & Its Challenges

Summary
Robust Design Methodology needed for

success of SoCs.
Design Reuse and Automation essential
ingredients.
Different methodologies followed in the
industry:

Waterfall Model
Spiral Design Model
Construction By Correction

SoC challenges can be handled effectively

with Design Planning and Management.

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