Department of Electrical and Computer Engineering

332:428 Capstone Design - Communications Systems Spring 2010

Novel Two-Way Car Alarm Responder System

Final Project Report

Group Members:
Matt Elder
Ryan Ginter

May 12, 2010

Table of Contents

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1. Design Project Overview
Most car alarm systems today are designed to simply alert people in the vicinity
of the car with the intention to scare any vandal or thief away from the car. While this
common alarm system is somewhat effective it has a lot of room for improvement. A
loud car alarm may draw attention to the target car, but normally the attention it draws is
negative. People become annoyed as car alarms continuously sound for hours before the
owner actually comes to the car to reset the alarm. Along with this aggravation, very few
people show much concern for a person’s car when a car alarm goes off, unless it is their
own car or that of a close friend.

To prevent these issues car alarm systems have started to become more direct
with their alerts. When the owner of the car can be directly alerted by the car, even when
out of hearing range from the car, the owner can respond much quicker. This prevents
prolonged public disturbances, and gives quick real-time alerts to the person most
concerned with the car’s status, its owner.

The one problem with current systems is that they are very expensive, ranging up
to $200 or more. The system in this project provides the same major capabilities of these
expensive systems, but at a much lower end-user cost. This is accomplished by
simplifying and customizing the internal workings of such direct car alarm systems, thus
removing expensive and unnecessary hardware components. Further this system uses
direct sequence spread spectrum techniques to provide secure transmissions, that are
resistant to both jamming and inter-user interference. Other features include the ability to
have up to four sensors, and a direct indication of the exact sensor that has been tripped
via LED alerts. Also Hamming coding methods are used to correct bit errors that may
occur during the data transmission.

For this project specifically only the communication between the car and user has
been prototyped, providing the direct alerts necessary to convey car troubles to the end-
user. The full system would also involve controls that the user can use to reset the car
alarm, or kill the engine. This addition is simply a replication of the current prototype, but
the data would be generated with buttons the user has control of, rather than car sensors.
And instead of alerts being received by the user, the car receives the data and responds by
resetting the alarm or killing the engine. The baseband communications remain the same
along with the RF systems used to convey the data in this full duplex system.

While this system is not a perfect substitute to current systems, it does provide an
effective alternative at a lower cost. This product is ideal for the user who values
functional security and low cost over expensive aesthetic appeals. The following report

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goes into more detail of the system and the processes involve with creating and
implementing the system.

2. Technical Specifications
• Chipping rate of 10,000 chips/sec
• PN sequence repetition after 127 cycles
• BPSK modulation at center frequency of 10 kHz
• BPSK bandwidth of 20 kHz
• BPSK band power of 12.6 dBm at Vcc = 5 Vdc
• DSSS band power of 11 dBm at Vcc = 5 Vdc
• Wireless OOK transmission centered at 433 MHz
• Wireless OOK transmission band power of up to 10 dBm
• Wireless range of 3,000 ft
• Two sensor prototype using sensors to check if window is broken or someone has
pulled on the car handle
• Error free transmissions when baseband clocks are at the same frequency.
• Error correction when clocks are not synchronized ranging from +10 Hz and –13
Hz around the expected clock frequency of 160 Hz
• Data rate ranging from 10bps to 100 bps
• Baseband average power consumption of 3.122 mW
• Expandable to four sensors with the additional two sensors being used for
identifying bumping of the car and ignition of the car’s engine
• Expandable data rate up to 2 kbps
• Expandable addition of speaker alert possible

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 3. Final Project Summary

3.1 System Design – Final Version

This section lays out the high-level final system design. The following block
diagrams highlight the key components of each of the major subsystem, and the signals
communicated between these systems. Following each major subsystem’s overview
block diagram smaller internal subsystems will be listed and described if further
elaboration is necessary. Also note that the major subsystems will be described in the
order of sensor data generation at the car through recovery of data and alert at the user’s
responder.

Directional Flow of Sensor Transmissions

Car Sensor
Subsystem Baseband Transmit Data Subsystem

Framing& DSSS Transmit

Sensor Hamming
Parallel Data Subsystem
1 Parity Bit
↓ via
Generator PN Sequence #1 Transmitter 1
Serial

Responder
Sensor
2 Baseband Received Data Subsystem LED
1
DSSS Received Sampling&
Error
Data Subsystem Serial
Detection &
via ↓
Receiver 1 Correction
PN Sequence #1 Parallel
LED
2

Baseband Received Data Subsystem

Sampling & DSSS Received

Error
Serial Data Subsystem
Detection & Reset
↓ via
Correction Receiver 2 Button
Parallel PN Sequence #2

Baseband Transmit Data Subsystem

DSSS Transmit Framing &

Hamming
Data Subsystem Parallel
Parity Bit
via ↓
Transmitter 2 Generator
PN Sequence #2 Serial

Directional Flow of Responder Transmissions

Fig. 3.1.1: Final Overall System Block Diagram.

In the final system data generated in parallel by the car’s sensors are sent serially,
with the addition of Hamming parity bits. It also has a start and stop bit added to frame
the data, allowing for asynchronous data recovery. The serial data is then spread using a
pseudorandom sequence. This sequence is then further modulated using Binary Phase

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 Shift Keying (BPSK), and sent to the end user. Upon receiving the BPSK signal it is
demodulated and despread. The data is then fully recovered, checked for errors, and made
aware to the user via LEDs. While the overall system prototyped implements the car-to-
user communication, in the final system the user would communicate control signals
back to the car in the same process as shown in the diagram. Note to provide this full
duplex communications at 433 MHz carrier is used along with two different
pseudorandom noise (PN) sequences, one for each direction of communication.

Parity Bits
Hamming P1-P3
Parity
Generator
Sensor Data D1-D4

Framing of Serial Data

Data & [0 D1 D2 D3 D4 P1 P2 P3 1] To
Sensor Data D 1-D4
Parallel -Serial DSSS
Conversion

TX NTX
Sensors
Trigger

Fig. 3.1.2: Baseband Transmit Data Subsystem Overview Block Diagram.

The Baseband Transmit Data Subsystem contains the Sensors, Hamming Parity
Generator, Transmission Trigger, and the Framing and Parallel-to-Serial Conversion
Subsystems. Together these subsystems take the parallel data generated by the car
sensors and transmit them in a serial stream to the DSSS Subsystem with the addition of
Hamming parity bits and a start and stop bit to frame the data.

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 No Need
To Hamming To
Parity Generator Transmit .
& Parallel-Serial Ignore.
Yes

Indicate
Data D1-D4 Same No NTX To Framing/
From the Need
Sensors
Information Parallel-Serial
To Converter
?
Data D1-D4

Transmit.

Hold
Register Previous Data
Local D1' – D4'
Clock
CLK

Fig. 3.1.3: Transmission Triggering Subsystem Block Diagram.

The Transmission Triggering Subsystem takes the data generated by the sensors and
compares it with the data from the previous clock cycle. If there is no change in the data
then there is no new information, and the data is not transmitted. If there is new
information then the Framing and Parallel-to-Serial Converter Subsystem are initiated by
toggling the Need to Transmit (NTX) signal.

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 Local
Clock TCK
CLK
Load & Transmit
TLD

TCK =
CLK/16 Stop
Frequency Data Load/Send Serial Data
Bit
Divider Control [0 D1 D2 D3 D4 P1 P2 P3 1]
Parallel -Serial To
Shift Register DSSS

From TX NTX TX Busy

Trigger Feedback

Parity Bits
P1-P3
From Parity Bits P1-P3
Sensors &
Hold Data D1-D4
Hamming
Parity Bit Register
Data Bits D1-D4
Generator Start
Bit

Fig. 3.1.4: Framing and Parallel-to-Serial Converter Subsystem Block Diagram.

The Framing and Parallel-to-Serial Subsystem have the sensor data and Hamming
parity bits as parallel inputs. These inputs are passed to the inputs of a parallel-to-serial
shift register if a NTX signal is toggled. This parallel-to-serial shift register has a start bit
always set to zero and a stop bit always set to one. The data and parity bits are input
between the start and stop bit to accomplish the framing of the data. The parallel-to-serial
process does not start until the Data Load and Send Control toggles the Transmit and
Load (TLD) signal. This signal is toggled after the NTX signal is toggled, however after
a transmission starts if NTX is toggled again the TLD signal will not be toggled until the
current data is done being sent. The output the framed serial stream of data is sent to the
DSSS Subsystem to be spread. This output is clocked at a data rate equal to the one
sixteenth of the local clock frequency.

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 DSSS Shift
OCO x DA x CA Registers
Subsystem
CA
Serial Data DSSS TX
Framing of Data [0 D1 D2 D3 D4 P1 P2 P3 1]
Subsystem
& Parallel -Serial
Conversion CA
[Serial Data = DA]
Wireless
OCO x DA
Transmit Data
Subsystem

Fig. 3.1.5: DSSS Transmit Data Subsystem Overview Block Diagram.

The DSSS Transmit Data Subsystem contains the DSSS TX Subsystem. This
subsystem uses input Serial Data generated by the Framing of Data & Parallel-Serial
Conversion Subsystem and produces BPSK modulated data DA and a reference carrier
signal CA for use in DSSS Shift Registers and Wireless Transmit Data Subsystem.

Serial Data
Framing of Data [0 D1 D2 D3 D4 P1 P2 P3 1] OCO x DA x CA DSSS Shift
& Parallel-Serial Registers
Conversion Subsystem

Data Select: CA

Test Data CA
or
Serial Data OCO x DA Wireless
Test Data Transmit Data
[10 Hz Square Wave] Subsystem

20 kHz
Divide-by-2 Divide-by-1000
CLK DA

X X
CA OCO OCO x DA
PN Generator
Feedback Taps
CA

Fig. 3.1.6: DSSS TX Subsystem Block Diagram.

The DSSS TX Subsystem is the system’s baseband direct-sequence spread spectrum
(DSSS) processor. This subsystem receives Serial Data from Framing of Data & Parallel-
Serial Conversion Subsystem and feeds it to a switch Data Select. Data Select is placed in
this subsystem to allow the experimenter to define DA as either a steady 10 Hz square
wave produced from the Divide-By-1000 stage or as the external received Serial Data via
a simple SPDT switch. Defining DA as a 10 Hz square wave is useful for testing
purposes only. Serial Data input must be selected for DA during standard operation. A
PN generator is present with physical feedback taps at particular pins of PN Generator in
order to provide a unique pseudo-random sequence OCO which will be used to spread the

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 baseband signal DA for transmission. The first XOR stage modulo-2 adds DA with OCO
producing direct-sequence spread OCO x DA, which is fed to the Wireless Transmit Data
Subsystem and to the next XOR stage for BPSK modulation and transport. This final
XOR stage modulo-2 adds CA and OCO x DA to produce BPSK OCO x DA x CA ready
for transport to DSSS Shift Registers Subsystem.

DSSS Sync
Subsystem
VAR_CLOCK

DSSS TX
Subsystem CA
SYNC’
OCO x DA x CA Serial Data
DSSS Shift DSSS Demod
[0 D1 D2 D3 D4 P1 P2 P3 1] Baseband
Registers CA Subsystem
Received Data
OCO x DA Subsystem Subsystem
[DA = Serial Data]
Wireless CA LCO
Received Data
Subsystem

Fig. 3.1.7: DSSS Received Data Subsystem Overview Block Diagram.

The DSSS Received Data Subsystem contains the DSSS Shift Registers, DSSS
Synchronization, and DSSS Demodulation Subsystem. This subsystem receives CA and
BPSK modulated DA generated by DSSS TX Subsystem. This subsystem also receives
CA and direct-sequence spread DA from Wireless Received Data Subsystem. With these
inputs the subsystem produces a demodulated and dispread estimate of DA.

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 DSSS TX
Subsystem

OCO x DA x CA CA

Shift Register

7 outputs 2x4
outputs 2 outputs NOR SYNC’
XOR DSSS Sync
OR and Subsystem
Stage
Feedback 7 outputs Stage XOR
Taps Stage

Local PN Generator

LCO VAR _CLOCK

DSSS Demod DSSS Sync

Subsystem Subsystem

Fig. 3.1.8: DSSS Shift Registers Subsystem Block Diagram.

Accepting various inputs from other subsystems, the Shift Register’s Subsystem
primary function is to check the logic of the output of a Local PN Generator with a Shift
Register fed by the output of DSSS TX Subsystem. The input to Shift Register contains
OCO which is the original transmitting PN Sequence. The goal of this subsystem is to
compare the outputs of Shift Register and Local PN Generator. When they are
synchronized, output SYNC’ to DSSS Synchronization Subsystem will go to a logic zero

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 Logic Q’
1 Reset Switch

Q’ DSSS Shift
DSSS Shift Registers
RS Latch
Registers Subsystem
Subsystem SYNC’
Bilateral Switch
VAR_CLOCK
VAR_CLOCK Set

2 x CA
DSSS TX CA DSSS Demod
Multiply -by-two Subsystem
Subsystem

Fig. 3.1.9: DSSS Synchronization Subsystem Block Diagram.

DSSS Synchronization Subsystem receives inputs SYNC’ and CA and outputs
VAR_CLOCK dependent on the value of SYNC’. Q’ resets to value logic 1 on startup
when SYNC’ is high and when Q’ Reset Switch is pressed. Q’ is set to logic 0 when
SYNC’ goes low, indicating synchronization of PN sequences LCO = OCO from Shift
Registers Subsystem. The Bilateral Switch defines VAR_CLOCK as (2 x CA) when Q’
is high and CA when Q’ is low. VAR_CLOCK is used in DSSS Shift Registers to clock
Local PN Generator and in the DSSS Demodulation Subsystem to recover DA.

OCO x DA x CA
DSSS TX
Subsystem

CA DA_est Amplifier DA Baseband

XOR Balanced Modulator Received Data
CA x LCO & LPF
Subsystem

DSSS Shift LCO

Registers
Subsystem

Fig. 3.1.10: DSSS Demodulation Subsystem Block Diagram.

The DSSS Demodulation Subsystem takes BPSK input OCO x DA x CA into
Balanced Modulator. Inputs CA and LCO modulo-2 are connected to a XOR gate to
produce CA x LCO, which is input to the Balanced Modulator. The Balanced Modulator
demodulates and outputs DA_est, which is a low power estimate of DA. DA_est is
shaped and boosted via Amplifier & LPF stage to recover DA.

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