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Topic 3 CMOS Fabrication Process: Peter Cheung Department of Electrical & Electronic Engineering Imperial College London
Topic 3 CMOS Fabrication Process: Peter Cheung Department of Electrical & Electronic Engineering Imperial College London
URL: www.ee.ic.ac.uk/pcheung/
E-mail: p.cheung@ic.ac.uk
PYKC Nov-27-09
Lecture 3 - 1
Layout of a Inverter
VDD
Qp
vo
vi
Qn
GND
PYKC Nov-27-09
Lecture 3 - 2
Lecture 3 - 3
Silicon Wafer
Silicon Wafer
Lecture 3 - 4
Phosphorous Diffusion
SiO2
p-substrate
Phosphorous is
diffused into the
unmasked regions of
silicon creating an n
-well for the fabrication
of p-channel devices
PYKC Nov-27-09
n-well
p-substrate
Lecture 3 - 5
Photoresist
SiO2
Photoresist
n-well
p-substrate
A thick field oxide is grown using a
contruction technique called Local Oxidation
Of Silicon (LOCOS).
SiO2
The thick oxide regions
provides isolation
between the MOSFETs
PYKC Nov-27-09
n-well
p-substrate
E4.20 Digital IC Design
Lecture 3 - 6
Thin Oxide
SiO2
n-well
p-substrate
Lecture 3 - 7
Mask 4: n+ Diffusion
Mask 4 is used to
control a heavy arsenic
implant and create the
source and drain of the
n-channel devices.
This is a self-aligned
structure.
Arsenic Implant
Photoresist
SiO2
n-well
p-substrate
The polysilicon gate acts like a barrier for this
implant to protect the channel region.
n+
n+
SiO2
n+
n-well
p-substrate
PYKC Nov-27-09
Lecture 3 - 8
Mask 5: p+ Diffusion
Mask 5 is used to
control a heavy Boron
implant and create the
source and drain of the
n-channel devices.
This is a self-aligned
structure.
Boron Implant
Photoresist
SiO2
n-well
p-substrate
The polysilicon gate acts like a barrier for this
implant to protect the channel region.
p+ n+
n+
SiO2
p+
p+ n+
n-well
p-substrate
PYKC Nov-27-09
Lecture 3 - 9
oxide
p+ n+
n+
SiO2
p+
p+ n +
n-well
p-substrate
Etched contact holes
p+ n+
n+
SiO2
p+
p+ n+
n-well
p-substrate
PYKC Nov-27-09
Lecture 3 - 10
Mask 7: Metalization
A thin layer of aluminum
is evaporated or
sputtered onto the
wafer.
Mask 7 is used to
pattern the
interconnection.
p+
n+
n+
SiO2
p+
p+ n+
n-well
p-substrate
Aluminum Interconnection
p+ n+
n+
SiO2
p+
p+ n+
n-well
p-substrate
PYKC Nov-27-09
Lecture 3 - 11
vi
vo
VDD
p+
n+
n+
p+
Qn
n+
Qp
n-well
Source-Body
Connection
p-substrate
PYKC Nov-27-09
p+
Source-Body
Connection
Lecture 3 - 12
VDD
Qp
vo
vi
Contact Hole
GND
Metal 1
PYKC Nov-27-09
Lecture 3 - 13
Dimension of transistors
n+
Poly
n+
Gate
n-well
p+
Drain
Gate
p-channel MOSFET
n-channel MOSFET
PYKC Nov-27-09
Poly
Source
Drain
Source
p+
Lecture 3 - 14
PYKC Nov-27-09
Lecture 3 - 15
PYKC Nov-27-09
Lecture 3 - 16
As shown above, the p+ region of the p-transistor, the n-well and the p- substrate form a
parasitic pnp transistor T1.
The n- well, the p- substrate and the p+ source of the n-transistor forms another parasitic
npn transistor T2.
There exists two resistors Rw and Rs due to the resistive drop in the well area and the
substrate area.
PYKC Nov-27-09
Lecture 3 - 17
Latch-up (cont)
PYKC Nov-27-09
Lecture 3 - 18