THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

ECNG 3016
ADVANCED DIGITAL ELECTRONICS
http://myelearning.sta.uwi.edu/course/view.php?id=686
Semester II 2009/2010
1.

GENERAL INFORMATION
Lab #:
Name of the Lab:

Practical 2
Frequency Division and Time Multiplexing of Displays

Lab Weighting:

0%

Delivery mode:

Lecture

Online
 Lab

Other

Venue for the Lab:

Microprocessor Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 3016

Theoretical content link: given at top of page
Pre-Requisites ECNG 2004
To undertake this lab, students should be able to:
1. Use Xilinx ISE in the implementation of digital systems
2. Describe Digital Systems using VHDL, in particular: write VHDL
code to a specified algorithm; create variables, signals and
components; and structurally map together an entity out of multiple
instantiated components

Recommended
prior knowledge
and skills3:

Course Staff

Position/Role

Estimated total
study hours1:

Cathy Radix

Lecturer

E-mail

Cathy.Radix@sta.uwi.tt

Azim Abdool

Instructor

azim.abdool@sta.uwi.tt

Phone
Office
Office

Hours
x3157 Rm 321, Mon/Tue
11am Blk 1
2pm
x2636 Rm 341/ Mon/
RTSG,
Thu
Blk 1
11am12pm

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

2.

LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Understand the concepts of frequency division and time multiplexing of
displays
2. Design and implement a frequency divider in VHDL to meet a required
specification
3. Design and implement a Time Multiplexing display unit to meet a required
specification using a simple state machine architecture

3. PRE-LAB
Due Date:
Submission
Procedure:
Estimated time to
completion:

Cognitive
Level
C
Ap
Ap

In lab with laboratory exercise.

3 hours

Write a frequency divider module that has an interface taking an input clock signal of 50MHz and
outputting a divided signal of 1kHz as well as 1Hz.

1. The frequency divider would implement the following given algorithm to produce a 1kHz
signal.
frequency_divider_ms(clock)
temporary variable cnt defined from 0 to 25000
begin
if a rising edge of input clock is detected
Increment cnt
if cnt = 25000 then
cnt  0

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

toggle output clock signal

end if
end if
end frequency_divider_ms

The frequency divider would implement the following second algorithm to obtain the 1Hz clock
signal.
frequency_divider_s(clock)
temporary variables i and j defined from 0 to 5000
begin
if a rising edge of input clock is detected
increment i
if i = 5000 then
i  0
increment j
if j = 5000 then
j  0
toggle output clock signal
end if
end if
end if
end frequency_divider_s

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

2. For time multiplexing of displays, we switch on a particular display while keeping all others
off. Given that on the Spartan 3 development board, there exists 4, active low, common
anode connected seven segment displays; draw a state diagram depicting a 4 bit output of a
controller unit.

Practical 2: Frequency Division and Time Multiplexing of Displays

4.

IN-LAB

Allotted Completion 3 hours

Time:
1 Computer
Required lab
1 Spartan 3 Toolkit
Equipment:
4.1. In-Lab Procedure
Write a VHDL entity that will describe a state machine control unit that has an interface:
clock, reset single input bits
anodes_o four bit output.
After creating the skeleton file for the controller unit, we will utilize the language templates to code
the state machine. The language templates provide a lot of simple coding examples for our usage.
We can use the provided templates to achieve many simple designs.
Go to Edit  Language Templates (Figure 1).

Figure 1: Going into the Language Templates

Select VHDL  Synthesis Constructs  Coding Examples  State Machines  Moore (Figure 2).

Practical 2: Frequency Division and Time Multiplexing of Displays

Figure 2: Selecting a Template

Follow the commented steps within the language template in order to code the state machine
architecture that was devised in the pre-lab. This would be a simple Moore state machine in VHDL
to look up the particular states of the anodes.
Synthesize your result and ensure that it builds correctly.
Add your frequency divider source that was created during the pre-lab to the current project. Ensure
that it gives no syntactual errors.

Practical 2: Frequency Division and Time Multiplexing of Displays

Create an entity called scrolling_msg_system which would have an interface:

clock, reset, enable single input bits
anodes four bit output
sseg 7 bit output
and a structurally created architecture which implements the following circuit (Figure 3). The circuit
components up_counter, adder_3bits, encode_anodes and decode_7seg are given.

Practical 2: Frequency Division and Time Multiplexing of Displays

Figure 3: Scrolling Message System Structure

Note that the connection between the encode_anodes component and the adder_3bits component
entail a 2 bit output going to a 3 bit input. The 2 bit output of encode_anodes should be connected to
the two less significant bits of the input of adder_3bits and the uppermost bit grounded off/cleared.
8

Practical 2: Frequency Division and Time Multiplexing of Displays

After finishing the creation of the scrolling_msg_system, implement it using the pin constraints
given in Table 1.
Table 1: Pin Constraints

Design Port

FPGA Pin to be mapped to

clock
reset
clock_enable
anodes(0)
anodes(1)
anodes(2)
anodes(3)
sseg(0)
sseg(1)
sseg(2)
sseg(3)
sseg(4)
sseg(5)
sseg(6)

T9
any available pushbutton
any available switch
D14
G14
F14
E13
E14
G13
N15
P15
R16
F13
N16

Download the solution on to the development board.

Ensure that clock_enable is set to 1 (depending on the particular switch that you have used).
Does the system scroll through a message?
How can you extend this system to:

utilize a greater number of seven segment displays?

display another (longer/shorter) message?

Proceed to post-lab exercise.

Practical 2: Frequency Division and Time Multiplexing of Displays

5.

POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date:
Submission
Procedure:
Deliverables:

Not Applicable
-

End of Practical 2: Frequency Division and Time Multiplexing of Displays

10

Practical 2: Frequency Division and Time Multiplexing of Displays

6.

APPENDIX TIME MULTIPLEXING OF DISPLAYS

Seven-segment displays are now widely used in almost all microprocessor-based

instruments. A single seven-segment display can display the digits from 0 to 9 and the hex digits
A to F. Each display is composed of seven LEDs that are arranged in a way to allow the display
of different digits using different combinations of LEDs Figure 4.

Figure 4: Common anode detail

Since the display is composed of LEDs, which need high current to drive them, power
consumption is very critical. Consider a panel with 4 displays and the number to be displayed is
8888. Each LED needs 20 mA. So we need a current of 20x7x4 = 560 mA. Thats a lot of current
compared to the current consumed by the microprocessor. Another problem is the number of
components and output bits that are needed to connect the displays to the processor. We need at
least 4x7 = 28 resistors and 28 output bits for the 4 displays. Is there a solution for these
problems? Yes, there is, its called MULTIPLEXING!
The Pegasus board contains a four-digit common anode seven-segment LED display. The
display is multiplexed, so only seven cathode signals exist to drive all 28 segments in the
display. Four digit-enable signals drive the common anodes and these signals determine which
digit the cathode signals illuminate Figure 5.

11

Practical 2: Frequency Division and Time Multiplexing of Displays

Figure 5: Common anode Sseg display

This connection scheme creates a multiplexed display, where driving the anode signals and
corresponding cathode patterns of each digit in a repeating, continuous succession can create the
appearance of a four-digit display. Each of the four digits will appear bright and continuously
illuminated if the digit enable signals are driven low once every 1 to 16ms (for a refresh
frequency of 1KHz to 60Hz). For example, in a 60Hz refresh scheme, each digit would be
illuminated for one quarter of the refresh cycle, or 4ms. The controller must assure that the
correct cathode pattern is present when the corresponding anode signal is driven (Figure 6).
However, this represents the cathode pattern for the shown for the given connection pattern.
These patterns would change for different connection patterns.
To illustrate the process, if AN0 is driven low while CB and CC are driven low, then a "1"
will be displayed in digit position 0. Then, if AN1 is driven low while CA, CB and CC are
driven low, then a "7" will be displayed in digit position 1. If A1 and CB, CC are driven for 4ms,
and then A2 and CA, CB, CC are driven for 4ms in an endless succession, the display will show
"17" in the first two digits. Figure 7 shows the pattern of decimal digit.

12

Practical 2: Frequency Division and Time Multiplexing of Displays

Figure 6: Sseg signal timing

Figure 7: Cathode pattern for decimal digits

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